KR101682420B1 - Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes - Google Patents

Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes Download PDF

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KR101682420B1
KR101682420B1 KR1020150088792A KR20150088792A KR101682420B1 KR 101682420 B1 KR101682420 B1 KR 101682420B1 KR 1020150088792 A KR1020150088792 A KR 1020150088792A KR 20150088792 A KR20150088792 A KR 20150088792A KR 101682420 B1 KR101682420 B1 KR 101682420B1
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silicon
hard mask
sidewall
silicon oxide
gate
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KR1020150088792A
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Korean (ko)
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최우영
김상완
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서강대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7311—Tunnel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors

Abstract

The present invention relates to a tunneling field effect transistor, and provides a method of manufacturing a self-aligned hetero-junction tunneling field effect transistor in which a hetero-junction of germanium and silicon is positioned under a sidewall gate or a sidewall insulation film using selective germanium condensation and a sidewall process.

Description

Technical Field [0001] The present invention relates to a self-aligned hetero-junction tunneling field-effect transistor using selective germanium condensation and a sidewall process, and more particularly, to a self-aligned hetero-junction tunneling field-

The present invention relates to a tunneling field effect transistor, and more particularly, to a method of manufacturing a self-aligned hetero-junction tunneling field effect transistor using selective germanium condensation and sidewall processes.

In general, the power consumption of a semiconductor device is closely related to the driving voltage. For low-power operation, reduction of the driving voltage is essential. However, in the case of conventional MOSFETs, there is a physical limitation that the subthreshold swing (SS) can not be lowered below 60 mV / dec at room temperature. Therefore, if the driving voltage is lowered, the performance degradation due to the increase of the leakage current or the decrease of the driving current is inevitable. To solve these problems, companies, research institutes and universities in advanced countries are concentrating their research efforts on the development of new high energy efficiency semiconductor devices as next generation devices.

One of the devices that are being developed as a next generation device is a tunneling field effect transistor (hereinafter referred to as " tunneling field effect transistor ") having a structure in which an asymmetric source 2 / drain 4 is formed of impurities having opposite polarities on both sides of a channel region 3 TFET).

In the case of the conventional N-channel TFET, the source 2 is connected to the P + region and the drain 4 is connected to the N + region and the drain region 4 on both sides of the channel region 3 of the intrinsic SOI substrate which is weakly doped or undoped in P- . Here, the P + region is a high-concentration doping layer of a P-type impurity and the N + region is a high-concentration doping layer of an N-type impurity (hereinafter the same).

2, when a positive (+) driving voltage is applied to the gate 6 on the gate insulating film 5 and a reverse bias voltage is applied to the source 2 and the drain 4, respectively, A tunneling junction having an energy band inclination is formed between the channel region 3 and the source 2 so that the electrons e existing in the valence band E v of the source 2 are coupled to the channel region 3 Band-to-band tunneling to the conduction band E c and the drive current I ON flows. In the case of a P-channel TFET, it has a symmetrical structure as in the case of the N-channel TFET described above, and operates symmetrically.

Due to the structure and operational characteristics of the TFET described above, the TFET can control the flow of electrons or holes (holes) by a tunneling method, which is different from the thermoelectron emission of the conventional MOSFET, so that the rapid ON / OFF state can be changed. Therefore, the tunneling field effect transistor is expected to show high performance even under very low driving voltage of 0.5V or less.

However, TFETs have not yet demonstrated comparable performance to MOSFETs. Important factors for a variety of reasons are low drive current and high leakage current due to ambipolar operation. Tunneling efficiency is very sensitive to the energy gap of semiconductor materials. Typical homo-junction tunneling field effect transistors include silicon (Si) junction tunneling field effect transistors and germanium (Ge) junction tunneling field effect transistors. The former is due to the homogeneous junction of silicon (Si) in the source (2) / channel region (3) / drain (4) in FIG. 1 and since the band gap energy of silicon is as large as 1.12 eV, tunneling efficiency The latter is due to the homojunction of germanium (Ge) in both the source (2) / channel region (3) / drain (4) in FIG. 1 and conversely the band gap energy of germanium is as small as 0.66 eV High drive current is guaranteed, but high leakage current due to ambipolar operation is a problem.

In order to solve the above problems, the inventors of the present invention have proposed a method of forming a high-permittivity film in a tunneling junction region between a source (2) and a channel region (3) instead of the gate insulating film (5) 1, the source 2 is formed of germanium (Ge), the channel region 3 / the drain 4 is formed of silicon (Si), and the source 2 is formed of germanium The heterojunction between the source 2 and the channel region 3 is formed or the source 2 and the channel region 3 are formed of germanium Ge and the drain 4 is formed of silicon Si, A germanium (Ge) -silicon (Si) hetero-junction tunneling field effect transistor having a heterojunction between the region 3 and the drain 4 has been proposed.

However, when a germanium (Ge) -silicon (Si) heterojunction is formed between the source 2 and the channel region 3, the indirect tunneling becomes the main component of the driving current and the germanium homojunction is formed (Ge) -silicon (Si) heterogeneous junction is formed between the channel region 3 and the drain 4, and the germanium hetero junction is formed between the source region 2 and the channel region 3, The above problem is solved, but there is a problem that the leakage current increases due to the reduction of the effective energy gap in the drain (4).

3, a hetero-junction tunneling field effect transistor having a germanium (62) -silicon (22) heterojunction structure beneath a gate 80 has been proposed (US Pat. No. 8,828,812) C is a channel region, 64 is a source, 24 is a drain, and 10 is a buried oxide film).

US Patent No. 8,828,812 discloses that a germanium 62-silicon 22 heterojunction is formed using an optional germanium condensation method and then a gate insulating film 70 and a gate 80 are bonded to the germanium 62- 22) heterojunction so that it is difficult to form the gate 80 precisely on the germanium (62) -silicon (22) hetero junction.

The present invention provides a method of manufacturing a hetero-junction tunneling field effect transistor self-aligned so that hetero-junction is located under a sidewall gate or sidewall insulation film using selective germanium condensation and sidewall processes. .

According to another aspect of the present invention, there is provided a method of fabricating a hetero-junction tunneling field effect transistor, comprising: forming a hard mask having a silicon oxide film and an etching selectivity on one side of a silicon substrate; A second step of forming a silicon germanium layer on the silicon substrate exposed to the periphery of the hard mask; A third step of forming the silicon germanium layer into a silicon oxide layer and simultaneously forming a silicon substrate region covered with the silicon germanium layer with a germanium layer by a germanium condensation technique through a thermal oxidation reaction; A fourth step of removing the silicon oxide film; Depositing and etching a gate insulating layer and a gate material on the substrate to form a sidewall gate on one side of the hard mask; A sixth step of implanting the first conductivity type impurity ions using the side wall gate and the hard mask as an ion implantation mask; Depositing a silicon oxide film on the substrate and planarizing the silicon oxide film; And an eighth step of removing the hard mask and implanting ions of second conductivity type impurities opposite to the first conductivity type.

In the eighth step, after the hard mask is removed, an insulating material is deposited and etched to form a sidewall insulating film on one side of the sidewall gate, and the second conductive impurity ions can be implanted.

Further comprising the step of forming a side wall on one side of the hard mask by depositing and etching a material ensuring an etch selectivity with the hard mask on the substrate between the first step and the second step, The silicon germanium layer may be formed on the silicon substrate exposed to the periphery of the sidewall, and the fourth step may be performed by removing the sidewall.

The formation of the silicon germanium layer in the second step may be selectively grown on the exposed silicon substrate, or may be formed by depositing the silicon germanium layer on the entire surface of the substrate to a predetermined thickness. In the latter case, the silicon germanium layer remaining on the sidewall gate and the hard mask is removed before removing the silicon oxide layer and the sidewall in the fourth step.

The material securing the etch selectivity with the hard mask may be a silicon oxide film, and the side walls may be formed as sidewalls of a silicon oxide film.

In the present invention, a hard mask is formed first on a silicon substrate, a silicon germanium layer is formed on a silicon substrate exposed around the hard mask, and the germanium is condensed through a thermal oxidation reaction and a process of forming a sidewall gate on the sidewall of the hard mask , A hetero-junction of germanium and silicon is formed at a position distant from the source under the gate of the sidewall, thereby producing a self-aligned hetero-junction tunneling field effect transistor.

Further, when a side wall is formed on one side of the hard mask such as a silicon oxide film to form a silicon germanium layer, or a side wall of an insulating film is formed on one side of the side wall gate and the impurity ion implantation process is performed, Or the position of the heterojunction formed under the side wall of the insulating film can be finely adjusted or the channel direction length of germanium and silicon doped less heavily than the source or drain can be easily controlled.

1 is a cross-sectional view showing the basic structure of a conventional tunneling field effect transistor (N-channel TFET).
FIG. 2 illustrates a tunneling current (ON CURRENT: I ON) tunneling junction between a P + region and a channel region adjacent to a P + region when a reverse bias is applied to the source / drain and a positive ) Is generated.
3 is a cross-sectional view conceptually illustrating the structure of a heterojunction tunneling field effect transistor proposed in US Patent No. 8,828,812.
FIGS. 4 to 6 are process cross-sectional views illustrating some process steps in a method of manufacturing a hetero-junction tunneling field effect transistor according to an embodiment of the present invention.
7 to 15 are cross-sectional views illustrating a method of manufacturing a hetero-junction tunneling field-effect transistor according to another embodiment of the present invention.
FIGS. 16 and 17 are cross-sectional views illustrating a method for fabricating a hetero-junction tunneling field-effect transistor according to another embodiment of the present invention, which can be performed in place of FIGS. 8 and 9, respectively.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 4 to 6 are cross-sectional views illustrating a process step of a hetero-junction tunneling field-effect transistor according to an embodiment of the present invention. Referring to FIGS. 4 to 6, 16 and 17, which illustrate that some steps can be performed differently from those of FIG.

First, as shown in FIG. 4, a hard mask 30 having a silicon oxide film (SiO 2 ) and an etching selectivity ratio is formed on one side of a silicon substrate 20 (first step).

Here, the silicon substrate 20 is preferably an SOI substrate having a silicon layer 20 on the buried oxide film 10 as shown in FIG. 4, but may also be a bulk silicon substrate. And the hard mask 30 has a future drain and the silicon area of the channel region (Fig. B region of 3) secured to an area of silicon oxide film and the etching selectivity ratio of excellent material in consideration of this, as for (e.g., silicon nitride (Si 3 N 4 ).

Next, as shown in FIG. 5, a silicon germanium layer (SiGe) 40 is formed on the silicon substrate 20 exposed to the periphery of the hard mask 30 (second step).

As shown in FIG. 5, the silicon germanium layer (SiGe) 40 may be formed around the hard mask 30 without forming a special side wall. However, as shown in FIG. 7, A step of forming a side wall 32 with a hard mask 30 and a material (for example, a silicon oxide film) securing an etch selectivity is firstly carried out. As shown in FIG. 8, The silicon germanium layer 40 may be formed.

When the sidewall 32 is formed as a sidewall of the silicon oxide film, a silicon oxide film may be deposited on the silicon substrate 20 to a predetermined thickness and may be formed on one side of the hard mask 30 by anisotropically etching. The thickness of the sidewall (the distance in the channel direction from the bottom of the sidewall) can be adjusted with process parameters such as thickness and etch. The silicon oxide sidewall 32 is subsequently removed and the sidewall gate is formed in its place, so that the heterojunction can be easily positioned under the sidewall gate with the process parameters.

The formation of the silicon germanium layer (SiGe) 40 can also be effected selectively on the silicon substrate exposed around the hard mask 30 and / or the silicon oxide film side wall 32, as shown in FIG. 5 or 8. However, as shown in FIG. 16, the hard mask 30 and / or the silicon oxide film sidewalls 32 may be formed on the entire surface of the silicon substrate with a predetermined thickness. In this case, as shown in FIG. 16, the silicon germanium layer 42 is formed on the silicon oxide film side wall 32 and the hard mask 30 with a predetermined thickness.

Next, as shown in FIG. 5, FIG. 8, or FIG. 16, in the state where the silicon germanium layers 40 and 42 are formed, if the thermal oxidation process is performed using a known germanium condensation technology (see US Pat. No. 8,828,812) The silicon germanium layers 40 and 42 are changed to the silicon oxide film 50 while the silicon substrate regions covered with the silicon germanium layers 40 and 42 are changed to the germanium layer 60 as shown in FIG. 6, FIG. 9, (Third step). At this time, the germanium layer 60 may be slightly extended below the hard mask 30 and / or the silicon oxide film sidewall 32 by adjusting the process time of the thermal oxidation process so that the next heterojunction position is located below the sidewall of the insulating film or the sidewall gate .

Next, as shown in FIG. 10, the silicon oxide film 50 is removed (step 4). At this time, when the silicon oxide film side wall 32 is present as shown in FIG. 9, the silicon oxide film side wall 32 is also removed. 17, when the silicon germanium layer 44 remains on the silicon oxide film side wall 32 and the hard mask 30, the silicon germanium layer 44 is removed first, and then the silicon oxide film 50 and the silicon oxide film 44 are removed. The side wall 32 is removed.

11, a gate insulating film 70 and a gate material are deposited and etched on the substrate having only the hard mask 30 to form a sidewall gate 80 on one side of the hard mask 30 (Step 5). At this time, the gate insulating film 70 may be formed of various kinds of high-k oxide (high-k) as well as a germanium oxide film, a silicon oxide film, and the sidewall gate 80 may be formed of a conductive material such as polycrystalline silicon or metal.

11, when the sidewall gate 80 is formed at the position where the silicon oxide film sidewall 32 is removed, the heterojunction between the germanium layer 60 and the silicon substrate 20 can be easily performed under the sidewall gate 80 .

Next, as shown in FIG. 12, a source 64 is formed by implanting first conductivity type (for example, P type) impurity ions using the side wall gate 80 and the hard mask 30 as an ion implantation mask Step 6).

Subsequently, a hard mask 30 and a material (for example, a silicon oxide film) securing an etch selectivity are deposited on the substrate and planarized to cover the source 64 side with the material film for hard mask etching 34 step).

Then, as shown in FIG. 13, the hard mask 30 is removed, and a second conductive type (for example, N type) impurity ions opposite to the first conductive type is injected to form a drain 24 step).

13, after the hard mask 30 is removed, the second conductive impurity ions may be directly implanted to form the drain 24. Alternatively, as shown in FIG. 14, the insulating material may be deposited and etched to form the drain The insulating film side wall 36 is further formed on one side of the side wall gate 80 and the second conductive type impurity ion implantation process is performed to form a gate insulating film having a position spaced a certain distance horizontally from the side wall gate 80 It is preferable that the drain 24 is formed to prevent leakage current due to the ambipolar operation. In the latter case, particularly, as shown in FIG. 6, it is more preferable that the silicon oxide film side wall 32 is not formed but a thermal oxidation process for germanium condensation is carried out so that the heterojunction position is located under the hard mask 30.

As described above, the hard mask 30 is formed on the silicon substrate 20 to have a predetermined thickness, the silicon oxide sidewall 32 is formed on one side of the hard mask, the silicon germanium layer is formed, Gate sidewalls 36 are formed on one side of the sidewall gate 80 and the impurity ion implantation process for forming the drain 24 is performed, ) Or germanium layer 62 that is less intrinsic or less heavily doped than the source or drain in the channel region (region C in FIG. 3) and the channel of the silicon layer 22 The length of the direction can be adjusted so that the leakage current problem due to the ambipolar operation can be fundamentally solved.

10: buried oxide film 20: silicon substrate
22: intrinsic or low concentration silicon layer 24: drain
30: hard mask 32: side wall
34: Material mask for hard mask etching 36: Insulating film side wall
40, 42, 44: silicon germanium layer 50: silicon oxide film
60: germanium layer 62: intrinsic or low concentration germanium layer
64: source 70: gate insulating film
80: Side wall gate

Claims (6)

A first step of forming a hard mask having a silicon oxide film and an etching selection ratio on one side of a silicon substrate;
A second step of forming a silicon germanium layer on the silicon substrate exposed to the periphery of the hard mask;
A third step of forming the silicon germanium layer into a silicon oxide layer and simultaneously forming a silicon substrate region covered with the silicon germanium layer with a germanium layer by a germanium condensation technique through a thermal oxidation reaction;
A fourth step of removing the silicon oxide film;
Depositing and etching a gate insulating layer and a gate material on the substrate to form a sidewall gate on one side of the hard mask;
A sixth step of implanting the first conductivity type impurity ions using the side wall gate and the hard mask as an ion implantation mask;
Depositing a silicon oxide film on the substrate and planarizing the silicon oxide film; And
And removing the hard mask and implanting ions of a second conductivity type impurity opposite to the first conductivity type. [5] The method of claim 1,
The method according to claim 1,
Wherein the step of forming the heterojunction tunneling electric field comprises the steps of: removing the hard mask, depositing and etching an insulating material to further form sidewalls of the insulating film on one side of the sidewall gate, and implanting the second conductive impurity ions A method of manufacturing an effect transistor.
3. The method according to claim 1 or 2,
Further comprising the step of forming a side wall on one side of the hard mask by depositing and etching a material ensuring an etch selectivity with the hard mask on the substrate between the first step and the second step,
The second step includes forming the silicon germanium layer on the silicon substrate exposed around the sidewall,
Wherein the fourth step further comprises removing the sidewalls. ≪ RTI ID = 0.0 > 11. < / RTI >
The method of claim 3,
Wherein the formation of the silicon germanium layer in the second step is selectively grown on the exposed silicon substrate. ≪ RTI ID = 0.0 > 11. < / RTI >
The method of claim 3,
Wherein the silicon germanium layer of the second step is deposited on the entire surface of the substrate to a predetermined thickness,
Wherein the silicon germanium layer remaining on the sidewall gate and the hard mask is removed prior to removing the silicon oxide layer and the sidewall in the fourth step.
The method of claim 3,
The material that secures the etch selectivity with the hard mask is a silicon oxide film,
Wherein the sidewalls are silicon oxide sidewalls. ≪ Desc / Clms Page number 20 >
KR1020150088792A 2015-06-23 2015-06-23 Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes KR101682420B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10236364B1 (en) 2018-06-22 2019-03-19 International Busines Machines Corporation Tunnel transistor
US10249755B1 (en) 2018-06-22 2019-04-02 International Business Machines Corporation Transistor with asymmetric source/drain overlap
US10347731B2 (en) 2017-11-09 2019-07-09 International Business Machines Corporation Transistor with asymmetric spacers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368127B2 (en) * 2009-10-08 2013-02-05 Globalfoundries Singapore Pte., Ltd. Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current
US20140199825A1 (en) * 2011-09-20 2014-07-17 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368127B2 (en) * 2009-10-08 2013-02-05 Globalfoundries Singapore Pte., Ltd. Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current
US20140199825A1 (en) * 2011-09-20 2014-07-17 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10347731B2 (en) 2017-11-09 2019-07-09 International Business Machines Corporation Transistor with asymmetric spacers
US10516028B2 (en) 2017-11-09 2019-12-24 International Business Machines Corporation Transistor with asymmetric spacers
US10236364B1 (en) 2018-06-22 2019-03-19 International Busines Machines Corporation Tunnel transistor
US10249755B1 (en) 2018-06-22 2019-04-02 International Business Machines Corporation Transistor with asymmetric source/drain overlap
US10483382B1 (en) 2018-06-22 2019-11-19 International Business Machines Corporation Tunnel transistor
US10510885B1 (en) 2018-06-22 2019-12-17 International Business Machines Corporation Transistor with asymmetric source/drain overlap

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