CN108538911A - L-type tunneling field-effect transistor of optimization and preparation method thereof - Google Patents
L-type tunneling field-effect transistor of optimization and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention discloses L-type tunneling field-effect transistor of a kind of optimization and preparation method thereof, mainly solve the problems, such as that existing device ON state current is low and dipolar effect is serious comprising：SOI substrate (1), isolation channel (2), source region (3), channel region (4), drain region (6), gate regions (5) and conductive layer (7)；Isolation channel (2) is located at the both sides of SOI substrate (1)；Source region (3), channel region (4) and drain region (6) are located at the upper surface of SOI substrate；Gate regions (5) are located at the upside of channel region (4)；Source region (3) uses Germanium semiconductor material, and gate regions (5) use heterogeneous gate dielectric structure, and use high-K gate dielectric material by source area side, and low K gate dielectric materials are used close to drain region side；The right margin of drain region (6) and gate regions (5) is equipped with interval S.The present invention can effectively inhibit dipolar effect, improve driving current, can be used for the making of large scale integrated circuit.
Description
Technical field
The invention belongs to the L-type tunneling field-effect transistor of technical field of semiconductor device more particularly to a kind of optimization and
Preparation method can be used for the making of large scale integrated circuit.
Background technology
With the progress of semiconductor integration technology, the development that integrated circuit technique follows " Moore laws " enters nanometer
Scale.However, the challenge of the problems such as from short-channel effect, ghost effect and quantum tunneling so that conventional CMOS crystal
It manages and scaled has become more and more difficult, it is difficult to meet the requirement of integrated circuit sustainable development.
Tunneling field-effect transistor TFET is worked based on band-to-band-tunneling quantum tunneling effect mechanism, at room temperature subthreshold
The value amplitude of oscillation can break through the limitation of conventional MOS FET subthreshold value limiting values 60mV/decade.So TFET devices have quickly
Switching characteristic and lower leakage current, can be effectively reduced device power consumption, it is considered to be continue the important of " Moore laws "
Approach.
But TFET devices face that ON state current is smaller, ideal value is not achieved in subthreshold swing and it is double to exist at present
The problems such as polar effect, so that seriously limiting its extensive use in terms of circuit.In order to improve TFET device performances, science
Worker proposes a kind of L-type TFET devices, and this structure improves the ON state current of TFET devices to a certain degree.But it compares
MOSFET element, silicon substrate TFET devices still face that driving current is small, the serious problem of dipolar effect, its application is made to receive limit
System.Therefore, it improves its driving current and effectively dipolar effect is inhibited to become silicon substrate TFET urgent problems to be solved.
Invention content
It is an object of the invention to the deficiencies for above-mentioned traditional silicon substrate TFET devices, propose a kind of L-type tunnelling of optimization
Field-effect transistor and preparation method effectively inhibit dipolar effect to reduce leakage current while improving driving current.
To achieve the above object, the L-type tunneling field-effect transistor that the present invention optimizes, including：SOI substrate, isolation channel, source
Area, channel region, drain region, grid region and conductive layer；Isolation channel is located at the both sides of SOI substrate；Source region, channel region and drain region are located at SOI
The upper surface of substrate；Grid region is located at the upside of channel region, it is characterised in that：
The source region, using Germanium semiconductor material；
The grid region uses high-K gate dielectric material, close to drain region using heterogeneous gate dielectric structure, and by source area side
Side uses low K gate dielectric materials；
The right margin in the drain region and grid region is equipped with interval S.
To achieve the above object, the method for the L-type tunneling field-effect transistor of preparation optimization of the invention, including following step
Suddenly：
1) it is sequentially prepared the SOI substrate for including bottom silicon, buried oxide layer and top layer silicon；
2) it is etched in the both sides of top layer silicon, forms shallow channel isolation area, and carry out oxide deposition, form isolation channel；
3) in top layer silicon surface etch, source region groove, under conditions of 300 DEG C~600 DEG C, epitaxial diposition germanium material are formed
Source region groove is filled, while being passed through boron doping gas in germanium and doping in situ is carried out to source region, forms p-type source region；
4) in top layer silicon surface etch, L-type groove structure is formed, the intrinsic silicon semiconductor layer of epitaxial diposition forms L-type raceway groove
Layer；
5) heterogeneous gate dielectric layer is grown in intrinsic silicon semiconductor layer surface, depositing polysilicon forms grid region；
6) in top layer silicon face and grid region right margin interval a quarter grid length or half grid length or 3/4ths grid
Strong point using photoetching process formed drain region figure, using ion implantation technology drain region implantation dosage be 3e14~9e15 arsenic from
Son, Implantation Energy are 30~50keV, and re-annealing activator impurity, it is 10 to form doping concentration18cm-3~1020cm-3N-type leakage
Area；
7) in source region, drain region and grid region photoetching lead window, deposit metal, photoetching lead, formed source electrode, drain electrode and
Gate electrode is finally completed the preparation of the L-type tunneling field-effect transistor of optimization.
The invention has the advantages that：
First, source region of the invention uses germanium material, since germanium material has smaller effective mass and narrower forbidden band wide
Degree, so as to shorten carrier tunneling distance, effectively increases device drive current, and reduce subthreshold swing；
Second, the present invention is since grid region uses heterogeneous gate dielectric structure, and the right margin in drain region and grid region is equipped with interval S,
To increase carrier reverse tunnel potential barrier so that carrier tunnelling probability becomes smaller when device is in reverse operation state, has
Effect inhibits dipolar effect；
Third, manufacture craft of the invention is simple and practicable, compatible with existing semiconductor fabrication process, can be with inexpensive real
It is existing.
Description of the drawings
Fig. 1 is the device architecture schematic diagram for the L-type tunneling field-effect transistor that the present invention optimizes；
Fig. 2 is the L-type tunneling field-effect transistor device flow diagram that the present invention makes optimization；
Fig. 3 is the computer aided design software simulated properties curve graph of the embodiment of the present invention 1；
Fig. 4 is the computer aided design software simulated properties curve graph of the embodiment of the present invention 2；
Fig. 5 is the computer aided design software simulated properties curve graph of the embodiment of the present invention 3.
Specific implementation mode
Below in conjunction with attached drawing, the embodiment of the present invention and effect are described in detail：
Referring to Fig.1, the L-type tunneling field-effect transistor that the present invention optimizes includes SOI substrate 1, isolation channel 2, source region 3, ditch
Road area 4, drain region 6, grid region 5 and conductive layer 7, wherein the substrate 1 of soi structure is by initial silicon chip 11,12 and of intermidate oxide buried layer
Si epitaxial layers 13 are constituted, and grid region 5 is made of high-K gate dielectric layer 51, low K gate dielectric layers 52 and polysilicon gate 53, and conductive layer 7 is by source
Electrode 71, gate electrode 72 and drain electrode 73 are constituted；Isolation channel 2 is located at the both sides of Si epitaxial layers 13；Source region 3, channel region 4 and drain region
6 are located at the upper surface of Si epitaxial layers 13；Grid region 5 is covered on channel region 4；Source electrode 71, gate electrode 72 and the leakage of conductive layer 7
Electrode 73 is drawn from source region 3, grid region 5 and 6 surface of drain region respectively.Specifically, source region 3 uses the germanium material of narrow band gap；It adopts in grid region 5
With heterogeneous gate dielectric structure, high-K gate dielectric material is used by source area side, low K gate dielectric materials are used close to drain region side；
The right margin in drain region 6 and grid region 5 is equipped with interval S, which is set as a quarter grid length or half grid length or 3/4ths
Grid length.
With reference to Fig. 2, the present invention provides following three kinds of embodiments.
Embodiment 1 makes the tunneling field-effect transistor in drain region and grid region right margin interval a quarter grid length.
Step 1, SOI substrate is made, such as Fig. 2 (a).
1a) buried oxide layer is generated in bottom initial silicon on piece dry-oxygen oxidation；
Top layer silicon epitaxy layer 1b) is grown on buried oxide layer by epitaxial growth technology, forms SOI substrate.
Step 2, it etches to form isolation channel in top layer silicon both sides, such as Fig. 2 (b).
2a) SiO is grown in SOI substrate top layer silicon face2, form the first SiO2Layer, then in the layer surface growth regulation one
Si3N4Layer forms the first protective layer；
Litho machine 2b) is used, shallow trench isolation figure is formed on the first protective layer using photoetching process；
2c) etched at shallow trench isolation figure to form shallow channel isolation area, etching depth using dry etch process
For top layer silicon thickness；
2d) deposited by chemical vapor deposition method under 600 DEG C of temperature condition using chemical vapor deposition device
Earth silicon material fills shallow channel isolation area；
Polishing machine 2e) is used, top layer silicon face is mechanically polished, removes the silica of top layer silicon excess surface, makes top
Layer silicon face is smooth, forms isolation channel.
Step 3, it is 10 to form doping concentration in top layer silicon face18cm-3Source region, such as Fig. 2 (c).
3a) SiO is grown in top layer silicon face2, form the 2nd SiO2Layer, then in two Si of the layer surface growth regulation3N4Layer, shape
At the second protective layer；
Litho machine 3b) is used, setting position forms source region figure on the second protective layer using photoetching process；
3c) etch to form source region groove at source region figure using dry etch process；
Germanium material 3d) is deposited using selective epitaxial growth process in source region groove, so that it is filled up completely groove, simultaneously
It is passed through boron doping gas and doping in situ, dosage 3e14 is carried out to source region, re-annealing realizes the activation in situ of doped chemical, shape
It is 10 at doping concentration18cm-3Highly dope p-type source region.
Step 4, L-type intrinsic silicon channel region is formed in top layer silicon face, such as Fig. 2 (d).
SiO2 4a) is grown in top layer silicon face, SiO2 layers of formation the 3rd is formed in three Si3N4 layers of the layer surface growth regulation
Third protective layer；
Litho machine 4b) is used, recess region figure is lithographically formed on third protective layer using photoetching process；
4c) etch to form groove at recess region figure using dry etch process；
4d) extension deposition of intrinsic silicon materials form L-type intrinsic silicon channel layer in groove.
Step 5, the L-type grid region for preparing heterogeneous gate dielectric structure, such as Fig. 2 (e).
5a) in L-type intrinsic silicon channel layer surface epitaxial diposition high K dielectric gate oxide；
The lateral high K dielectric gate oxide of channel layer surface 5b) is etched away using selective etch technique；
Chemical vapor deposition device 5c) is used, under 600 DEG C of temperature condition, by chemical vapor deposition method in ditch
Channel layer surface deposition low-K dielectric gate oxide, at heterogeneous gate dielectric layer；
5d) in the crystal silicon grid material of dual material gate dielectric layer surface epitaxial diposition heavy doping；
Polishing machine 5e) is used, top layer silicon face is mechanically polished, so as to surfacing and remove top layer silicon face
Polysilicon and gate oxide, reuse litho machine, and gate patterns are formed in the polysilicon surface of gate groove using photoetching process, and
Selective etch falls the polycrystalline silicon material and gate oxide material of gate groove surface portion, forms L-type grid region.
Step 6, it is 10 to form doping concentration in top layer silicon face18cm-3Drain region, such as Fig. 2 (f).
6a) in top layer silicon and groove surfaces growth SiO2 to form the 4th SiO2 layers, in four Si of the layer surface growth regulation3N4
Layer forms the 4th protective layer；
6b) use litho machine, using photoetching process on the 4th protective layer with grid region right margin interval a quarter grid length
Form drain region figure；
The shallow grooves to be formed and can expose drain region 6c) are etched at the figure of drain region using dry etch process；
Ion implantation apparatus 6d) is used, using ion implantation technology in the arsenic ion that groove implantation dosage is 3e14, injection
Energy is 30keV, and it is 10 to form doping concentration18cm-3N-type drain region；
6e) under 1000 DEG C of temperature condition, quick high-temp annealing, activator impurity.
Step 7, conductive layer is made, such as Fig. 2 (g).
7a) pushed up using chemical vapor deposition method under 600 DEG C of temperature condition using chemical vapor deposition device
Layer silicon face deposit silicon nitride insulating layer；
Polishing machine 7b) is used, insulating silicon nitride layer surface is mechanically polished, keeps its smooth；
It 7c) in insulating layer and lead hole surface splash-proofing sputtering metal, then carries out alloying and forms metal silicide, and etch away gold
Belong to the metal of suicide surfaces；
7d) again in insulating layer and lead hole surface splash-proofing sputtering metal, until filling fairlead, and metal surface is mechanically polished
Keep its smooth, then be lithographically formed source electrode, gate electrode, drain electrode completes the making of the L-type tunneling field-effect transistor of optimization.
Embodiment 2 makes the tunneling field-effect transistor in drain region and grid region right margin interval half grid length.
Step 1 makes SOI substrate, such as Fig. 2 (a).
The specific implementation of this step is identical as the step 1 of embodiment 1.
Step 2 etches to form isolation channel, such as Fig. 2 (b) in top layer silicon both sides.
The specific implementation of this step is identical as the step 2 of embodiment 1.
Step 3, it is 10 to form doping concentration in top layer silicon face19cm-3Source region, such as Fig. 2 (c).
3.1) SiO is grown in top layer silicon face2, form the 2nd SiO2Layer, then in two Si of the layer surface growth regulation3N4Layer, shape
At the second protective layer；
3.2) litho machine is used, setting position forms source region figure on the second protective layer using photoetching process；
3.3) it etches to form source region groove at source region figure using dry etch process；
3.4) germanium material is deposited using selective epitaxial growth process in source region groove, so that it is filled up completely groove, together
When be passed through boron doping gas doping in situ, dosage 4e15 carried out to source region, re-annealing realizes that the in situ of doped chemical is activated,
It is 10 to form doping concentration19cm-3Highly dope p-type source region.
Step 4 forms L-type intrinsic silicon channel region, such as Fig. 2 (d) in top layer silicon face.
The specific implementation of this step is identical as the step 4 of embodiment 1.
Step 5 prepares the L-type grid region of heterogeneous gate dielectric structure, such as Fig. 2 (e).
The specific implementation of this step is identical as the step 5 of embodiment 1.
Step 6, it is 10 to form doping concentration in top layer silicon face19cm-3Drain region, such as Fig. 2 (f).
6.1) in top layer silicon and groove surfaces growth SiO2 to form the 4th SiO2 layers, in four Si of the layer surface growth regulation3N4
Layer forms the 4th protective layer；
6.2) use litho machine, using photoetching process on the 4th protective layer with grid region right margin interval half grid length
Form drain region figure；
6.3) shallow grooves to be formed and can expose drain region are etched at the figure of drain region using dry etch process；
6.4) ion implantation apparatus is used, using ion implantation technology in the arsenic ion that groove implantation dosage is 6e15, note
Energy is 40keV, and it is 10 to form doping concentration19cm-3N-type drain region；
6.5) under 1000 DEG C of temperature condition, quick high-temp annealing, activator impurity.
Step 7 makes conductive layer, such as Fig. 2 (g).
The specific implementation of this step is identical as the step 7 of embodiment 1, completes the L-type tunneling field-effect transistor of optimization
It makes.
Embodiment 3 makes the tunneling field-effect transistor in drain region and 3/4ths grid length of grid region right margin interval.
The first step makes SOI substrate, such as Fig. 2 (a).
The specific implementation of this step is identical as the step 1 of embodiment 1.
Second step etches to form isolation channel, such as Fig. 2 (b) in top layer silicon both sides.
The specific implementation of this step is identical as the step 2 of embodiment 1.
Third walks, and it is 10 to form doping concentration in top layer silicon face20cm-3Source region, such as Fig. 2 (c).
First, SiO is grown in top layer silicon face2, form the 2nd SiO2Layer, then in two Si of the layer surface growth regulation3N4Layer,
Form the second protective layer；
Then, using litho machine, using photoetching process, setting position forms source region figure on the second protective layer；
Then, it etches to form source region groove at source region figure using dry etch process；
Then, germanium material is deposited using selective epitaxial growth process in source region groove, so that it is filled up completely groove, together
When be passed through boron doping gas doping in situ, dosage 5e15 carried out to source region, re-annealing realizes that the in situ of doped chemical is activated,
It is 10 to form doping concentration20cm-3Highly dope p-type source region.
4th step forms L-type intrinsic silicon channel region, such as Fig. 2 (d) in top layer silicon face.
The specific implementation of this step is identical as the step 4 of embodiment 1.
5th step prepares the L-type grid region of heterogeneous gate dielectric structure, such as Fig. 2 (e).
The specific implementation of this step is identical as the step 5 of embodiment 1.
6th step, it is 10 to form doping concentration in top layer silicon face20cm-3Drain region, such as Fig. 2 (f).
First, in top layer silicon and groove surfaces growth SiO2 to form the 4th SiO2 layers, in the layer surface growth regulation four
Si3N4Layer forms the 4th protective layer；
Then, using litho machine, using photoetching process on the 4th protective layer with grid region right margin interval half grid
Length forms drain region figure；
Then, it etches to form the shallow grooves that can expose drain region at the figure of drain region using dry etch process；
Then, using ion implantation apparatus, using ion implantation technology in the arsenic ion that groove implantation dosage is 9e15, note
It is 50keV to enter energy, and it is 10 to form doping concentration20cm-3N-type drain region；
Then, under 1000 DEG C of temperature condition, quick high-temp annealing, activator impurity.
7th step makes conductive layer, such as Fig. 2 (g).
The specific implementation of this step is identical as the step 7 of embodiment 1, completes the L-type tunneling field-effect transistor of optimization
It makes.
The present invention feature and effect can be further illustrated by following emulation experiment,
Experiment content：
Experiment 1, by computer aided design software to the tunneling transistor of embodiment 1 and conventional silicon substrate L-type TFET
I-V characteristic emulation is carried out, the results are shown in Figure 3；
Experiment 2, by computer aided design software to the tunneling transistor of embodiment 2 and conventional silicon substrate L-type TFET
I-V characteristic emulation is carried out, the results are shown in Figure 4；
Experiment 3, by computer aided design software to the tunneling transistor of embodiment 3 and conventional silicon substrate L-type TFET
I-V characteristic emulation is carried out, the results are shown in Figure 5；
From the comparing result of Fig. 3~5 as it can be seen that compared with traditional silicon substrate L-type TFET devices, the L of optimization provided by the invention
Type tunneling field-effect transistor source region uses the Germanium semiconductor material with smaller effective mass and low energy gap width, shortens tunnel
Distance is worn, carrier tunneling rate is increased and then effectively improves driving current, reaches 10-4A/μm；Simultaneously it is also seen that the present invention exists
Dipolar effect is effectively inhibited while improving ON state current, reverse leakage current all-the-time stable is 10-14A/ μm of this order of magnitude,
This is because device of the present invention is equipped with interval S in the right margin in drain region and grid region, increases reverse tunnel barrier width and brought
Performance change.
Above description is only three specific examples of the present invention, does not constitute any limitation of the invention, it is clear that for
It, all may be without departing substantially from the principle of the invention, structure after having understood the content of present invention and principle for one of skill in the art
In the case of, carry out various modifications in form and details and change, but these modifications and variations based on inventive concept
Still within the claims of the present invention.
Claims (10)
1. a kind of L-type tunneling field-effect transistor of optimization, including：SOI substrate (1), isolation channel (2), source region (3), channel region
(4), drain region (6), grid region (5) and conductive layer (7)；Isolation channel (2) is located at the both sides of SOI substrate (1)；Source region (3), channel region
(4) and drain region (6) are located at the upper surface of SOI substrate；Grid region (5) is located at the upside of channel region (4), it is characterised in that：
The source region (3), using Germanium semiconductor material；
The grid region (5) uses high-K gate dielectric material, close to drain region one using heterogeneous gate dielectric structure, and by source area side
Side uses low K gate dielectric materials；
The right margin in the drain region (6) and grid region (5) is equipped with interval S.
2. the L-type tunneling field-effect transistor of optimization according to claim 1, which is characterized in that the high-K gate dielectric material
Material, using HfO2。
3. the L-type tunneling field-effect transistor of optimization according to claim 1, which is characterized in that the low K gate mediums material
Material, using SiO2。
4. the L-type tunneling field-effect transistor of optimization according to claim 1, which is characterized in that the drain region (6) and grid
The right margin interval S in area (5), is set as a quarter grid length or half grid length or 3/4ths grid lengths.
5. a kind of preparation method of the L-type tunneling field-effect transistor of optimization, which is characterized in that include the following steps：
1) it is sequentially prepared the SOI substrate for including bottom silicon, buried oxide layer and top layer silicon；
2) it is etched in the both sides of top layer silicon, forms shallow channel isolation area, and carry out oxide deposition, form isolation channel；
3) in top layer silicon surface etch, source region groove is formed, under conditions of 300 DEG C~600 DEG C, the filling of epitaxial diposition germanium material
Source region groove, while being passed through boron doping gas in germanium and doping in situ is carried out to source region, form p-type source region；
4) in top layer silicon surface etch, L-type groove structure is formed, the intrinsic silicon semiconductor layer of epitaxial diposition forms L-type channel layer；
5) heterogeneous gate dielectric layer is grown in intrinsic silicon semiconductor layer surface, depositing polysilicon forms grid region；
6) at top layer silicon face and grid region right margin interval a quarter grid length or half grid length or 3/4ths grid lengths
Using photoetching process formed drain region figure, using ion implantation technology drain region implantation dosage be 3e14~9e15 arsenic ion,
Its Implantation Energy is 30~50keV, and re-annealing activator impurity, it is 10 to form doping concentration18~1020cm-3N-type drain region；
7) in source region, drain region and grid region photoetching lead window, metal is deposited, photoetching lead forms source electrode, drain electrode and grid electricity
Pole is finally completed the preparation of the L-type tunneling field-effect transistor of optimization.
6. method as claimed in claim 5, which is characterized in that etched in the both sides of top layer silicon in step 2), form shallow trench
Isolated area carries out as follows：
2a) SiO is grown in SOI substrate top layer silicon face2To form the first SiO2Layer, then in one Si of the layer surface growth regulation3N4Layer,
Form the first protective layer；
Shallow channel isolation area figure 2b) is formed on the first protective layer using photoetching process；
It 2c) is etched at the figure of shallow channel isolation area using dry etch process, forms shallow channel isolation area, etching depth is top
Layer silicon thickness.
7. method as claimed in claim 5, which is characterized in that in the surface etch of top layer silicon in step 3), it is recessed to form source region
Slot carries out as follows：
3a) SiO is grown in top layer silicon face2To form the 2nd SiO2Layer, then in two Si of the layer surface growth regulation3N4Layer forms the
Two protective layers；
Source region figure 3b) is formed on the second protective layer using photoetching process；
It 3c) is etched at source region figure using dry etch process, forms source region groove.
8. method as claimed in claim 5, which is characterized in that step 3) is passed through boron doping gas in germanium and carries out original to source region
Position doping, dosage are 3e14~5e15, doping concentration 1018cm-3~1020cm-3。
9. preparation method as claimed in claim 5, which is characterized in that in top layer silicon surface etch in step 4), it is recessed to form L-type
Slot structure carries out as follows：
4a) in SiO2 layers of top layer silicon face growth SiO2 formation the 3rd, in three Si3N4 layers of the layer surface growth regulation, third is formed
Protective layer；
Photoetching 4b) is carried out to third protective layer, forms L-type recess region figure；
It 4c) is etched at recess region figure using dry etch process, forms L-type groove structure.
10. preparation method as claimed in claim 5, which is characterized in that grown in intrinsic silicon semiconductor layer surface in step 5)
Heterogeneous gate dielectric layer is to deposit high-K gate dielectric in L-type intrinsic silicon channel layer surface first with chemical vapor deposition method；It is sharp again
The lateral high-K gate dielectric of channel layer surface is etched away with selective etch technique；Then utilize chemical vapor deposition method in ditch
The low K gate mediums of channel layer surface deposition form heterogeneous gate dielectric layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109904218A (en) * | 2019-03-01 | 2019-06-18 | 西北工业大学 | Inverted T shaped tunneling field-effect transistor |
| CN109935631A (en) * | 2019-03-24 | 2019-06-25 | 西安电子科技大学 | Undoped L shape tunneling field-effect transistor and preparation method thereof |
| CN109959696A (en) * | 2019-03-24 | 2019-07-02 | 西安电子科技大学 | Semiconductor biosensor and preparation method thereof based on tunneling field-effect transistor |
| CN113675266A (en) * | 2021-07-26 | 2021-11-19 | 西安电子科技大学 | Negative capacitance L-shaped gate tunneling field effect transistor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664165A (en) * | 2012-05-18 | 2012-09-12 | 北京大学 | Method for manufacturing complementary tunneling field effect transistor (TFET) based on standard complementary metal oxide semiconductor integrated circuit (CMOS IC) process |
| CN103594376A (en) * | 2013-11-08 | 2014-02-19 | 北京大学 | Junction-modulated type tunneling field effect transistor and manufacturing method thereof |
-
2018
- 2018-04-28 CN CN201810398738.6A patent/CN108538911B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664165A (en) * | 2012-05-18 | 2012-09-12 | 北京大学 | Method for manufacturing complementary tunneling field effect transistor (TFET) based on standard complementary metal oxide semiconductor integrated circuit (CMOS IC) process |
| CN103594376A (en) * | 2013-11-08 | 2014-02-19 | 北京大学 | Junction-modulated type tunneling field effect transistor and manufacturing method thereof |
Non-Patent Citations (2)
| Title |
|---|
| CONG LI ET AL: "Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement", 《SUPERLATTICES AND MICROSTRUCTURES》 * |
| KAIN LU LOW ET AL: "Device physics and design of a L-shaped germanium source tunneling transistor", 《JPN. J. APPL. PHYS.》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109904218A (en) * | 2019-03-01 | 2019-06-18 | 西北工业大学 | Inverted T shaped tunneling field-effect transistor |
| CN109904218B (en) * | 2019-03-01 | 2020-07-14 | 西北工业大学 | Inverted T-shaped tunneling field effect transistor |
| CN109935631A (en) * | 2019-03-24 | 2019-06-25 | 西安电子科技大学 | Undoped L shape tunneling field-effect transistor and preparation method thereof |
| CN109959696A (en) * | 2019-03-24 | 2019-07-02 | 西安电子科技大学 | Semiconductor biosensor and preparation method thereof based on tunneling field-effect transistor |
| CN109935631B (en) * | 2019-03-24 | 2020-10-09 | 西安电子科技大学 | Undoped L-shaped tunneling field effect transistor and preparation method thereof |
| CN109959696B (en) * | 2019-03-24 | 2021-04-06 | 西安电子科技大学 | Semiconductor biosensor based on tunneling field effect transistor and preparation method thereof |
| CN113675266A (en) * | 2021-07-26 | 2021-11-19 | 西安电子科技大学 | Negative capacitance L-shaped gate tunneling field effect transistor and preparation method thereof |
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