CN102723341B - A kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method - Google Patents

Abstract

The invention discloses a kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method.Its process is: preparation a slice SOI substrate, and upper strata basis material is (100) crystal face, and underlying substrate material is (110) crystal face; Substrate slice grows N-type Si extension, and preparation deep trench isolation, manufactures conventional Si bipolar transistor in bipolar device region; Etch deep trouth in PMOS device active area, selective growth strain Si PMOS device active layer, this active layer is prepared the compressive strain PMOS device of vertical-channel; Etch deep trouth in nmos device active area, selective growth strain Si nmos device active layer, this epitaxial loayer is prepared the tensile strain nmos device of planar channeling.The present invention makes full use of strain Si material mobility higher than body Si material and strain Si material stress and the anisotropic feature of mobility, based on SOI substrate, has prepared mixing crystal face strain Si vertical-channel BiCMOS integrated device and the circuit of excellent performance.

Description

A kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method.

Background technology

The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously.It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid.In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

Silicon materials experienced by more than 50 year as semi-conducting material application, traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law.At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.

But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology.Particularly when IC chip feature sizes enters nanoscale, from device angles, short channel effect in nanoscale devices, high-field effect, quantum effect, the impact of parasitic parameter, the problems such as technological parameter fluctuation are to device leakage current, subthreshold behavior, the impact of the performances such as ON state/off-state current is more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet novel, the demand of high-velocity electrons system.

In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Therefore; current industrial quarters is when manufacture large scale integrated circuit especially hybrid digital-analog integrated circuit; still Si BiCMOS or SiGe BiCMOS technology (Si BiCMOS is Si bipolar transistor BJT+Si CMOS, and SiGe BiCMOS is SiGe heterojunction bipolar transistor HBT+Si CMOS) is adopted.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that Si BiCMOS technology manufactures, especially frequency performance, is greatly limited; And for SiGe BiCMOS technology, although bipolar transistor have employed SiGe HBT, the unipolar device promoted for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, promote further so these all limit BiCMOS performance of integrated circuits ground.

For this reason, will when not reducing a kind of mobility of charge carrier of types of devices, improve the mobility of the charge carrier of another kind of types of devices, this patent proposes a kind ofly to utilize the selectivity of silicon materials to add stress technique to prepare BiCMOS, namely mixes the preparation of crystal face strain BiCMOS integrated device.

Summary of the invention

The object of the present invention is to provide a kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method, with realize do not changing existing equipment and increase cost condition under, prepared the mixing crystal face strain Si vertical-channel BiCMOS integrated device based on SOI substrate and excellent performance and circuit.

The object of the invention is to one and mixing crystal face strain Si vertical-channel BiCMOS integrated device and preparation method are provided, in described BiCMOS integrated device, nmos device is strain Si planar channeling, PMOS device is strain Si vertical-channel, and bipolar device adopts common Si bipolar transistor.

Further, the conducting channel of described nmos device is strain Si material, and the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

Further, the conducting channel of described PMOS device is strain Si material, and the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel.

Further, described nmos device be prepared in crystal face for (100) SOI substrate on, PMOS device be prepared in crystal face for (110) substrate on.

Further, on substrate, bipolar device adopts the preparation of body Si material.

Further, described BiCMOS integrated device substrate is SOI material.

Another object of the present invention is to provide a kind of preparation method mixing crystal face strain Si vertical-channel BiCMOS integrated device, comprise the steps:

The first step, choose two panels N-type doping Si sheet, wherein a slice crystal face is (110), and a slice crystal face is (100), and two panels doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm; Using crystal face be a slice of (100) as upper strata basis material, and in this basis material hydrogen injecting, be that a slice of (110) is as underlying substrate material using crystal face; Chemico-mechanical polishing (CMP) technique is adopted to carry out polishing to two oxide layer surfaces;

Second step, two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

4th step, photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 2 ~ 3 μm, as collector region;

5th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3heavy doping collector electrode;

6th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁸~ 5 × 10 ¹⁸cm ^-3base;

7th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

8th step, photoetching PMOS device active area, in PMOS device active area, utilize dry etching, etches the deep trouth that the degree of depth is 1.5 ~ 2.5 μm, the oxide layer of centre carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth seven layer material on the PMOS device active area of (110) crystal face substrate: ground floor is N-type Si resilient coating, and thickness is 1.5 ~ 2.5 μm, deep trouth fills up by this layer, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be N-type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ²⁰cm ^-3, as the drain region of PMOS device; 4th layer is thickness is 3 ~ 5nmP type strained si layer/, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer; Layer 5 to be thickness the be N-type strain Si of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

9th step, photoetching nmos device active area, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, the second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3, the N-type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

Tenth step, utilize dry etch process, in PMOS device source, leak isolated area and etch the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

11 step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600 ~ 800 DEG C, deposit one deck SiO ₂resilient coating and layer of sin, etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.3 ~ 0.7 μm of leakage groove; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, form PMOS device and leak trenched side-wall isolation; Dry etching is utilized to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-SiGe beyond flute surfaces, formed and leak bonding pad;

12 step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5 ~ 0.9 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

13 step, etch nmos device active area, utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100 ~ 300nm, Ge component is 10 ~ 30%, etching N MOS device grid; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Be the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, dry etching falls this layer of SiO ₂, as nmos device grid curb wall, form nmos device grid;

14 step, carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 ~ 5 × 10 ²⁰cm ^-3;

15 step, photoetching lead-in wire window, sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact, splash-proofing sputtering metal, photoetching goes between, and forming conducting channel is that having of 22 ~ 45nm mixes crystal face strain Si vertical-channel BiCMOS integrated device.

Further, PMOS device channel length determines according to the N-type strained si layer/layer thickness of the 3rd step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

Further, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in the seven to ten three step, and maximum temperature is less than or equal to 800 DEG C.

Another object of the present invention is to provide a kind of preparation method mixing crystal face strain Si vertical-channel BiCMOS integrated circuit, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as upper strata basis material, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as underlying substrate material;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, implementation method prepared by isolated area is:

(2a) substrate surface thermal oxidation a layer thickness is the SiO of 300nm ₂layer;

(2b) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 2 μm, as collector region;

(2c) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2d) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

Step 3, implementation method prepared by bipolar device base and emitter region is:

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 4, implementation method prepared by PMOS device active area is:

(4a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.5 μm, oxide layer is carved thoroughly;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/7a of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 22nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of PMOS device;

(4g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/7b of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(4h) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

Step 5, implementation method prepared by nmos device active area is:

(5a) photoetching nmos device active area;

(5b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 200nm, doping content is 1 × 10 ¹⁵cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(5e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

Step 6, implementation method prepared by shallow-trench isolation is:

(6a) utilize dry etch process, etch in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 7, the implementation method that PMOS device leaks bonding pad preparation preparation is:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(7b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.3 μm of leakage groove;

(7c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 8, implementation method prepared by PMOS grid bonding pad is:

(8a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.5 μm of gate groove;

(8b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(8c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

Step 9, implementation method prepared by nmos device is:

(9a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(9b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(9c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(9d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(9e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(9f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device;

Step 10, implementation method prepared by formation BiCMOS integrated circuit is:

(10a) lead-in wire window is made by lithography;

(10b) sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(10c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, the final CMOS of formation conducting channel is that having of 22nm mixes crystal face strain Si vertical-channel BiCMOS integrated device and circuit.

tool of the present invention has the following advantages:

1. the mixing crystal face strain Si vertical-channel BiCMOS device that prepared by the present invention have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, (100) crystal face is compressive strain for strain Si PMOS device, the mobility in its hole is higher than body Si material, and be tensile strain for strain Si nmos device on (110) crystal face, the mobility of its electronics is also higher than body Si material, therefore, this electric property such as device frequency and current driving ability is higher than the body Si cmos device of same size;

2. the mixing crystal face strain Si vertical-channel BiCMOS device prepared of the present invention, adopt selective epitaxial technology, respectively at nmos device and PMOS device active area selective growth strain Si material, improve the flexibility of device layout, enhance BiCMOS device and integrated circuit electric property;

3. have employed SOI substrate in the mixing crystal face strain Si vertical-channel BiCMOS device that prepared by the present invention, reduce power consumption and the cut-in voltage of device and circuit, improve the reliability of device and circuit;

4. the present invention prepares in mixing crystal face strain Si vertical-channel BiCMOS device technology, adopt Poly-SiGe material as grid, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe grid, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

5. the maximum temperature related in the mixing crystal face strain Si vertical-channel BiCMOS device process that prepared by the present invention is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

6. in the mixing crystal face strain Si vertical-channel BiCMOS device prepared of the present invention, the raceway groove of PMOS device is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

7., in the mixing crystal face strain Si vertical-channel BiCMOS that prepared by the present invention, in order to effectively suppress short-channel effect, introducing light dope source and drain (LDD) technique, improve device performance;

8., in the mixing crystal face strain Si vertical-channel BiCMOS structure that prepared by the present invention, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

9. in the mixing crystal face strain Si vertical-channel BiCMOS that prepared by the present invention, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.

Accompanying drawing explanation

Fig. 1 is the realization flow figure of mixing crystal face strain Si vertical-channel BiCMOS integrated device preparation method provided by the invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of mixing crystal face strain Si vertical-channel BiCMOS integrated device, described BiCMOS integrated device nmos device is strain Si planar channeling, and PMOS device is strain Si vertical-channel, adopts common Si bipolar transistor.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of described nmos device is strain Si material, and the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of described PMOS device is strain Si material, and the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel.

As a prioritization scheme of the embodiment of the present invention, described nmos device is prepared in the SOI substrate that crystal face is (100), and PMOS device is prepared on the substrate of crystal face for (110).

As a prioritization scheme of the embodiment of the present invention, on substrate, bipolar device adopts the preparation of body Si material.

As a prioritization scheme of the embodiment of the present invention, described BiCMOS integrated device substrate is SOI material.

Referring to accompanying drawing 1, preparation technology's flow process of the present invention's mixing crystal face strain Si vertical-channel BiCMOS integrated device and circuit is described in further detail.

Embodiment 1: preparation 22nm mixing crystal face strain Si vertical-channel BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2a) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 2 μm, as collector region;

(2c) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2d) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by bipolar device base and emitter region.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 4, prepared by PMOS device active area.

(4a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.5 μm, oxide layer is carved thoroughly;

(4b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 1.5 μm along (110) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/7a of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 22nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of PMOS device;

(4g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(4h) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 5, prepared by nmos device active area.

(5a) photoetching nmos device active area;

(5b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 200nm, doping content is 1 × 10 ¹⁵cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(5e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device.

Step 6, prepared by shallow-trench isolation.

(6a) utilize dry etch process, etch in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, PMOS device leaks bonding pad preparation.

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(7b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.3 μm of leakage groove;

(7c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 8, prepared by PMOS device grid bonding pad.

(8a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.5 μm of gate groove;

(8b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(8c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 9, prepared by nmos device.

(9a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(9b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(9c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(9d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(9e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(9f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device.

Step 10, forms BiCMOS integrated circuit.

(10a) photoetching lead-in wire window;

(10b) sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(10c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, final formation conducting channel is that having of 22nm mixes crystal face strain Si vertical-channel BiCMOS integrated device and circuit.

Embodiment 2: preparation 30nm mixing crystal face strain Si vertical-channel BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material of lower floor;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 400 DEG C of temperature;

(1e) substrate temperature after bonding is raised 150 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 150nm, and carry out chemico-mechanical polishing at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2a) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 5 × 10 ¹⁶cm ^-3si layer, thickness is 2.5 μm, as collector region;

(2c) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2d) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 4 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by bipolar device base and emitter region.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 900 DEG C, annealing 45min activator impurity, forming doping content is 5 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 900 DEG C, annealing 45min activator impurity, forming doping content is 3 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 900 DEG C, annealing 45min activator impurity, becomes doping content to be 1 × 10 ²⁰cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer.

Step 4, prepared by PMOS device active area.

(4a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2 μm, oxide layer is carved thoroughly;

(4b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2 μm along (110) crystal face, doping content is 3 × 10 ¹⁵cm ^-3;

(4c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.75 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(4e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/7a of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(4f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 30nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(4g) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(4h) utilize chemical vapor deposition (CVD) method, at 700 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 5, prepared by nmos device active area.

(5a) photoetching nmos device active area;

(5b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 300nm, doping content is 3 × 10 ¹⁵cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.75 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 3 × 10 ¹⁶cm ^-3;

(5e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, regrowth a layer thickness is the P type strained si layer/of 17nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 6, prepared by shallow-trench isolation.

(6a) utilize dry etch process, etch in isolated area the shallow slot that the degree of depth is 0.4 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, PMOS device leaks bonding pad preparation.

(7a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(7b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.5 μm of leakage groove;

(7c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(7d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 8, prepared by PMOS device grid bonding pad.

(8a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.7 μm of gate groove;

(8b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(8c) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 20%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 9, prepared by nmos device.

(9a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(9b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 200nm, Ge component is 20%;

(9c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(9d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 3 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(9e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one thickness is the SiO of 4nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(9f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 3 × 10 ²⁰cm ^-3, form nmos device.

Step 10, forms BiCMOS integrated circuit.

(10a) photoetching lead-in wire window;

(10b) sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(10c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, final formation conducting channel is that having of 30nm mixes crystal face strain Si vertical-channel BiCMOS integrated device and circuit.

Embodiment 3: preparation 45nm mixing crystal face strain Si vertical-channel BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material of lower floor's active layer;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 480 DEG C of temperature;

(1e) substrate temperature after bonding is raised 100 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 200nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2a) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁷cm ^-3si layer, thickness is 3 μm, as collector region;

(2c) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2d) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 5 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by bipolar device base and emitter region.

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 1 × 10 ²⁰cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 5 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 950 DEG C, annealing 30min activator impurity, becomes doping content to be 5 × 10 ²⁰cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer.

Step 4, prepared by PMOS device active area.

(4a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.5 μm, oxide layer is carved thoroughly;

(4b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2.5 μm along (110) crystal face, doping content is 5 × 10 ¹⁵cm ^-3;

(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe5 that a layer thickness is the N-type Ge component trapezoidal profile of 2 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device;

(4e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(4f) utilize chemical vapor deposition (CVD) method, at 750 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 45nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(4g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(4h) utilize chemical vapor deposition (CVD) method, at 750 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the source region of PMOS device.

Step 5, prepared by nmos device active area.

(5a) photoetching nmos device active area;

(5b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 400nm, doping content is 5 × 10 ¹⁵cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 2 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(5e) utilize chemical vapor deposition (CVD) method, at 750 DEG C, regrowth a layer thickness is the P type strained si layer/12 of 20nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 6, prepared by shallow-trench isolation.

(6a) utilize dry etch process, etch in isolated area the shallow slot that the degree of depth is 0.5 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation.

Step 7, PMOS device leaks bonding pad preparation.

(7a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(7b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.7 μm of leakage groove;

(7c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(7d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 8, prepared by PMOS device grid bonding pad.

(8a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.9 μm of gate groove;

(8b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(8c) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 9, prepared by nmos device.

(9a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(9b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 300nm, Ge component is 30%;

(9c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(9d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(9e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one thickness is the SiO of 5nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device gate lateral wall, form nmos device grid;

(9f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 5 × 10 ²⁰cm ^-3, form nmos device.

Step 10, forms BiCMOS integrated circuit.

(10a) photoetching lead-in wire window;

(10b) sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(10c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, final formation conducting channel is that having of 45nm mixes crystal face strain Si vertical-channel BiCMOS integrated device and circuit.

The mixing crystal face strain Si vertical-channel BiCMOS integrated device that the embodiment of the present invention provides and preparation method's tool have the following advantages:

1. the mixing crystal face strain Si vertical-channel BiCMOS device that prepared by the present invention have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, (100) crystal face is compressive strain for strain Si PMOS device, the mobility in its hole is higher than body Si material, and be tensile strain for strain Si nmos device on (110) crystal face, the mobility of its electronics is also higher than body Si material, therefore, this electric property such as device frequency and current driving ability is higher than the body Si cmos device of same size;

2. the mixing crystal face strain Si vertical-channel BiCMOS device prepared of the present invention, adopt selective epitaxial technology, respectively at nmos device and PMOS device active area selective growth strain Si material, improve the flexibility of device layout, enhance BiCMOS device and integrated circuit electric property;

3. have employed SOI substrate in the mixing crystal face strain Si vertical-channel BiCMOS device that prepared by the present invention, reduce power consumption and the cut-in voltage of device and circuit, improve the reliability of device and circuit;

4. the present invention prepares in mixing crystal face strain Si vertical-channel BiCMOS device technology, adopt Poly-SiGe material as grid, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe grid, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

5. the maximum temperature related in the mixing crystal face strain Si vertical-channel BiCMOS device process that prepared by the present invention is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

6. in the mixing crystal face strain Si vertical-channel BiCMOS device prepared of the present invention, the raceway groove of PMOS device is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

7., in the mixing crystal face strain Si vertical-channel BiCMOS that prepared by the present invention, in order to effectively suppress short-channel effect, introducing light dope source and drain (LDD) technique, improve device performance;

8., in the mixing crystal face strain Si vertical-channel BiCMOS structure that prepared by the present invention, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

9. in the mixing crystal face strain Si vertical-channel BiCMOS that prepared by the present invention, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. mix a preparation method for crystal face strain Si vertical-channel BiCMOS integrated device, it is characterized in that, comprise the steps:

The first step, choose two panels N-type doping Si sheet, wherein a slice crystal face is (110), and a slice crystal face is (100), and two panels doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm; Using crystal face be a slice of (100) as upper strata basis material, and in this upper strata basis material hydrogen injecting, be that a slice of (110) is as underlying substrate material using crystal face; Chemico-mechanical polishing (CMP) technique is adopted to carry out polishing to two oxide layer surfaces;

Second step, two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

4th step, photoetching bipolar device active area, epitaxial growth one deck doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 2 ~ 3 μm, as collector region;

5th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3heavy doping collector electrode;

6th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 ¹⁸~ 5 × 10 ¹⁸cm ^-3base;

7th step, at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 ¹⁹~ 5 × 10 ²⁰cm ^-3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

8th step, photoetching PMOS device active area, in PMOS device active area, utilize dry etching, etches the deep trouth that the degree of depth is 1.5 ~ 2.5 μm, the oxide layer of centre carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth seven layer material on the PMOS device active area of (110) crystal face substrate: ground floor is N-type Si resilient coating, thickness is 1.5 ~ 2.5 μm, deep trouth fills up by this N-type Si resilient coating, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be N-type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ²⁰cm ^-3, as the drain region of PMOS device; 4th layer is thickness is 3 ~ 5nmP type strained si layer/, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer; Layer 5 to be thickness the be N-type strain Si of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

9th step, photoetching nmos device active area, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, the second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3, the N-type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

Tenth step, utilize dry etch process, in PMOS device source, leak isolated area and etch the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

11 step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600 ~ 800 DEG C, deposit one deck SiO ₂resilient coating and layer of sin, etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.3 ~ 0.7 μm of leakage groove; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, form PMOS device and leak trenched side-wall isolation; Dry etching is utilized to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-SiGe beyond flute surfaces, formed and leak bonding pad;

12 step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5 ~ 0.9 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

13 step, etch nmos device active area, utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100 ~ 300nm, Ge component is 10 ~ 30%, etching N MOS device grid; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Be the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, dry etching falls this layer of SiO ₂, as nmos device grid curb wall, form nmos device grid;

14 step, carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 ~ 5 × 10 ²⁰cm ^-3;

15 step, photoetching lead-in wire window, sputter layer of metal titanium (Ti) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, form device Metal Contact, splash-proofing sputtering metal, photoetching goes between, and forming conducting channel is that having of 22 ~ 45nm mixes crystal face strain Si vertical-channel BiCMOS integrated device.

2. the preparation method of mixing crystal face strain Si vertical-channel BiCMOS integrated device according to claim 1, it is characterized in that, PMOS device channel length is determined according to the N-type strained si layer/layer thickness of the 8th step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

3. the preparation method of mixing crystal face strain Si vertical-channel BiCMOS integrated device according to claim 1, it is characterized in that, maximum temperature involved in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in the seven to ten three step, and maximum temperature is less than or equal to 800 DEG C.

4. mix a preparation method for crystal face strain Si vertical-channel BiCMOS integrated circuit, it is characterized in that, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as upper strata basis material, and in this upper strata basis material hydrogen injecting;

(1b) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as underlying substrate material;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, implementation method prepared by isolated area is:

(2a) substrate surface thermal oxidation a layer thickness is the SiO of 300nm ₂layer;

(2b) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 2 μm, as collector region;

(2c) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2d) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2f) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

Step 3, implementation method prepared by bipolar device base and emitter region is:

(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁹cm ^-3heavy doping collector electrode;

(3b) at substrate surface thermal oxidation one SiO ₂layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 ¹⁸cm ^-3base;

(3c) at substrate surface thermal oxidation one SiO ₂layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 ¹⁹cm ^-3highly doped emitter, form bipolar transistor;

(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 4, implementation method prepared by PMOS device active area is:

(4a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.5 μm, oxide layer is carved thoroughly;

(4b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 1.5 μm along (110) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(4c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(4d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(4e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 22nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of PMOS device;

(4g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(4h) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

Step 5, implementation method prepared by nmos device active area is:

(5a) photoetching nmos device active area;

(5b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 200nm, doping content is 1 × 10 ¹⁵cm ^-3;

(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(5e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

Step 6, implementation method prepared by shallow-trench isolation is:

(6a) utilize dry etch process, etch in isolated area the shallow slot that the degree of depth is 0.3 μm;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂;

(6c) by chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form shallow-trench isolation;

Step 7, PMOS device is leaked the implementation method prepared bonding pad and is:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(7b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.3 μm of leakage groove;

(7c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 8, implementation method prepared by PMOS grid bonding pad is:

(8a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.5 μm of gate groove;

(8b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(8c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

Step 9, implementation method prepared by nmos device is:

(9a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(9b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(9c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(9d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(9e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(9f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device;

Step 10, implementation method prepared by formation BiCMOS integrated circuit is:

(10a) photoetching lead-in wire window;

(10b) sputter layer of metal titanium (Ti) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(10c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, the final CMOS of formation conducting channel is that having of 22nm mixes crystal face strain Si vertical-channel BiCMOS integrated device and circuit.