CN102790052B

CN102790052B - Tri-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on SiGe HBT (Heterojunction Bipolar Transistor) and preparation method

Info

Publication number: CN102790052B
Application number: CN201210244089.7A
Authority: CN
Inventors: 胡辉勇; 宋建军; 宣荣喜; 周春宇; 张鹤鸣; 李妤晨; 舒斌; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2015-04-22
Anticipated expiration: 2032-07-16
Also published as: CN102790052A

Abstract

The invention discloses a tri-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on SiGe HBT (Heterojunction Bipolar Transistor) and a preparation method. A buried layer is prepared on a substrate, an N-Si layer, a P-SiGe layer and an N-Si layer are continuously grown, a dielectric layer is deposited, deep-groove isolation is prepared, a collector region, a base region and an emitter region are prepared, a collector electrode, base electrode and emitter electrode contact region is formed, and a SiGe HBT device is formed; active region deep grooves of an NMOS (N-channel Metal Oxide Semiconductor) device and a PMOS (P-channel Metal Oxide Semiconductor) device are etched, a P-type Si layer/a P-type SiGe gradient layer/a P-type SiGe layer/a P-type strain Si layer serving as the active region of the NMOS device and an N-type Si layer/an N-type strain SiGe layer/an N-type Si cap layer serving as the active region of the PMOS device are respectively and selectively grown in the deep grooves in an extending manner; a virtual grid electrode and a side wall are prepared, and source and drain electrodes of the NMOS and the PMOS device are formed through self-alignment; and the virtual grid is etched, a SiON grid dielectric layer and a W-TiN composite grid are deposited to form a CMOS structure, and finally the tri-stain BiCMOS integrated device and a circuit are constructed. Tensile strain Si with high electronic mobility and compressive strain SiGe with high hole mobility are sufficiently utilized as conducting channels for the NMOS device and the PMOS device, and the performance of the BiCMOS integrated circuit is effectively improved.

Description

A kind of three strain BiCMOS integrated device and preparation methods based on SiGe HBT

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of three strain BiCMOS integrated device and preparation methods based on SiGe HBT.

Background technology

The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously.It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid.In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

Silicon materials experienced by more than 50 year as semi-conducting material application, traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law.At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.

But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology.Particularly when IC chip feature sizes enters nanoscale, from device angles, short channel effect in nanoscale devices, high-field effect, quantum effect, the impact of parasitic parameter, the problems such as technological parameter fluctuation are to device leakage current, subthreshold behavior, the impact of the performances such as ON state/off-state current is more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet novel, the demand of high-velocity electrons system.

In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that Si BiCMOS technology manufactures, especially frequency performance, is greatly limited; And for SiGe BiCMOS technology, although bipolar transistor have employed SiGe HBT, the unipolar device promoted for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, promote further so these all limit BiCMOS performance of integrated circuits ground.

Summary of the invention

The object of the present invention is to provide a kind of three strain BiCMOS integrated device and preparation methods based on SiGe HBT, using the tensile strain Si realizing utilizing the electron mobility high and high compressive strain SiGe of hole mobility as the conducting channel of NMOS and PMOS device, effectively improve the performance of BiCMOS device and circuit.

The object of the present invention is to provide a kind of three strain BiCMOS integrated devices based on SiGe HBT, the three kinds of devices forming this BiCMOS integrated device are respectively: strain Si planar channeling nmos device, strain SiGe planar channeling PMOS device and SiGe HBT device.

Further, nmos device conducting channel is strain Si material, is tensile strain along channel direction.

Further, PMOS device conducting channel is strain SiGe material, is compressive strain along channel direction.

Further, PMOS device adopts quantum well structure.

Further, the base of SiGe HBT device is strain SiGe material.

Further, SiGe HBT device is planar structure.

Another object of the present invention is to the preparation method that a kind of three strain BiCMOS integrated devices based on SiGe HBT are provided, comprise the steps:

The first step, to choose doping content be 5 × 10 ¹⁴~ 5 × 10 ¹⁵cm ^-3p type Si sheet as substrate;

Second step, be the SiO of 300 ~ 500nm at substrate surface thermal oxidation one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forms N-type heavy doping buried region;

The oxide layer of the 3rd step, removal excess surface, epitaxial growth a layer thickness is the N-type Si epitaxial loayer of 2 ~ 3 μm, and as collector region, this layer of doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

4th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the SiGe layer of 20 ~ 60nm in Grown a layer thickness, as base, this layer of Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3;

5th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the N-type Si layer of 100 ~ 200nm in Grown a layer thickness, as emitter region, this layer of doping content is 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3;

6th step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

7th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180 ~ 300nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

8th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 105 ~ 205nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

9th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching collector region, carries out N-type impurity injection to this region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area;

Tenth step, photoetching base region, carry out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area, and to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT; The method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

11 step, photoetching nmos device active area, utilize dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then, in deep trouth, the method for chemical vapor deposition (CVD) is utilized, at 600 ~ 750 DEG C, continuously growth four layer materials: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device, form nmos device active area;

12 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then in deep trouth, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material: ground floor to be thickness the be N-type relaxation Si layer of 1.9 ~ 2.8 μm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The N-type strained sige layer of the second layer to be thickness be 12 ~ 15nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is 15 ~ 25%; The intrinsic relaxation Si layer of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area.Utilize wet etching, etch away the layer SiO on surface ₂;

13 step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 3 ~ 5nm in substrate surface deposit a layer thickness ₂, as the gate dielectric layer of nmos device and PMOS device, and then utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the Poly-Si of 200 ~ 300nm in substrate surface deposit a layer thickness, etching Poly-Si and SiO ₂layer, forms the empty grid of nmos device and PMOS device;

14 step, photoetching nmos device active area, carry out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

15 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3 ~ 5nm ₂, utilize dry etching, the SiO on etched substrate surface ₂, retain Ploy-Si sidewall sections, form nmos device and PMOS device gate electrode side wall; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration ¹⁹~ 1 × 10 ²⁰cm ^-3nmos device source-drain area; Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration ¹⁹~ 1 × 10 ²⁰cm ^-3pMOS device source-drain area;

16 step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 400 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; Utilize the method for physical vapor deposition (PVD), deposit W-TiN composite grid, utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device and PMOS device grid;

17 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, photoetching lead-in wire window, sputter layer of metal over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, depositing metal, photoetching goes between, and forms the drain electrode of MOS device, the emitter of source electrode and grid and bipolar device, base stage and collector electrode metal lead-in wire, forms the three strain BiCMOS integrated devices based on SiGe HBT that conducting channel is 22 ~ 45nm.

Determine to chemical vapor deposition (CVD) technological temperature in the 17 step according to the 4th step based on involved maximum temperature in the three strain BiCMOS integrated device manufacture processes of SiGe HBT further, in this preparation method, maximum temperature is less than or equal to 800 DEG C.

Further, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20 ~ 60nm.

Another object of the present invention is to the preparation method that a kind of three strain BiCMOS integrated circuits based on SiGe HBT are provided, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1a) choosing doping content is 5 × 10 ¹⁴cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 800 DEG C, annealing 90min activator impurity, forms N-type heavy doping buried region;

(1d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2 μm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

(1e) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, this layer of Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1f) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the N-type Si layer of 100nm in Grown a layer thickness, and as emitter region, this layer of doping content is 1 × 10 ¹⁷cm ^-3;

Step 2, implementation method prepared by deep trench isolation district is:

(2a) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2d) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

Step 3, implementation method prepared by collector electrode shallow-trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation;

Step 4, implementation method prepared by base stage shallow-trench isolation is:

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 105nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching collector region, carries out N-type impurity injection to this region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5d) photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5e) to substrate at 950 DEG C of temperature, annealing 120s, carries out impurity activation, forms SiGe HBT;

(5f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 6, implementation method prepared by nmos device epitaxial material is:

(6a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;

(6b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type Si resilient coating of 200nm, and doping content is 5 × 10 ¹⁵cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe graded bedding of 1.5 μm, and bottom Ge component is 0, and top Ge component is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(6d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe layer of 200nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(6e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 ¹⁶cm ^-3as the raceway groove of nmos device;

Step 7, implementation method prepared by PMOS device active area is:

(7a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.82 μm;

(7c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.8 μm in PMOS device active area, doping content is 5 × 1017cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 15nm in PMOS device active area, Ge component is 15%, and doping content is 5 × 10 ¹⁷cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 5nm in PMOS device active area, form PMOS device active area;

(7f) utilize wet etching, etch away the layer SiO on surface ₂;

Step 8, implementation method prepared by the empty grid of MOS is:

(8a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 3.5nm at substrate surface deposition thickness ₂layer, as the gate dielectric layer of nmos device and PMOS device;

(8b) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the Poly-Si of 300nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO ₂layer, forms the empty grid of nmos device and the empty grid of PMOS device;

(8c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(8d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

Step 9, implementation method prepared by nmos device and PMOS device source-drain area is:

(9a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 5nm ₂;

(9b) dry etching is utilized, the SiO on etched substrate surface ₂, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;

(9c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration ¹⁹cm ^-3nmos device source region and drain region;

(9d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration ¹⁹cm ^-3pMOS device source region and drain region;

Step 10, implementation method prepared by nmos device and PMOS device grid is:

(10a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness ₂layer;

(10b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid;

(10c) the empty grid of wet etching, form a groove at gate electrode place;

(10d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, at substrate surface deposit one deck SiON, thickness is 5nm;

(10e) method of physical vapor deposition (PVD) is utilized, deposit W-TiN composite grid;

(10f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid;

Step 11, the implementation method forming BiCMOS integrated circuit is:

(11a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer;

(11b) photoetching lead-in wire window, sputters layer of metal, alloy over the entire substrate, and autoregistration forms metal silicide;

(11c) depositing metal, photoetching goes between, form MOS device drain electrode, source electrode and gate metal lead-in wire and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the three strain BiCMOS integrated devices and circuit based on SiGe HBT that conducting channel is 45nm.

tool of the present invention has the following advantages:

1. what prepared by the present invention strains in BiCMOS integrated devices based on three of SiGe HBT, and PMOS device applies the hole mobility compressive strain sige material higher than body Si material as conducting channel, effectively promotes the electric property of PMOS device; And nmos device applies the electron mobility tensile strain Si material higher than body Si material as conducting channel, effectively promote the electric property of nmos device, therefore the BiCMOS integrated device prepared compared with body Si material of the electric property of the BiCMOS integrated device prepared of the present invention and circuit thereof and circuit performance excellent;

2. what prepared by the present invention strains BiCMOS integrated devices based on three of SiGe HBT, adopt selective epitaxial technology, respectively in nmos device and PMOS device active area selective growth tensile strain Si and compressive strain sige material, nmos device and the electric property such as PMOS device frequency performance and current driving ability are obtained promote, thus BiCMOS device and performance of integrated circuits obtain enhancing simultaneously;

3. what prepared by the present invention strains in BiCMOS integrated devices based on three of SiGe HBT, and in order to effectively suppress short-channel effect, limiting device degradation, introduces light dope source and drain (LDD) technique, improve device performance;

4. what prepared by the present invention strains in BiCMOS integrated devices based on three of SiGe HBT, PMOS device is quantum well devices, namely strained sige layer is between Si cap layers and body Si layer, compared with surface channel device, reduce the interface scattering in channel carrier transport process, inhibit the reduction of mobility; Hole barrier simultaneously between Si cap layers and strained sige layer, inhibits hot carrier to inject in gate medium, improves the reliability of BiCMOS integrated device and circuit;

5. what prepared by the present invention strains in BiCMOS integrated devices based on three of SiGe HBT, adopts the SiON of high-k to replace traditional pure SiO ₂do gate medium, enhance the grid-control ability of device, improve the reliability of device;

6. what prepared by the present invention strains in BiCMOS integrated devices based on three of SiGe HBT, have employed metal gate mosaic technology (damascene process) and prepare gate electrode, this gate electrode is metal W-TiN composite construction, due to the TiN of lower floor and strain Si and strain SiGe material work functions difference less, improve the electrology characteristic of device, the W on upper strata then can reduce the resistance of gate electrode, achieves the optimization of gate electrode.

Accompanying drawing explanation

Fig. 1 is provided by the invention based on the three strain BiCMOS integrated devices of SiGe HBT and the realization flow figure of circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of three strain BiCMOS integrated devices based on SiGe HBT, the three kinds of devices forming this BiCMOS integrated device are respectively: strain Si planar channeling nmos device, strain SiGe planar channeling PMOS device and SiGe HBT device.

As a prioritization scheme of the embodiment of the present invention, nmos device conducting channel is strain Si material, is tensile strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, PMOS device conducting channel is strain SiGe material.Be compressive strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, PMOS device adopts quantum well structure.

As a prioritization scheme of the embodiment of the present invention, the base of SiGe HBT device is strain SiGe material.

As a prioritization scheme of the embodiment of the present invention, SiGe HBT device is planar structure.

Referring to accompanying drawing 1, the present invention's preparation is described in further detail based on the three strain BiCMOS integrated devices of SiGe HBT and the technological process of circuit.

Embodiment 1: prepare three strain BiCMOS integrated device and the circuit based on SiGe HBT that conducting channel is 45nm, concrete steps are as follows:

Step 1, epitaxial growth.

(1f) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the N-type Si layer of 100nm in Grown a layer thickness, and as emitter region, this layer of doping content is 1 × 10 ¹⁷cm ^-3.

Step 2, prepared by deep trench isolation district.

(2d) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 6, prepared by nmos device epitaxial material.

(6c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe graded bedding of 1.5 μm, and bottom Ge component is 0%, and top Ge component is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(6e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 ¹⁶cm ^-3as the raceway groove of nmos device.

Step 7, prepared by PMOS device active area.

(7c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.8 μm in PMOS device active area, doping content is 5 × 10 ¹⁷cm ^-3;

(7f) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, the empty grid preparation of MOS.

(8d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD).

Step 9, nmos device and the preparation of PMOS device source-drain area.

(9d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration ¹⁹cm ^-3pMOS device source region and drain region.

Step 10, nmos device and the preparation of PMOS device grid.

(10c) the empty grid of wet etching, form a groove at gate electrode place;

(10f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid.

Step 11, forms BiCMOS integrated circuit.

Embodiment 2: prepare three strain BiCMOS integrated device and the circuit based on SiGe HBT that conducting channel is 30nm, concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choosing doping content is 1 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 900 DEG C, annealing 60min activator impurity, forms N-type heavy doping buried region;

(1d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2.5 μm, as collector region, this layer of doping content is 5 × 10 ¹⁶cm ^-3;

(1e) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiGe layer of 40nm in Grown a layer thickness, and as base, this layer of Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3;

(1f) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the N-type Si layer of 150nm in Grown a layer thickness, and as emitter region, this layer of doping content is 3 × 10 ¹⁷cm ^-3.

Step 2, prepared by deep trench isolation district.

(2a) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 4 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂;

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 240nm;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 155nm;

(4e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching collector region, carries out N-type impurity injection to this region, makes collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector electrode;

(5d) photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 5 × 10 ¹⁹cm ^-3, form base stage;

(5e) to substrate at 1000 DEG C of temperature, annealing 60s, carries out impurity activation, forms SiGe HBT;

(5f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer.

Step 6, prepared by nmos device epitaxial material.

(6b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type Si resilient coating of 300nm at nmos device active area selective growth thickness, doping content is 1 × 10 ¹⁶cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type SiGe graded bedding of 1.8 μm at nmos device active area selective growth thickness, bottom Ge component is 0, and top Ge component is 20%, and doping content is 1 × 10 ¹⁶cm ^-3;

(6d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type SiGe layer of 300nm at nmos device active area selective growth thickness, Ge component is 20%, and doping content is 1 × 10 ¹⁷cm ^-3;

(6e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 18nm at nmos device active area selective growth thickness, doping content is 1 × 10 ¹⁷cm ^-3as the raceway groove of nmos device.

Step 7, prepared by PMOS device active area.

(7a) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.42 μm;

(7c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.4 μm in PMOS device active area, doping content is 1 × 10 ¹⁷cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 14nm in PMOS device active area, Ge component is 20%, and doping content is 1 × 10 ¹⁷cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 4nm in PMOS device active area, form PMOS device active area;

(7f) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, the empty grid preparation of MOS.

(8a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 4nm at substrate surface deposition thickness ₂layer, as the gate dielectric layer of nmos device and PMOS device;

(8b) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the Poly-Si of 240nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO ₂layer, forms the empty grid of nmos device and the empty grid of PMOS device;

(8c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 3 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(8d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 3 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD).

Step 9, nmos device and the preparation of PMOS device source-drain area.

(9a) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm ₂;

(9c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 8 × 10 that autoregistration generates impurity concentration ¹⁹cm ^-3nmos device source region and drain region;

(9d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 8 × 10 that autoregistration generates impurity concentration ¹⁹cm ^-3pMOS device source region and drain region.

Step 10, nmos device and the preparation of PMOS device grid.

(10a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 450nm in substrate surface deposit a layer thickness ₂layer;

(10c) the empty grid of wet etching, form a groove at gate electrode place;

(10d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, at substrate surface deposit one deck SiON, thickness is 3nm;

Step 11, forms BiCMOS integrated circuit.

(11a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer;

(11c) depositing metal, photoetching goes between, form MOS device drain electrode, source electrode and gate metal lead-in wire and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the three strain BiCMOS integrated devices and circuit based on SiGe HBT that conducting channel is 30nm.

Embodiment 3: prepare three strain BiCMOS integrated device and the circuit based on SiGe HBT that conducting channel is 22nm, concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 950 DEG C, annealing 30min activator impurity, forms N-type heavy doping buried region;

(1d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 3 μm, as collector region, this layer of doping content is 1 × 10 ¹⁷cm ^-3;

(1e) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the SiGe layer of 60nm in Grown a layer thickness, and as base, this layer of Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3;

(1f) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the N-type Si layer of 200nm in Grown a layer thickness, and as emitter region, this layer of doping content is 5 × 10 ¹⁷cm ^-3.

Step 2, prepared by deep trench isolation district.

(2a) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 5 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂;

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 300nm;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 205nm;

(4e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching collector region, carries out N-type impurity injection to this region, makes collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector electrode;

(5d) photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ²⁰cm ^-3, form base stage;

(5e) to substrate at 1100 DEG C of temperature, annealing 15s, carries out impurity activation, forms SiGe HBT;

(5f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer.

Step 6, prepared by nmos device epitaxial material.

(6b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type Si resilient coating of 200nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁵cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type SiGe graded bedding of 1.5 μm at nmos device active area selective growth thickness, bottom Ge component is 0, and top Ge component is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(6d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type SiGe layer of 200nm at nmos device active area selective growth thickness, Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(6e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 15nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁶cm ^-3as the raceway groove of nmos device.

Step 7, prepared by PMOS device active area.

(7a) method of chemical vapor deposition (CVD) is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 μm;

(7c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 1.9 μm in PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 12nm in PMOS device active area, Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 3nm in PMOS device active area, form PMOS device active area;

(7f) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, the empty grid preparation of MOS.

(8a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 3nm at substrate surface deposition thickness ₂layer, as the gate dielectric layer of nmos device and PMOS device;

(8b) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the Poly-Si of 200nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO ₂layer, forms the empty grid of nmos device and the empty grid of PMOS device;

(8c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(8d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD).

Step 9, nmos device and the preparation of PMOS device source-drain area.

(9a) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm ₂;

(9c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 1 × 10 that autoregistration generates impurity concentration ²⁰cm ^-3nmos device source region and drain region;

(9d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 1 × 10 that autoregistration generates impurity concentration ²⁰cm ^-3pMOS device source region and drain region.

Step 10, nmos device and the preparation of PMOS device grid.

(10a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness ₂layer;

(10c) the empty grid of wet etching, form a groove at gate electrode place;

(10d) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5nm;

Step 11, forms BiCMOS integrated circuit.

(11a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer;

(11c) depositing metal, photoetching goes between, form MOS device drain electrode, source electrode and gate metal lead-in wire, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form three strain BiCMOS integrated device and the circuit based on SiGeHBT that conducting channel is 22nm.

The three strain BiCMOS integrated devices based on SiGe HBT that the embodiment of the present invention provides and preparation method's tool have the following advantages:

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1., based on a preparation method for the three strain BiCMOS integrated devices of SiGe HBT, it is characterized in that, comprise the steps:

The oxide layer of the 3rd step, removal excess surface, epitaxial growth a layer thickness is the N-type Si epitaxial loayer of 2 ~ 3 μm, and as collector region, N-type Si outer layer doping concentration is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

4th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the SiGe layer of 20 ~ 60nm in Grown a layer thickness, as base, SiGe layer Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3;

5th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the N-type Si layer of 100 ~ 200nm in Grown a layer thickness, as emitter region, N-type Si layer doping content is 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3;

9th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching collector region, carries out N-type impurity injection to photoetching collector region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area;

Tenth step, photoetching base region, carry out p type impurity injection to photoetching base region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area, and to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT; The method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

11 step, photoetching nmos device active area, utilize dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then, in deep trouth, the method for chemical vapor deposition (CVD) is utilized, at 600 ~ 750 DEG C, continuously growth four layer materials: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device, form nmos device active area;

12 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then in deep trouth, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material: ground floor to be thickness the be N-type relaxation Si layer of 1.9 ~ 2.8 μm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The N-type strained sige layer of the second layer to be thickness be 12 ~ 15nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is 15 ~ 25%; The intrinsic relaxation Si layer of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area, utilizes wet etching, etch away the layer SiO on surface ₂;

16 step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 400 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; Utilize the method for physical vapour deposition (PVD) (PVD), deposit W-TiN composite grid, chemico-mechanical polishing (CMP) method is utilized to remove the metal on surface, stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device and PMOS device grid;

17 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, photoetching lead-in wire window, sputter layer of metal alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, depositing metal, photoetching goes between, form the drain electrode of MOS device, the emitter of source electrode and grid and bipolar device, base stage and collector electrode metal lead-in wire, form the three strain BiCMOS integrated devices based on SiGe HBT that conducting channel is 22 ~ 45nm.

2. preparation method according to claim 1, it is characterized in that, determine to chemical vapor deposition (CVD) technological temperature in the 17 step according to the 4th step based on involved maximum temperature in the three strain BiCMOS integrated device manufacture processes of SiGeHBT in this preparation method, maximum temperature is less than or equal to 800 DEG C.

3. preparation method according to claim 1, is characterized in that, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20 ~ 60nm.

4., based on a preparation method for the three strain BiCMOS integrated circuits of SiGe HBT, it is characterized in that, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2 μm, as collector region, N-type epitaxial si layer doping content is 1 × 10 ¹⁶cm ^-3;

(1e) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, SiGe layer Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type Si layer of 100nm in Grown a layer thickness, as emitter region, N-type Si layer doping content is 1 × 10 ¹⁷cm ^-3;

Step 2, implementation method prepared by deep trench isolation district is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5c) photoetching collector region, carries out N-type impurity injection to photoetching collector region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5d) photoetching base region, carries out p type impurity injection to photoetching base region, makes base contact regions doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

Step 6, implementation method prepared by nmos device epitaxial material is:

Step 7, implementation method prepared by PMOS device active area is:

(7f) utilize wet etching, etch away the layer SiO on surface ₂;

Step 8, implementation method prepared by the empty grid of MOS is:

Step 10, implementation method prepared by nmos device and PMOS device grid is:

(10c) the empty grid of wet etching, form a groove at gate electrode place;

(10e) method of physical vapour deposition (PVD) (PVD) is utilized, deposit W-TiN composite grid;

Step 11, the implementation method forming BiCMOS integrated circuit is:

(11b) photoetching lead-in wire window, sputters layer of metal alloy over the entire substrate, and autoregistration forms metal silicide;