CN102723340B - A kind of SOI BJT two strain plane BiCMOS integrated device and preparation method - Google Patents

A kind of SOI BJT two strain plane BiCMOS integrated device and preparation method Download PDF

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CN102723340B
CN102723340B CN201210244424.3A CN201210244424A CN102723340B CN 102723340 B CN102723340 B CN 102723340B CN 201210244424 A CN201210244424 A CN 201210244424A CN 102723340 B CN102723340 B CN 102723340B
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CN102723340A (en
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胡辉勇
宋建军
宣荣喜
张鹤鸣
王海栋
舒斌
王斌
郝跃
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Xidian University
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Abstract

The invention discloses a kind of SOI BJT two strain plane BiCMOS integrated device and preparation method, SOI substrate sheet grows N-type Si extension and do collector region, preparation deep trench isolation, manufactures conventional Si bipolar transistor in bipolar device region; Utilize dry etch process to etch MOS device active area deep trouth, respectively selective epitaxial growth in groove: P type Si layer, P type SiGe graded bedding, P type SiGe layer, P type strained si layer/as nmos device active area and N-type Si layer, N-type strained sige layer, N-type Si cap layers as PMOS device active area; Prepare empty grid, carry out MOS device LDD injection respectively, deposit SiO 2, prepare side wall, autoregistration forms NMOS and PMOS device source and drain; Etch empty grid, deposit SiON gate dielectric layer and W-TiN composite grid, final constituting channel is the BiCMOS integrated device of 22 ~ 45nm.The method makes full use of the conducting channel of the high tensile strain Si of electron mobility and the high compressive strain SiGe of hole mobility respectively as NMOS and PMOS device, effectively improves the performance of BiCMOS integrated device and circuit.

Description

A kind of SOI BJT two strain plane BiCMOS integrated device and preparation method
Technical field
The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of SOI BJT, two strain plane BiCMOS integrated device and preparation method.
Background technology
The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously; It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.
Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid; In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy; At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.
Silicon materials experienced by more than 50 year as semi-conducting material application, traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law; At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.
But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology, particularly when IC chip feature sizes enters nanoscale, from device angles, short channel effect in nanoscale devices, high-field effect, quantum effect, the impact of parasitic parameter, the problems such as technological parameter fluctuation are to device leakage current, subthreshold behavior, ON state, the impact of the performances such as off-state current is more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet novel, the demand of high-velocity electrons system.
The good characteristic of Si material, particularly can easily form exceedingly useful dielectric film---SiO 2film and Si 3n 4film, thus Si material can be utilized to realize the most cheap integrated circuit technology, be developed so far, whole world number, with the equipment of trillion dollars and Technical investment, has made Si base technique define very powerful industry ability; Meanwhile, long-term science research input also makes people to the understanding of Si and technique thereof, reaches very deep, thorough stage, therefore in IC industry, Si technology is mainstream technology, and Si integrated circuit (IC) products is main product, accounts for more than 90% of IC industry; In Si integrated circuit using bipolar transistor as the analog integrated circuit of basic structural unit in electronic system in occupation of consequence, along with the development of Si technology, the performance of Si bipolar transistor also obtain and significantly improves.
In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development; Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack as SiO with Si technique 2the factors such as such passivation layer limit its extensive use and development.
Therefore, current industrial quarters, when manufacture large scale integrated circuit especially hybrid digital-analog integrated circuit, still adopts Si BiCMOS(Si BiCMOS to be Si bipolar transistor BJT+Si CMOS).
Develop the SOI(Silicon on Insulator utilizing and insulating surface has thinner single-crystal semiconductor layer this year: silicon-on-insulator) substrate to be to replace the integrated circuit of large bulk silicon, by using SOI substrate, can reduce the parasitic capacitance between the drain electrode of transistor and substrate, SOI substrate is attracted attention because it can improve the performance of semiconductor integrated circuit for this reason.
Summary of the invention
The object of the present invention is to provide a kind of SOI BJT, two strain plane BiCMOS integrated device and preparation method, to realize, under the condition not changing existing equipment and increase cost, preparing the SOI BJT of 22 ~ 45nm, two strain plane BiCMOS integrated device and integrated circuit.
The object of the present invention is to provide a kind of SOI BJT, two strain plane BiCMOS integrated device, adopt SOI common Si bipolar transistor, strain Si planar channeling nmos device and strain SiGe planar channeling PMOS device.
Further, nmos device conducting channel is strain Si material, is tensile strain along channel direction.
Further, PMOS device conducting channel is strain SiGe material, is compressive strain along channel direction.
Further, in same SOI substrate, bipolar device adopts the preparation of body Si material.
Further, PMOS device adopts quantum well structure.
Another object of the present invention is to the preparation method providing a kind of SOI BJT, two strain plane BiCMOS integrated device, this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100 ~ 150nm, and N-type doping content is 1 × 10 16~ 1 × 10 17cm -3sOI substrate sheet;
Second step, on soi substrates epitaxial growth one deck doping content are 1 × 10 16~ 1 × 10 17cm -3si layer, thickness is 300 ~ 400nm, as collector region;
3rd step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness 2layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO 2, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;
4th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 19~ 1 × 10 20cm -3heavy doping collector electrode;
5th step, at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 18~ 5 × 10 18cm -3base;
6th step, at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 19~ 5 × 10 20cm -3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO 2layer;
7th step, photoetching nmos device active area, utilize dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then, in deep trouth, the method for chemical vapor deposition (CVD) is utilized, at 600 ~ 750 DEG C, continuously growth four layer materials: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 5 × 10 15~ 5 × 10 16cm -3, the second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 5 × 10 15~ 5 × 10 16cm -3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 16~ 5 × 10 17cm -3, the P type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 16~ 5 × 10 17cm -3as the raceway groove of nmos device, form nmos device active area;
8th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO 2, photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then in deep trouth, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material: ground floor to be thickness the be N-type relaxation Si layer of 1.9 ~ 2.8 μm, doping content is 5 × 10 16~ 5 × 10 17cm -3; The N-type strained sige layer of the second layer to be thickness be 12 ~ 15nm, doping content is 5 × 10 16~ 5 × 10 17cm -3, Ge component is 15 ~ 25%; The intrinsic relaxation Si layer of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area; Utilize wet etching, etch away the layer SiO on surface 2;
9th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 3 ~ 5nm in substrate surface deposit a layer thickness 2, as the gate dielectric layer of nmos device and PMOS device, and then utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the Poly-Si of 200 ~ 300nm in substrate surface deposit a layer thickness, etching Poly-Si and SiO 2layer, forms the empty grid of nmos device and PMOS device;
Tenth step, photoetching nmos device active area, carry out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD); Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 ~ 5 × 10 18cm -3p type lightly-doped source drain structure (P-LDD);
11 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3 ~ 5nm 2, utilize dry etching, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device and PMOS device gate electrode side wall; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration 19~ 1 × 10 20cm -3nmos device source-drain area; Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration 19~ 1 × 10 20cm -3pMOS device source-drain area;
12 step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 400 ~ 500nm in substrate surface deposit a layer thickness 2layer; Utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; Utilize the method for physical vapor deposition (PVD), deposit W-TiN composite grid, utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form nmos device and PMOS device grid;
13 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO 2layer, photoetching lead-in wire window, sputter layer of metal over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, depositing metal, photoetching goes between, and form drain electrode, source electrode and gate metal lead-in wire, forming conducting channel is the SOI BJT of 22 ~ 45nm, two strain plane BiCMOS integrated device.
Further, maximum temperature involved in SOI BJT, two strain plane BiCMOS integrated device manufacture process in this preparation method determines according to chemical vapor deposition (CVD) technological temperature in the 7th step, the 8th step, the 9th step, the tenth step, the 11 step, the 12 step and the 13 step, and maximum temperature is less than or equal to 800 DEG C.
Another object of the present invention is to the preparation method providing a kind of SOI BJT, two strain plane BiCMOS integrated circuit, this preparation method comprises the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO 2, thickness is 150nm, and upper layer of material is doping content is 1 × 10 16cm -3n-type Si, thickness is 100nm;
(1b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer;
Step 2, implementation method prepared by isolated area is:
(2a) epitaxial growth one deck doping content is 1 × 10 on soi substrates 16cm -3si layer, thickness is 200nm, as collector region;
(2b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer;
(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;
(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO 2;
(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;
Step 3, implementation method prepared by bipolar device is:
(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 19cm -3heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 18cm -3base;
(3c) at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 19cm -3highly doped emitter, form bipolar transistor;
(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO 2layer;
Step 4, implementation method prepared by nmos device epitaxial material is:
(4a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;
(4b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type Si resilient coating of 200nm, and doping content is 5 × 10 15cm -3;
(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe graded bedding of 1.5 μm, and bottom Ge component is 0%, and top Ge component is 25%, and doping content is 5 × 10 15cm -3;
(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe layer of 200nm, and Ge component is 25%, and doping content is 5 × 10 16cm -3;
(4e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 16cm -3as the raceway groove of nmos device;
Step 5, implementation method prepared by PMOS device active area is:
(5a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO 2;
(5b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.82 μm;
(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.8 μm in PMOS device active area, doping content is 5 × 10 17cm -3;
(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 15nm in PMOS device active area, Ge component is 15%, and doping content is 5 × 10 17cm -3;
(5e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 5nm in PMOS device active area, form PMOS device active area;
(5f) utilize wet etching, etch away the layer SiO on surface 2;
Step 6, implementation method prepared by the empty grid of MOS is:
(6a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 3.5nm at substrate surface deposition thickness 2layer, as the gate dielectric layer of nmos device and PMOS device;
(6b) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the Poly-Si of 300nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO 2layer, forms the empty grid of nmos device and the empty grid of PMOS device;
(6c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD);
(6d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 × 10 18cm -3p type lightly-doped source drain structure (P-LDD);
Step 7, implementation method prepared by nmos device and PMOS device source-drain area is:
(7a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 5nm 2;
(7b) dry etching is utilized, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;
(7c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3nmos device source region and drain region;
(7d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3pMOS device source region and drain region;
Step 8, implementation method prepared by nmos device and PMOS device grid is:
(8a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness 2layer;
(8b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid;
(8c) the empty grid of wet etching, form a groove at gate electrode place;
(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, at substrate surface deposit one deck SiON, thickness is 5nm;
(8e) method of physical vapor deposition (PVD) is utilized, deposit W-TiN composite grid;
(8f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid;
Step 9, the implementation method forming BiCMOS integrated circuit is:
(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO 2layer;
(9b) photoetching lead-in wire window, sputters layer of metal, alloy over the entire substrate, and autoregistration forms metal silicide;
(9c) depositing metal, photoetching goes between, and forms nmos device drain electrode, source electrode and grid, PMOS device drain electrode, source electrode and grid, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming conducting channel is the SOI BJT of 45nm, two strain plane BiCMOS integrated device and circuit.
tool of the present invention has the following advantages:
1. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, PMOS device applies the hole mobility compressive strain sige material higher than body Si material as conducting channel, effectively promotes the electric property of PMOS device; And nmos device applies the electron mobility tensile strain Si material higher than body Si material as conducting channel, effectively promote the electric property of nmos device, therefore the BiCMOS integrated device prepared compared with body Si material of the electric property of the BiCMOS integrated device prepared of the present invention and circuit thereof and circuit performance excellent;
2. SOI BJT, the two strain plane BiCMOS integrated device prepared of the present invention, adopt selective epitaxial technology, respectively in nmos device and PMOS device active area selective growth tensile strain Si and compressive strain sige material, nmos device and the electric property such as PMOS device frequency performance and current driving ability are obtained promote, thus BiCMOS device and performance of integrated circuits obtain enhancing simultaneously;
3. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, in order to effectively suppress short-channel effect, introducing light dope source and drain (LDD) technique, improve device performance;
4. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, PMOS device is quantum well devices, namely strained sige layer is between Si cap layers and body Si layer, compared with surface channel device, reduce the interface scattering in channel carrier transport process, inhibit the reduction of mobility; Hole barrier simultaneously between Si cap layers and strained sige layer, inhibits hot carrier to inject in gate medium, improves the reliability of BiCMOS integrated device and circuit;
5. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, adopt the SiON of high-k to replace traditional pure SiO 2do gate medium, enhance the grid-control ability of MOS device, improve the reliability of device;
6. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device process, have employed metal gate mosaic technology (damascene process) and prepare gate electrode, this gate electrode is metal W-TiN composite construction, due to the TiN of lower floor and strain Si and strain SiGe material work functions difference less, improve the electrology characteristic of device, the W on upper strata then can reduce the resistance of gate electrode, achieves the optimization of gate electrode;
7. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.
Accompanying drawing explanation
Fig. 1 is the realization flow figure of SOI BJT provided by the invention, two strain plane BiCMOS integrated device preparation method.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Embodiments provide a kind of SOI BJT, two strain plane BiCMOS integrated device, adopt SOI common Si bipolar transistor, strain Si planar channeling nmos device and strain SiGe planar channeling PMOS device.
As a prioritization scheme of the embodiment of the present invention, nmos device conducting channel is strain Si material, is tensile strain along channel direction.
As a prioritization scheme of the embodiment of the present invention, PMOS device conducting channel is strain SiGe material, is compressive strain along channel direction.
As a prioritization scheme of the embodiment of the present invention, in same SOI substrate, bipolar device adopts the preparation of body Si material.
As a prioritization scheme of the embodiment of the present invention, PMOS device adopts quantum well structure.
Referring to accompanying drawing 1, preparation technology's flow process of SOI BJT of the present invention, two strain plane BiCMOS integrated device and circuit is described in further detail.
Embodiment 1: prepare the SOI BJT that conducting channel is 45nm, two strain plane BiCMOS integrated device and circuit, concrete steps are as follows:
Step 1, epitaxial growth.
(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO 2, thickness is 150nm, and upper layer of material is doping content is 1 × 10 16cm -3n-type Si, thickness is 100nm;
(1b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer.
Step 2, prepared by isolated area.
(2a) epitaxial growth one deck doping content is 1 × 10 on soi substrates 16cm -3si layer, thickness is 200nm, as collector region;
(2b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer;
(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;
(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO 2;
(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.
Step 3, prepared by bipolar device.
(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 19cm -3heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 18cm -3base;
(3c) at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 19cm -3highly doped emitter, form bipolar transistor;
(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO 2layer.
Step 4, prepared by nmos device epitaxial material.
(4a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;
(4b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type Si resilient coating of 200nm, and doping content is 5 × 1015cm -3;
(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe graded bedding of 1.5 μm, and bottom Ge component is 0%, and top Ge component is 25%, and doping content is 5 × 10 15cm -3;
(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe layer of 200nm, and Ge component is 25%, and doping content is 5 × 10 16cm -3;
(4e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 16cm -3as the raceway groove of nmos device.
Step 5, prepared by PMOS device active area.
(5a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO 2;
(5b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.82 μm;
(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.8 μm in PMOS device active area, doping content is 5 × 10 17cm -3;
(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 15nm in PMOS device active area, Ge component is 15%, and doping content is 5 × 10 17cm -3;
(5e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 5nm in PMOS device active area, form PMOS device active area;
(5f) utilize wet etching, etch away the layer SiO on surface 2.
Step 6, the empty grid preparation of MOS.
(6a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 3.5nm at substrate surface deposition thickness 2layer, as the gate dielectric layer of nmos device and PMOS device;
(6b) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the Poly-Si of 300nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO 2layer, forms the empty grid of nmos device and the empty grid of PMOS device;
(6c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD);
(6d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 × 10 18cm -3p type lightly-doped source drain structure (P-LDD).
Step 7, nmos device and the preparation of PMOS device source-drain area.
(7a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 5nm 2;
(7b) dry etching is utilized, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;
(7c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3nmos device source region and drain region;
(7d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3pMOS device source region and drain region.
Step 8, nmos device and the preparation of PMOS device grid.
(8a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness 2layer;
(8b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid;
(8c) the empty grid of wet etching, form a groove at gate electrode place;
(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, at substrate surface deposit one deck SiON, thickness is 5nm;
(8e) method of physical vapor deposition (PVD) is utilized, deposit W-TiN composite grid;
(8f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid.
Step 9, forms BiCMOS integrated circuit.
(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO 2layer;
(9b) photoetching lead-in wire window, sputters layer of metal, alloy over the entire substrate, and autoregistration forms metal silicide;
(9c) depositing metal, photoetching goes between, and forms nmos device drain electrode, source electrode and grid, PMOS device drain electrode, source electrode and grid, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming conducting channel is the SOI BJT of 45nm, two strain plane BiCMOS integrated device and circuit.
Embodiment 2: prepare the SOI BJT that conducting channel is 30nm, two strain plane BiCMOS integrated device and circuit, concrete steps are as follows:
Step 1, epitaxial growth.
(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO 2, thickness is 300nm, and upper layer of material is doping content is 5 × 10 16cm -3n-type Si, thickness is 120nm;
(1b) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness 2layer.
Step 2, prepared by isolated area.
(2a) epitaxial growth one deck doping content is 5 × 10 on soi substrates 16cm -3si layer, thickness is 350nm, as collector region;
(2b) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness 2layer;
(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 4 μm;
(2d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO 2;
(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.
Step 3, prepared by bipolar device.
(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 900 DEG C, annealing 90min activator impurity, forming doping content is 5 × 10 19cm -3heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 900 DEG C, annealing 45min activator impurity, forming doping content is 3 × 10 18cm -3base;
(3c) at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 900 DEG C, annealing 45min activator impurity, becomes doping content to be 1 × 10 20cm -3highly doped emitter, form bipolar transistor;
(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO 2layer.
Step 4, prepared by nmos device epitaxial material.
(4a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;
(4b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type Si resilient coating of 300nm at nmos device active area selective growth thickness, doping content is 1 × 10 16cm -3;
(4c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type SiGe graded bedding of 1.8 μm at nmos device active area selective growth thickness, bottom Ge component is 0%, and top Ge component is 20%, and doping content is 1 × 10 16cm -3;
(4d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type SiGe layer of 300nm at nmos device active area selective growth thickness, Ge component is 20%, and doping content is 1 × 10 17cm -3;
(4e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 18nm at nmos device active area selective growth thickness, doping content is 1 × 10 17cm -3as the raceway groove of NMOS device.
Step 5, prepared by PMOS device active area.
(5a) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at substrate surface deposit one deck SiO 2;
(5b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.42 μm;
(5c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.4 μm in PMOS device active area, doping content is 1 × 10 17cm -3;
(5d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 14nm in PMOS device active area, Ge component is 20%, and doping content is 1 × 10 17cm -3;
(5e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 4nm in PMOS device active area, form PMOS device active area;
(5f) utilize wet etching, etch away the layer SiO on surface 2.
Step 6, the empty grid preparation of MOS.
(6a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 4nm at substrate surface deposition thickness 2layer, as the gate dielectric layer of nmos device and PMOS device;
(6b) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the Poly-Si of 240nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO 2layer, forms the empty grid of nmos device and the empty grid of PMOS device;
(6c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 3 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD);
(6d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 3 × 10 18cm -3p type lightly-doped source drain structure (P-LDD).
Step 7, nmos device and the preparation of PMOS device source-drain area.
(7a) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm 2;
(7b) dry etching is utilized, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;
(7c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 8 × 10 that autoregistration generates impurity concentration 19cm -3nmos device source region and drain region;
(7d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 8 × 10 that autoregistration generates impurity concentration 19cm -3pMOS device source region and drain region.
Step 8, nmos device and the preparation of PMOS device grid.
(8a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 450nm in substrate surface deposit a layer thickness 2layer;
(8b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid;
(8c) the empty grid of wet etching, form a groove at gate electrode place;
(8d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, at substrate surface deposit one deck SiON, thickness is 3nm;
(8e) method of physical vapor deposition (PVD) is utilized, deposit W-TiN composite grid;
(8f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid.
Step 9, forms BiCMOS integrated circuit.
(9a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO 2layer;
(9b) photoetching lead-in wire window, sputters layer of metal, alloy over the entire substrate, and autoregistration forms metal silicide;
(9c) depositing metal, photoetching goes between, and forms nmos device drain electrode, source electrode and grid, PMOS device drain electrode, source electrode and grid, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming conducting channel is the SOI BJT of 30nm, two strain plane BiCMOS integrated device and circuit.
Embodiment 3: prepare the SOI BJT that conducting channel is 22nm, two strain plane BiCMOS integrated device and circuit, concrete steps are as follows:
Step 1, epitaxial growth.
(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO 2, thickness is 400nm, and upper layer of material is doping content is 1 × 10 17cm -3n-type Si, thickness is 150nm;
(1b) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness 2layer.
Step 2, prepared by isolated area.
(2a) epitaxial growth one deck doping content is 1 × 10 on soi substrates 17cm -3si layer, thickness is 400nm, as collector region;
(2b) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness 2layer;
(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 5 μm;
(2d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO 2;
(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.
Step 3, prepared by bipolar device.
(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 1 × 10 20cm -3heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 950 DEG C, annealing 30min activator impurity, forming doping content is 5 × 10 18cm -3base;
(3c) at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 950 DEG C, annealing 30min activator impurity, becomes doping content to be 5 × 10 20cm -3highly doped emitter, form bipolar transistor;
(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO 2layer.
Step 4, prepared by nmos device epitaxial material.
(4a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;
(4a) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type Si resilient coating of 200nm at nmos device active area selective growth thickness, doping content is 5 × 10 15cm -3;
(4b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type SiGe graded bedding of 1.5 μm at nmos device active area selective growth thickness, bottom Ge component is 0%, and top Ge component is 25%, and doping content is 5 × 10 15cm -3;
(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type SiGe layer of 200nm at nmos device active area selective growth thickness, Ge component is 25%, and doping content is 5 × 10 16cm -3;
(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 15nm at nmos device active area selective growth thickness, doping content is 5 × 10 16cm -3as the raceway groove of nmos device.
Step 5, prepared by PMOS device active area.
(5a) method of chemical vapor deposition (CVD) is utilized, at 800 DEG C, at substrate surface deposit one deck SiO 2;
(5b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 μm;
(5c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 1.9 μm in PMOS device active area, doping content is 5 × 10 16cm -3;
(5d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 12nm in PMOS device active area, Ge component is 25%, and doping content is 5 × 10 16cm -3;
(5e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 3nm in PMOS device active area, form PMOS device active area;
(5f) utilize wet etching, etch away the layer SiO on surface 2.
Step 6, the empty grid preparation of MOS.
(6a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 3nm at substrate surface deposition thickness 2layer, as the gate dielectric layer of nmos device and PMOS device;
(6b) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the Poly-Si of 200nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO 2layer, forms the empty grid of nmos device and the empty grid of PMOS device;
(6c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 5 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD);
(6d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 5 × 10 18cm -3p type lightly-doped source drain structure (P-LDD).
Step 7, nmos device and the preparation of PMOS device source-drain area.
(7a) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm 2;
(7b) dry etching is utilized, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;
(7c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 1 × 10 that autoregistration generates impurity concentration 20cm -3nmos device source region and drain region;
(7d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 1 × 10 that autoregistration generates impurity concentration 20cm -3pMOS device source region and drain region.
Step 8, CMOS source and drain and grid preparation.
(8a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness 2layer;
(8b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid;
(8c) the empty grid of wet etching, form a groove at gate electrode place;
(8d) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5nm;
(8e) method of physical vapor deposition (PVD) is utilized, deposit W-TiN composite grid;
(8f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid.
Step 9, forms BiCMOS integrated circuit.
(9a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO 2layer;
(9b) photoetching lead-in wire window, sputters layer of metal, alloy over the entire substrate, and autoregistration forms metal silicide;
(9c) depositing metal, photoetching goes between, and forms nmos device drain electrode, source electrode and grid, PMOS device drain electrode, source electrode and grid, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming conducting channel is the SOI BJT of 22nm, two strain plane BiCMOS integrated device and circuit.
The SOI BJT that the embodiment of the present invention provides, two strain plane BiCMOS integrated device and preparation method's tool have the following advantages:
1. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, PMOS device applies the hole mobility compressive strain sige material higher than body Si material as conducting channel, effectively promotes the electric property of PMOS device; And nmos device applies the electron mobility tensile strain Si material higher than body Si material as conducting channel, effectively promote the electric property of nmos device, therefore the BiCMOS integrated device prepared compared with body Si material of the electric property of the BiCMOS integrated device prepared of the present invention and circuit thereof and circuit performance excellent;
2. SOI BJT, the two strain plane BiCMOS integrated device prepared of the present invention, adopt selective epitaxial technology, respectively in nmos device and PMOS device active area selective growth tensile strain Si and compressive strain sige material, nmos device and the electric property such as PMOS device frequency performance and current driving ability are obtained promote, thus BiCMOS device and performance of integrated circuits obtain enhancing simultaneously;
3. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, in order to effectively suppress short-channel effect, introducing light dope source and drain (LDD) technique, improve device performance;
4. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, PMOS device is quantum well devices, namely strained sige layer is between Si cap layers and body Si layer, compared with surface channel device, reduce the interface scattering in channel carrier transport process, inhibit the reduction of mobility; Hole barrier simultaneously between Si cap layers and strained sige layer, inhibits hot carrier to inject in gate medium, improves the reliability of BiCMOS integrated device and circuit;
5. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, adopt the SiON of high-k to replace traditional pure SiO 2do gate medium, enhance the grid-control ability of MOS device, improve the reliability of device;
6. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device process, have employed metal gate mosaic technology (damascene process) and prepare gate electrode, this gate electrode is metal W-TiN composite construction, due to the TiN of lower floor and strain Si and strain SiGe material work functions difference less, improve the electrology characteristic of device, the W on upper strata then can reduce the resistance of gate electrode, achieves the optimization of gate electrode;
7. the present invention prepare SOI BJT, in two strain plane BiCMOS integrated device, bipolar device adopts the collector region thickness of SOI substrate thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (3)

1. a preparation method for SOI BJT two strain plane BiCMOS integrated device, it is characterized in that, this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100 ~ 150nm, and N-type doping content is 1 × 10 16~ 1 × 10 17cm -3sOI substrate sheet;
Second step, on soi substrates epitaxial growth one deck doping content are 1 × 10 16~ 1 × 10 17cm -3si layer, thickness is 300 ~ 400nm, as collector region;
3rd step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness 2layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO 2, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;
4th step, contact zone, photoetching collector region, carry out the injection of N-type impurity to collector region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 19~ 1 × 10 20cm -3heavy doping collector electrode;
5th step, at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 1 × 10 18~ 5 × 10 18cm -3base;
6th step, at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forming doping content is 5 × 10 19~ 5 × 10 20cm -3highly doped emitter, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO 2layer;
7th step, photoetching nmos device active area, utilize dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then, in deep trouth, the method for chemical vapor deposition (CVD) is utilized, at 600 ~ 750 DEG C, continuously growth four layer materials: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 5 × 10 15~ 5 × 10 16cm -3, the second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 5 × 10 15~ 5 × 10 16cm -3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 16~ 5 × 10 17cm -3, the P type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 16~ 5 × 10 17cm -3as the raceway groove of nmos device, form nmos device active area;
8th step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO 2, photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 1.92 ~ 2.82 μm; Then in deep trouth, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, selective epitaxial growth trilaminate material: ground floor to be thickness the be N-type relaxation Si layer of 1.9 ~ 2.8 μm, doping content is 5 × 10 16~ 5 × 10 17cm -3; The N-type strained sige layer of the second layer to be thickness be 12 ~ 15nm, doping content is 5 × 10 16~ 5 × 10 17cm -3, Ge component is 15 ~ 25%; The intrinsic relaxation Si layer of third layer to be thickness be 3 ~ 5nm, forms PMOS device active area; Utilize wet etching, etch away the layer SiO on surface 2;
9th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 3 ~ 5nm in substrate surface deposit a layer thickness 2, as the gate dielectric layer of nmos device and PMOS device, and then utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the Poly-Si of 200 ~ 300nm in substrate surface deposit a layer thickness, etching Poly-Si and SiO 2layer, forms the empty grid of nmos device and PMOS device;
Tenth step, photoetching nmos device active area, carry out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD); Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 ~ 5 × 10 18cm -3p type lightly-doped source drain structure (P-LDD);
11 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3 ~ 5nm 2, utilize dry etching, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device and PMOS device gate electrode side wall; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration 19~ 1 × 10 20cm -3nmos device source-drain area; Photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration 19~ 1 × 10 20cm -3pMOS device source-drain area;
12 step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 400 ~ 500nm in substrate surface deposit a layer thickness 2layer; Utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; Utilize the method for physical vapour deposition (PVD) (PVD), deposit W-TiN composite grid, chemico-mechanical polishing (CMP) method is utilized to remove the metal on surface, stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device and PMOS device grid;
13 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO 2layer, photoetching lead-in wire window, sputter layer of metal alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, depositing metal, photoetching goes between, form drain electrode, source electrode and gate metal lead-in wire, forming conducting channel is the SOI BJT of 22 ~ 45nm, two strain plane BiCMOS integrated device.
2. the preparation method of SOI BJT according to claim 1 two strain plane BiCMOS integrated device, it is characterized in that, in this preparation method, in SOI BJT two strain plane BiCMOS integrated device manufacture process, involved maximum temperature determines to chemical vapor deposition (CVD) technological temperature in the 13 step according to the 7th step, and maximum temperature is less than or equal to 800 DEG C.
3. a preparation method for SOI BJT two strain plane BiCMOS integrated circuit, it is characterized in that, this preparation method comprises the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose SOI substrate sheet, this SOI substrate sheet lower layer support material is Si, and intermediate layer is SiO 2, thickness is 150nm, and upper layer of material is doping content is 1 × 10 16cm -3n-type Si, thickness is 100nm;
(1b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer;
Step 2, implementation method prepared by isolated area is:
(2a) epitaxial growth one deck doping content is 1 × 10 on soi substrates 16cm -3si layer, thickness is 200nm, as collector region;
(2b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness 2layer;
(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;
(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO 2;
(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;
Step 3, implementation method prepared by bipolar device is:
(3a) contact zone, photoetching collector region, carries out the injection of N-type impurity to collector region, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 19cm -3heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2layer, photoetching base, carries out the injection of p type impurity to base, and at 800 DEG C, annealing 90min activator impurity, forming doping content is 1 × 10 18cm -3base;
(3c) at substrate surface thermal oxidation one SiO 2layer, photoetching emitter region, carries out the injection of N-type impurity to substrate, and at 800 DEG C, annealing 90min activator impurity, becomes doping content to be 5 × 10 19cm -3highly doped emitter, form bipolar transistor;
(3d) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO 2layer;
Step 4, implementation method prepared by nmos device epitaxial material is:
(4a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;
(4b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type Si resilient coating of 200nm, and doping content is 5 × 10 15cm -3;
(4c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe graded bedding of 1.5 μm, and bottom Ge component is 0%, and top Ge component is 25%, and doping content is 5 × 10 15cm -3;
(4d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type SiGe layer of 200nm, and Ge component is 25%, and doping content is 5 × 10 16cm -3;
(4e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in nmos device active area, optionally growth thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 16cm -3as the raceway groove of nmos device;
Step 5, implementation method prepared by PMOS device active area is:
(5a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO 2;
(5b) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the deep trouth that the degree of depth is 2.82 μm;
(5c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type relaxation Si layer that a layer thickness is 2.8 μm in PMOS device active area, doping content is 5 × 10 17cm -3;
(5d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the N-type strained sige layer that a layer thickness is 15nm in PMOS device active area, Ge component is 15%, and doping content is 5 × 10 17cm -3;
(5e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, optionally grow the intrinsic relaxation Si cap layers of a layer thickness 5nm in PMOS device active area, form PMOS device active area;
(5f) utilize wet etching, etch away the layer SiO on surface 2;
Step 6, implementation method prepared by the empty grid of MOS is:
(6a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 3.5nm at substrate surface deposition thickness 2layer, as the gate dielectric layer of nmos device and PMOS device;
(6b) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the Poly-Si of 300nm in substrate surface deposit a layer thickness, etching Poly-Si, SiO 2layer, forms the empty grid of nmos device and the empty grid of PMOS device;
(6c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 18cm -3n-type lightly-doped source drain structure (N-LDD);
(6d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and forming doping content is 1 × 10 18cm -3p type lightly-doped source drain structure (P-LDD);
Step 7, implementation method prepared by nmos device and PMOS device source-drain area is:
(7a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 5nm 2;
(7b) dry etching is utilized, the SiO on etched substrate surface 2, retain Ploy-Si sidewall sections, form nmos device gate electrode side wall and PMOS device gate electrode side wall;
(7c) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3nmos device source region and drain region;
(7d) photoetching PMOS device active area, carries out P type ion implantation to PMOS device, and it is 5 × 10 that autoregistration generates impurity concentration 19cm -3pMOS device source region and drain region;
Step 8, implementation method prepared by nmos device and PMOS device grid is:
(8a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness 2layer;
(8b) utilize chemico-mechanical polishing (CMP) method flat surface, then use dry etch process etching surface SiO 2to empty grid upper surface, expose empty grid;
(8c) the empty grid of wet etching, form a groove at gate electrode place;
(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, at substrate surface deposit one deck SiON, thickness is 5nm;
(8e) method of physical vapour deposition (PVD) (PVD) is utilized, deposit W-TiN composite grid;
(8f) utilize chemico-mechanical polishing (CMP) method to remove the metal on surface, the stop layer using W-TiN as chemico-mechanical polishing (CMP), thus form nmos device grid and PMOS device grid;
Step 9, the implementation method forming BiCMOS integrated circuit is:
(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO 2layer;
(9b) photoetching lead-in wire window, sputters layer of metal alloy over the entire substrate, and autoregistration forms metal silicide;
(9c) depositing metal, photoetching goes between, form nmos device drain electrode, source electrode and grid, PMOS device drain electrode, source electrode and grid, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming conducting channel is the SOI BJT of 45nm, two strain plane BiCMOS integrated device and circuit.
CN201210244424.3A 2012-07-16 2012-07-16 A kind of SOI BJT two strain plane BiCMOS integrated device and preparation method Expired - Fee Related CN102723340B (en)

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