CN102916015B

CN102916015B - Strain Si BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on SOI SiGe HBT (Heterojunction Bipolar Transistor) and preparation method thereof

Info

Publication number: CN102916015B
Application number: CN201210244722.2A
Authority: CN
Inventors: 张鹤鸣; 王海栋; 胡辉勇; 宋建军; 宣荣喜; 舒斌; 戴显英; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2014-12-31
Anticipated expiration: 2032-07-16
Also published as: CN102916015A

Abstract

The invention discloses a strain Si BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on SOI SiGe HBT (Heterojunction Bipolar Transistor) and a preparation method thereof. The preparation method comprises the following steps: growing N-type Si epitaxy on a substrate, preparing a deep-trench isolator, forming a collector contact region, dryly etching to form a nitride side wall, wetly etching to form a base window, selectively growing a SiGe base region, and photoetching a collector window, removing Poly-Si to form a SiGe HBT device; photoetching an MOS (Metal Oxide Semiconductor) device active area groove, respectively and continuously growing Si buffer layer, gradient SiGe layer, fixed component SiGe layer, N-type strain Si channel layer, Si buffer layer and the like in the MOS device active area groove, and preparing a drain electrode and a grid electrode to form a PMOS (Positive channel Metal Oxide Semiconductor) device; and preparing an NMOS (Negative channel Metal Oxide Semiconductor) device grid dielectric layer and a grid polycrystal to form an NMOS device. The characteristic of tension strain Si material such as mobility anisotropy is fully utilized to prepare the BiCMOS integrated device with strengthened performance and a circuit thereof.

Description

A kind of strain Si BiCMOS integrated device based on SOI SiGe HBT and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to and a kind ofly prepare strain Si BiCMOS integrated device based on SOI SiGe HBT and preparation method.

Background technology

The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously; It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid; In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy; At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

Silicon materials experienced by more than 50 year as semi-conducting material application, traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law; At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.

But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology, particularly when IC chip feature sizes enters nanoscale, from device angles, short channel effect in nanoscale devices, high-field effect, quantum effect, the impact of parasitic parameter, the problems such as technological parameter fluctuation are to device leakage current, subthreshold behavior, ON state, the impact of the performances such as off-state current is more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet novel, the demand of high-velocity electrons system.

In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that Si BiCMOS technology manufactures, especially frequency performance, is greatly limited; And for SiGe BiCMOS technology, although bipolar transistor have employed SiGe HBT, the unipolar device promoted for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, promote further so these all limit BiCMOS performance of integrated circuits ground.

Summary of the invention

The object of the invention is to utilize and prepare strain Si vertical-channel PMOS device, strain Si planar channeling nmos device and SiGe HBT on a substrate slice, form strain BiCMOS integrated device, to realize the optimization of device and performance of integrated circuits.

The object of the present invention is to provide a kind of strain Si BiCMOS integrated device based on SOI SiGe HBT and circuit, nmos device and PMOS device are strain Si MOS device, and bipolar device is SOI tri-polycrystal SiGe HBT device.

Nmos device strained Si channel is horizontal channel further, in cmos device, is tensile strain along channel direction.

PMOS device strained Si channel is vertical-channel further, in cmos device, is compressive strain, and is hollow structure along channel direction.

Further, SiGe HBT device adopts SOI substrate.

Further, SiGe HBT device emitter, base stage and collector electrode all adopt polycrystalline silicon material.

Further, SiGe HBT device fabrication process adopts self-registered technology, and is whole plane structure.

Another object of the present invention is to provide a kind of strain Si BiCMOS integrated device preparation method based on SOI SiGe HBT, this preparation method comprises the steps:

The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100 ~ 150nm, and N-type doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3sOI substrate sheet;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the N-type Si epitaxial loayer of 50 ~ 100nm in Grown a layer thickness, as collector region, this layer of doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

3rd step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in epitaxial si layer superficial growth a layer thickness ₂layer, photoetching deep trench isolation, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 3 ~ 5 μm, and recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂; Finally, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

4th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 500 ~ 700nm in epitaxial si layer surface deposition a layer thickness ₂layer, photoetching collector contact district window, carries out phosphorus injection to substrate, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, then by substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

5th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit two layer material: ground floor is SiO ₂layer, thickness is 20 ~ 40nm; The second layer is P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 × 10 ²⁰~ 1 × 10 ²¹cm ^-3;

6th step, photoetching Poly-Si, form outer base area, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

7th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit layer of sin layer, thickness is 50 ~ 100nm, photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;

8th step, utilize wet etching, to SiO in window ₂layer carries out excessive erosion, forms region, base, utilizes chemical vapor deposition (CVD) method, and at 600 ~ 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, thickness is 20 ~ 60nm;

9th step, photoetching collector electrode window, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit Poly-Si, thickness is 200 ~ 400nm, again phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

Tenth step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, photoetching collector contact hole, and phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer;

11 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

12 step, photoetching PMOS device active area, by dry etch process, in PMOS device active area, etch the deep trouth that the degree of depth is 2.1 ~ 3.2 μm, oxide layer is carved thoroughly, utilizes chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, at PMOS device active area (i.e. deep trouth) selective epitaxial growth seven layer material: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device; The P type strained si layer/of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD); The N-type strained si layer/of layer 5 to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD); Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the source region of PMOS device;

13 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂; Photoetching nmos device active area, in nmos device active area, etches the deep trouth that the degree of depth is 1.9 ~ 2.8 μm, oxide layer is carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, at nmos device active area selective epitaxial growth four layer material: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of the 4th layer of to be thickness be 10 ~ 15nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

14 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching PMOS device source and drain isolated area, utilizes dry etch process, goes out at this region etch the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂, form the electrode shallow-trench isolation of MOS device;

15 step, photoetching leak trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.4 ~ 0.7 μm of leakage groove; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

16 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 ~ 0.7 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as the gate dielectric layer of PMOS device; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in gate groove, deposit doping content is 1 ~ 5 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove; Photoetching gate medium and grid Poly-SiGe, form grid and source electrode, final formation PMOS device structure;

17 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at nmos device active area deposition thickness ₂layer, as the gate dielectric layer of nmos device; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, be the P type Poly-SiGe of 200 ~ 300nm at nmos device active area deposition thickness, doping content is 1 ~ 5 × 10 ²⁰cm ^-3, Ge component is 10 ~ 30%, photoetching gate medium and grid Poly-SiGe, forms grid; Utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 1 ~ 5 × 10 ¹⁸cm ^-3;

18 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, utilizes dry etch process, etches away the SiO on surface ₂, form nmos device grid curb wall, utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content in nmos device source region and drain region reach 1 ~ 5 × 10 ²⁰cm ^-3;

19 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching lead-in wire window, sputter layer of metal nickel (Ni) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact; Photoetching goes between, form the drain electrode of MOS device, source electrode and gate metal lead-in wire, and the emitter of SiGe HBT, base stage and collector electrode metal lead-in wire, forming base thickness is 20 ~ 60nm, the strain Si BiCMOS integrated device based on SOI SiGe HBT of collector region thickness to be 150 ~ 250nm, MOS conducting channel be 22 ~ 45nm.

Further, PMOS device channel length determines according to the N-type strained si layer/thickness of the 12 step deposit, and get 22 ~ 45nm, the channel length of nmos device is determined by technique, gets 22 ~ 45nm.

Determine to chemical vapor deposition (CVD) technological temperature in the 19 step according to the 12 step based on maximum temperature involved in the strain Si BiCMOS integrated device of SOI SiGe HBT and circuit fabrication process further, in this preparation method, maximum temperature is less than or equal to 800 DEG C.

Further, collector region thickness decides according to the thickness of Si epitaxial loayer of first step SOI upper strata Si thickness and second step growth, gets 150 ~ 250nm.

Further, base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20 ~ 60nm.

Another kind of object of the present invention is to provide a kind of strain Si BiCMOS integrated circuit preparation based on SOI SiGe HBT, and this preparation method comprises the steps:

Step 1, epitaxially grown implementation method is as follows:

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 150nm, and upper layer of material is doping content is 1 × 10 ¹⁶cm ^-3n-type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 50nm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

Step 2, implementation method prepared by deep trench isolation is as follows:

(2a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in epitaxial si layer superficial growth a layer thickness ₂layer;

(2b) photoetching deep trench isolation region;

(2c) go out at deep trench isolation region dry etching the deep trouth that the degree of depth is 3 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂, and fill up in deep trouth;

(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

Step 3, implementation method prepared by collector contact district is as follows:

(3a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, answer deposit a layer thickness to be the SiO of 500nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector contact area;

(3d) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation;

Step 4, implementation method prepared by base contact is as follows:

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 DEG C, is the SiO of 20nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 600 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm;

Step 5, implementation method prepared by base material is as follows:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) wet etching is utilized, to SiO in window ₂layer carries out excessive erosion, forms region, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm;

Step 6, implementation method prepared by emitter region is as follows:

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 600 DEG C, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

(6c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer;

Step 7, the implementation method that HBT device is formed is as follows:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer, anneal 120s at 950 DEG C of temperature, activator impurity, forms HBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 8, prepared by PMOS device active area epitaxial material;

(8a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 2.1 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 200nm, doping content 1 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.5 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 25%, and doping content is 1 × 10 ¹⁸cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one deck Ge component is 25% on the sige layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(8e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 3nm, and doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(8f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 22nm, and as PMOS device channel region, doping content is 5 × 10 ¹⁶cm ^-3;

(8g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 3nm, and doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(8h) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 200nm is fixed as 25%, and as PMOS device source region, doping content is 5 × 10 ¹⁹cm ^-3, form PMOS device active area;

Step 9, implementation method prepared by nmos device active area materials is as follows:

(9a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(9b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 1.9 μm, oxide layer is carved thoroughly;

(9c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the P type Si resilient coating of 200nm in nmos device active area selective growth a layer thickness, doping content 1 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.5 μm, Ge component gradient distribution, and bottom is 0%, and top is 25%, and doping content is 1 × 10 ¹⁵cm ^-3;

(9e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one deck Ge component is 25% on the sige layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 × 10 ¹⁶cm ^-3;

(9f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow the P type strained si layer/that a layer thickness is 10nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁶cm ^-3, form nmos device active area;

Step 10, implementation method prepared by PMOS device isolation and leakage groove is as follows:

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(10b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.3 μm;

(10c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(10d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.4 μm of leakage groove;

(10e) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 11, the implementation method that PMOS device is formed is as follows:

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂;

(11b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 μm of gate groove;

(11c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 300 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 6nm;

(11d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in gate groove, deposit doping content is 1 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 30%, is filled up by PMOS device gate groove;

(11e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grid and source electrode, finally form PMOS device;

Step 12, the implementation method that nmos device is formed is as follows:

(12a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(12b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of 6nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(12c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 30%, and thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^-3;

(12d) photoetching gate medium and grid Poly-SiGe, forms grid;

(12e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(12f) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 3nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂form grid side wall;

(12g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 1 × 10 ²⁰cm ^-3, finally form nmos device;

Step 13, the implementation method forming BiCMOS integrated circuit is as follows:

(13a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(13b) lithography fair lead;

(13c) at substrate surface sputtering layer of metal nickel (Ni), alloy;

(13d) photoetching lead-in wire, form PMOS device drain metal lead-in wire, source metal lead-in wire, gate metal goes between, nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming base thickness is 20nm, the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of collector region thickness to be 150nm, MOS conducting channel be 22nm.

tool of the present invention has the following advantages:

1. the present invention manufacture based in the strain Si BiCMOS integrated device structure of SOI SiGe HBT, CMOS part have employed strain Si material and manufactures conducting channel, because strain Si material carrier mobility is far above body Si material, therefore by the circuit performance excellence that simulation and the hybrid digital-analog integrated circuit performance of the manufacture of this BiCMOS device architecture comparatively use body Si to manufacture;

2. the present invention manufacture based on the CMOS structure in the strain Si BiCMOS integrated device structure of SOI SiGe HBT, take full advantage of the anisotropy of strain Si material stress, introduce tensile strain in the horizontal direction, improve nmos device electron mobility; Introduce compressive strain in the vertical direction, improve PMOS device hole mobility; Therefore, this performance such as device frequency and current driving ability is higher than the relaxation Si cmos device of same size;

3. in preparation process of the present invention, strained si layer/chemical vapor deposition (CVD) method deposit, accurately can control growth thickness, and the channel length of PMOS device in CMOS is the thickness of strained si layer/, thus avoid small size photoetching, decrease process complexity, reduce cost;

4. what prepared by the present invention is hollow based on the raceway groove of PMOS device in the strain Si BiCMOS integrated device structure of SOI SiGe HBT, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

5. the present invention prepare based on the CMOS structure in the strain Si BiCMOS integrated device of SOI SiGe HBT, PMOS device have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of MOS device, enhance the electric property of cmos device;

6. the present invention prepare based on the CMOS structure in the strain Si BiCMOS integrated device of SOI SiGe HBT, nmos device adopts Poly-SiGe material as gate electrode, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

7. the present invention prepares stress CMOS device is after bipolar device manufacture completes, and the maximum temperature related in its technical process is 800 DEG C, lower than the technological temperature causing strain SiGe base stress relaxation, effectively keep the characteristic of strain SiGe, improve the performance of integration integrated circuits;

8. what prepared by the present invention is thin compared with traditional devices based on the collector region thickness of SOI SiGe HBT in the strain Si BiCMOS integrated device of SOI SiGe HBT, therefore, there is collector region effect extending transversely in this device, and two dimensional electric field can be formed in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices;

9. the strain Si BiCMOS integrated device based on SOI SiGe HBT prepared of the present invention, middle SOI SiGe HBT, in preparation process, adopts Fully self-aligned process, efficiently reduces dead resistance and electric capacity, improve electric current and the frequency characteristic of device;

10. the strain Si BiCMOS integrated device based on SOI SiGe HBT prepared of the present invention, middle SOI SiGe HBT emitter, base stage and collector electrode all adopt polycrystalline, polycrystalline can partly be produced on above oxide layer, reduce the area of device active region, thus reduction device size, improve the integrated level of circuit.

Accompanying drawing explanation

Fig. 1 is the realization flow figure of the strain Si BiCMOS integrated device preparation method based on SOI SiGe HBT provided by the invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of strain Si BiCMOS integrated device based on SOI SiGe HBT and circuit, nmos device and PMOS device are strain Si MOS device, and bipolar device is SOI tri-polycrystal SiGe HBT device.

As a prioritization scheme of the embodiment of the present invention, in cmos device, nmos device strained Si channel is horizontal channel, is tensile strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, in cmos device, PMOS device strained Si channel is vertical-channel, is compressive strain along channel direction, and is hollow structure.

As a prioritization scheme of the embodiment of the present invention, SiGe HBT device adopts SOI substrate.

As a prioritization scheme of the embodiment of the present invention, SiGe HBT device emitter, base stage and collector electrode all adopt polycrystalline silicon material.

As a prioritization scheme of the embodiment of the present invention, SiGe HBT device fabrication process adopts self-registered technology, and is whole plane structure.

Referring to accompanying drawing 1, the present invention's preparation is described in further detail based on the strain Si BiCMOS integrated device of SOI SiGe HBT and the technological process of circuit.

Embodiment 1: preparation channel length is the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of 22nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 50nm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3.

Step 2, prepared by deep trench isolation.

(2b) photoetching deep trench isolation region;

(2c) go out at shallow trench isolation areas dry etching the deep trouth that the degree of depth is 3 μm;

(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by collector contact district.

(3b) photoetching collector contact district window;

(3d) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation.

Step 4, prepared by base contact.

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm.

Step 6, prepared by emitter region.

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, HBT device is formed.

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area epitaxial material.

(8h) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 200nm is fixed as 25%, and as PMOS device source region, doping content is 5 × 10 ¹⁹cm ^-3, form PMOS device active area.

Step 9, prepared by nmos device active area materials.

(9f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow the P type strained si layer/that a layer thickness is 10nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁶cm ^-3, form nmos device active area.

Step 10, PMOS device isolation and the preparation of leakage groove.

(10e) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, PMOS device is formed.

(11e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grid and source electrode, finally form PMOS device.

Step 12, nmos device is formed.

(12d) photoetching gate medium and grid Poly-SiGe, forms grid;

(12g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 1 × 10 ²⁰cm ^-3, finally form nmos device.

Step 13, forms BiCMOS integrated circuit.

(13b) lithography fair lead;

(13c) at substrate surface sputtering layer of metal nickel (Ni), alloy;

Embodiment 2: preparation channel length is the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of 30nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 300nm, and upper layer of material is doping content is 5 × 10 ¹⁶cm ^-3n-type Si, thickness is 120nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 80nm, as collector region, this layer of doping content is 5 × 10 ¹⁶cm ^-3.

Step 2, prepared by deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm in epitaxial si layer superficial growth a layer thickness ₂layer;

(2b) photoetching deep trench isolation region;

(2c) go out at deep trench isolation region dry etching the deep trouth that the degree of depth is 4 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂, and fill up in deep trouth;

Step 3, prepared by collector contact district.

(3a) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, answer deposit a layer thickness to be the SiO of 600nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector contact area;

(3d) by substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 700 DEG C, is the SiO of 30nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 300nm, and doping content is 5 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 700 DEG C, at substrate surface deposit SiO ₂layer, thickness is 300nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in substrate surface deposit one SiN layer, thickness is 80nm;

(4f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit layer of sin layer, thickness is 15nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in base regioselectivity growth SiGe base, Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3, thickness is 40nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 700 DEG C, at substrate surface deposit Poly-Si, thickness is 300nm;

(6c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 5 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, HBT device is formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer, anneal 60s at 1000 DEG C of temperature, activator impurity, forms HBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area epitaxial material.

(8a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 2.7 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 300nm, doping content 3 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.8 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 20%, and doping content is 3 × 10 ¹⁸cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one deck Ge component is 20% on the sige layer, and thickness is the P type SiGe layer of 300nm, and doping content is 8 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(8e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 4nm, and doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(8f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 30nm, and as PMOS device channel region, doping content is 1 × 10 ¹⁷cm ^-3;

(8g) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 4nm, and doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(8h) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 300nm is fixed as 20%, and as PMOS device source region, doping content is 8 × 10 ¹⁹cm ^-3, form PMOS device active area.

Step 9, prepared by nmos device active area materials.

(9a) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(9b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 2.4 μm, oxide layer is carved thoroughly;

(9c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the P type Si resilient coating of 300nm in nmos device active area selective growth a layer thickness, doping content 3 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.8 μm, Ge component gradient distribution, and bottom is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(9e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one deck Ge component is 20% on the sige layer, and thickness is the P type SiGe layer of 300nm, and doping content is 1 × 10 ¹⁷cm ^-3;

(9f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, grow the P type strained si layer/that a layer thickness is 12nm on the sige layer, nmos device channel region, doping content is 1 × 10 ¹⁷cm ^-3, form nmos device active area.

Step 10, PMOS device isolation and the preparation of leakage groove.

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(10b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.4 μm;

(10c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(10d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.5 μm of leakage groove;

(10e) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, PMOS device is formed.

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(11b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.5 μm of gate groove;

(11c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 350 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 8nm;

(11d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in gate groove, deposit doping content is 3 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 20%, is filled up by PMOS device gate groove;

Step 12, nmos device is formed.

(12a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(12b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of 8nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(12c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 20%, and thickness is 240nm, and doping content is 3 × 10 ²⁰cm ^-3;

(12d) photoetching gate medium and grid Poly-SiGe, forms grid;

(12e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 3 × 10 ¹⁸cm ^-3;

(12f) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 4nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂form grid side wall;

(12g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 3 × 10 ²⁰cm ^-3, finally form nmos device.

Step 13, forms BiCMOS integrated circuit.

(13a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(13b) lithography fair lead;

(13c) at substrate surface sputtering layer of metal nickel (Ni), alloy;

(13d) photoetching lead-in wire, form PMOS device drain metal lead-in wire, source metal lead-in wire, gate metal goes between, nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming base thickness is 40nm, the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of collector region thickness to be 200nm, MOS conducting channel be 30nm.

Embodiment 3: preparation channel length is the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of 45nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 400nm, and upper layer of material is doping content is 1 × 10 ¹⁷cm ^-3n-type Si, thickness is 150nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 100nm, as collector region, this layer of doping content is 1 × 10 ¹⁷cm ^-3.

Step 2, prepared by deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm in epitaxial si layer superficial growth a layer thickness ₂layer;

(2b) photoetching deep trench isolation region;

(2c) go out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm;

(2d) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂, and fill up in deep trouth;

Step 3, prepared by collector contact district.

(3a) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, answer deposit a layer thickness to be the SiO of 700nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector contact area;

(3d) by substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 DEG C, is the SiO of 40nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 400nm, and doping content is 1 × 10 ²¹cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in substrate surface deposit one SiN layer, thickness is 100nm;

(4f) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 20nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3, thickness is 60nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 800 DEG C, at substrate surface deposit Poly-Si, thickness is 400nm;

(6b) phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

(6c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, HBT device is formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer, anneal 15s at 1100 DEG C of temperature, activator impurity, forms HBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area epitaxial material.

(8a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 3.2 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 400nm, doping content 5 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 2 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, selective growth one deck Ge component is 15% on the sige layer, and thickness is the P type SiGe layer of 400nm, and doping content is 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device;

(8e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 5nm, and doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(8f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 45nm, and as PMOS device channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(8g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 5nm, and doping content is 5 × 1018cm-3, as P type lightly-doped source drain structure (P-LDD);

(8h) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 400nm is fixed as 15%, and as PMOS device source region, doping content is 1 × 10 ²⁰cm ^-3, form PMOS device active area.

Step 9, prepared by nmos device active area materials.

(9a) method of chemical vapor deposition (CVD) is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(9b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 2.8 μm, oxide layer is carved thoroughly;

(9c) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the P type Si resilient coating of 400nm in nmos device active area selective growth a layer thickness, doping content 5 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 2 μm, Ge component gradient distribution, and bottom is 0%, and top is 15%, and doping content is 5 × 10 ¹⁵cm ^-3;

(9e) utilize the method for (CVD), at 750 DEG C, selective growth one deck Ge component is 15% on the sige layer, and thickness is the P type SiGe layer of 400nm, and doping content is 5 × 10 ¹⁷cm ^-3;

(9f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, grow the P type strained si layer/that a layer thickness is 15nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁷cm ^-3, form nmos device active area.

Step 10, PMOS device isolation and the preparation of leakage groove.

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(10b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.5 μm;

(10c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(10d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.6 μm of leakage groove;

(10e) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, PMOS device is formed.

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(11b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.7 μm of gate groove;

(11c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 400 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 10nm;

(11d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in gate groove, deposit doping content is 5 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove;

Step 12, nmos device is formed.

(12a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(12b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of 10nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(12c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 10%, and thickness is 300nm, and doping content is 5 × 10 ²⁰cm ^-3;

(12d) photoetching gate medium and grid Poly-SiGe, forms grid;

(12e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 5 × 10 ¹⁸cm ^-3;

(12f) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 5nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂form grid side wall;

(12g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 5 × 10 ²⁰cm ^-3, finally form nmos device.

Step 13, forms BiCMOS integrated circuit.

(13a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(13b) lithography fair lead;

(13c) at substrate surface sputtering layer of metal nickel (Ni), alloy;

(13d) photoetching lead-in wire, form PMOS device drain metal lead-in wire, source metal lead-in wire, gate metal goes between, nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, and bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, forming base thickness is 60nm, the strain Si BiCMOS integrated device based on SOI SiGe HBT and the circuit of collector region thickness to be 250nm, MOS conducting channel be 45nm.

The strain Si BiCMOS integrated device based on SOI SiGe HBT that the embodiment of the present invention provides and preparation method's tool have the following advantages:

10. the strain Si BiCMOS integrated device based on SOI SiGe HBT prepared of the present invention, middle SOI SiGe HBT emitter, base stage and collector electrode all adopt polycrystalline, polycrystalline can partly be produced on above oxide layer, reduce the area of device active region, thus reduction device size, improve the integrated level of circuit.The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1., based on a preparation method for the strain Si BiCMOS integrated device of SOI SiGe HBT, it is characterized in that, this preparation method comprises the steps:

3rd step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in epitaxial si layer superficial growth a layer thickness ₂layer, photoetching deep trench isolation, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 3 ~ 5 μm, and recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in deep trouth ₂; Finally, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

19 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching lead-in wire window, sputter layer of metal nickel (Ni) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact; Photoetching goes between, form the drain electrode of MOS device, source electrode and gate metal lead-in wire, and the emitter of SiGe HBT, base stage and collector electrode metal lead-in wire, forming base thickness is 20 ~ 60nm, the strain Si BiCMOS integrated device based on SOI SiGe HBT of collector region thickness to be 150 ~ 250nm, MOS conducting channel be 22 ~ 45nm.

2. preparation method according to claim 1, is characterized in that, PMOS device channel length is determined according to the N-type strained si layer/thickness of the 12 step deposit, and get 22 ~ 45nm, the channel length of nmos device is determined by technique, gets 22 ~ 45nm.

3. preparation method according to claim 1, it is characterized in that, determine to chemical vapor deposition (CVD) technological temperature in the 19 step according to the 12 step based on maximum temperature involved in the strain Si BiCMOS integrated device of SOI SiGe HBT and circuit fabrication process in this preparation method, maximum temperature is less than or equal to 800 DEG C.

4. preparation method according to claim 1, is characterized in that, collector region thickness decides according to the thickness of the Si epitaxial loayer that first step SOI upper strata Si thickness and second step grow, and gets 150 ~ 250nm.

5. preparation method according to claim 1, is characterized in that, base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20 ~ 60nm.

6., based on a preparation method for the strain Si BiCMOS integrated circuit of SOI SiGe HBT, it is characterized in that, this preparation method comprises the steps:

Step 1, epitaxially grown implementation method is as follows:

Step 2, implementation method prepared by deep trench isolation is as follows:

(2b) photoetching deep trench isolation region;

(3b) photoetching collector contact district window;

Step 4, implementation method prepared by base contact is as follows:

Step 5, implementation method prepared by base material is as follows:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

Step 6, implementation method prepared by emitter region is as follows:

Step 7, the implementation method that HBT device is formed is as follows:

Step 8, prepared by PMOS device active area epitaxial material;

Step 11, the implementation method that PMOS device is formed is as follows:

Step 12, the implementation method that nmos device is formed is as follows:

(12d) photoetching gate medium and grid Poly-SiGe, forms grid;

(13b) lithography fair lead;

(13c) at substrate surface sputtering layer of metal nickel (Ni) alloy;