CN102738151B

CN102738151B - SiGe HBT (Heterojunction Bipolar Transistor) device strain Si BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof

Info

Publication number: CN102738151B
Application number: CN201210243599.2A
Authority: CN
Inventors: 胡辉勇; 宋建军; 张鹤鸣; 舒斌; 李妤晨; 吕懿; 宣荣喜; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2015-07-22
Anticipated expiration: 2032-07-16
Also published as: CN102738151A

Abstract

The invention discloses a SiGe HBT (Heterojunction Bipolar Transistor) device strain Si BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a manufacturing method of the SiGe HBT device strain Si BiCMOS integrated device. The method comprises the following steps of: growing N-Si on an Si substrate as a bipolar device collector region; etching a base region; growing P-SiGe, i-Si, i-Poly-Si in the base region; manufacturing deep trench isolation; manufacturing an emitter, a base and a collector; forming a SiGe HBT device; etching an active area trench of an NMOS (N-Channel Metal Oxide Semiconductor) device and a PMOS (P-Channel Metal Oxide Semiconductor) device respectively; growing an active layer at the NMOS and PMOS devices at the active area trench of the NMOS and PMOS devices respectively; manufacturing the source and drain and the grid of the NMOS and PMOS devices respectively so as to form the NMOS and PMOS devices; and alloying and etching a lead so as to form the SiGe HBT device, the strain Si BiCMOS integrated device and a circuit. The characteristic of anisotropic tension strain Si material mobility rate is utilized sufficiently; and the SiGe HBT device, and the strain Si BiCMOS integrated circuit with enhanced performance are manufactured at 600-800 DEG C.

Description

A kind of SiGe HBT device strain Si BiCMOS integrated device and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of SiGe HBT device strain Si BiCMOS integrated device and preparation method.

Background technology

Integrated circuit is foundation stone and the core of information-intensive society economic development.Mention when choosing Section 5 electronic technology in the most great project technological contribution in 20, the world of 20th century recently as American Engineering technos, " from vacuum tube to semiconductor, integrated circuit, become the foundation stone of contemporary every profession and trade intelligent work." integrated circuit time one of the typical products best embodying Characteristics of Knowledge Economy.At present, the electronics and information industry based on integrated circuit has become the large industry of the first in the world.Along with the development of integrated circuit technique, the clear and definite boundary between complete machine and element is broken, and integrated circuit not only becomes the basis of modern industry and science and technology, and is just creating the silicon culture of information age.

Due to the good characteristic of Si material, particularly exceedingly useful dielectric film can be easily formed---SiO ₂film and Si ₃n ₄film, thus Si material can be utilized to realize the most cheap integrated circuit technology, be developed so far, whole world number, with the equipment of trillion dollars and Technical investment, has made Si base technique define very powerful industry ability.Meanwhile, long-term science research input also makes people to the understanding of Si and technique thereof, reaches very deep, thorough stage, therefore in IC industry, Si technology is mainstream technology, and Si integrated circuit (IC) products is main product, accounts for more than 90% of IC industry.In Si integrated circuit using bipolar transistor as the analog integrated circuit of basic structural unit in electronic system in occupation of consequence, along with the development of Si technology, the performance of Si bipolar transistor also obtain and significantly improves.

But to the nineties in last century, Si bipolar transistor is due to the restriction of the reasons such as voltage, base width, power density, the method of the scaled down that can not generally adopt by industrial quarters again, to improve the performance of device and integrated circuit, seriously constrains the further raising of analog integrated circuit and the electronic system performance based on it.

In order to improve the performance of device and integrated circuit further, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Summary of the invention

The object of the present invention is to provide a kind of SiGe HBT device, strain Si BiCMOS integrated device and circuit preparation method, to realize utilizing the anisotropic feature of tensile strain Si material mobility, at 600 ~ 800 DEG C, prepare the SiGe HBT device of performance enhancement, strain Si BiCMOS integrated device.

The object of the present invention is to provide a kind of SiGe HBT device strain Si BiCMOS integrated device, described strain Si BiCMOS device adopts two polycrystal SiGe HBT device, strain Si planar channeling nmos device and strain Si vertical-channel PMOS device.

Further, described nmos device conducting channel is strain Si material, is tensile strain along channel direction.

Further, described PMOS device strained Si channel is vertical-channel, is compressive strain along channel direction, and is hollow structure.

Further, the base of SiGeHBT device is strain SiGe material.

Further, the emitter of SiGeHBT device and base stage adopt polysilicon contact.

Another object of the present invention is to the preparation method providing a kind of SiGe HBT device strain Si BiCMOS integrated device, described preparation method comprises the steps:

The first step, to choose doping content be 5 × 10 ¹⁴~ 5 × 10 ¹⁵cm ^-3p type Si sheet as substrate;

Second step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm at epitaxial si layer surface deposition one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, form N-type heavy doping buried region;

3rd step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the N-type Si epitaxial loayer of 1.5 ~ 2 μm in Grown a layer thickness, as collector region, this layer of doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

4th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm, and at substrate surface growth trilaminate material: ground floor is SiGe layer, and Ge component is 15 ~ 25%, thickness is the doping of 20 ~ 60nm, P type, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, as base; The second layer is unadulterated intrinsic layer si layer, and thickness is 10 ~ 20nm; Third layer is unadulterated intrinsic Poly-Si layer, and thickness is 200 ~ 300nm, as base stage and emitter region;

5th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in deep trouth, fills SiO ₂;

6th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180 ~ 300nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

7th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215 ~ 325nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

8th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area;

9th step, photoetching emitting area, carry out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3, form emitter region;

Tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area; And to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT device;

11 step, photoetching PMOS device active area, by dry etch process, in PMOS device active area, etch the deep trouth that the degree of depth is 2 ~ 3 μm, carve the oxide layer in substrate; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, at PMOS device active area (i.e. deep trouth) selective epitaxial growth seven layer material: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.7 ~ 2.0 μm,

Bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device; The P type strained si layer/of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD); The N-type strained si layer/of layer 5 to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^- ³, as P type lightly-doped source drain structure (P-LDD); Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the active area of PMOS device;

12 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂; Photoetching nmos device active area, in nmos device active area, etches the deep trouth that the degree of depth is 1.9 ~ 2.8 μm; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, at nmos device active area selective epitaxial growth four layer material: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.8 ~ 2.3 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of the 4th layer of to be thickness be 10 ~ 15nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

13 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching PMOS device source and drain isolated area, utilizes dry etch process, goes out at this region etch the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂, form shallow-trench isolation;

14 step, photoetching leak trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.4 ~ 0.7 μm of leakage groove; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

15 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 ~ 0.7 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as the gate dielectric layer of PMOS device; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in gate groove, deposit doping content is 1 ~ 5 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove; Photoetching gate medium and grid Poly-SiGe, form grid and source electrode, final formation PMOS device structure;

16 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at nmos device active area deposition thickness ₂layer, as the gate dielectric layer of nmos device; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, be the P type Poly-SiGe of 200 ~ 300nm at nmos device active area deposition thickness, doping content is 1 ~ 5 × 10 ²⁰cm ^-3, Ge component is 10 ~ 30%, photoetching gate medium and grid Poly-SiGe, forms grid; Utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 1 ~ 5 × 10 ¹⁸cm ^-3;

17 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, utilizes dry etch process, etches away the SiO on surface ₂, form nmos device grid curb wall, utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content in nmos device source region and drain region reach 1 ~ 5 × 10 ²⁰cm ^-3;

18 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching lead-in wire window, sputter layer of metal nickel (Ni) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact; Depositing metal, photoetching goes between, and forms SiGe HBT device, strain Si BiCMOS integrated device that MOS conducting channel is 22 ~ 45nm.

Further, described PMOS device channel length is determined according to the N-type strained si layer/thickness of the 11 step deposit, and get 22 ~ 45nm, the channel length of nmos device is determined by technique, gets 22 ~ 45nm.

Further, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20 ~ 60nm.

Further, chemical vapor deposition (CVD) technological temperature involved in strain Si cmos device manufacture process in described preparation method, maximum temperature is less than or equal to 800 DEG C.

Another object of the present invention is to the preparation method providing a kind of SiGe HBT device strain Si BiCMOS integrated circuit, described preparation method comprises the steps:

Step 1, implementation method prepared by epitaxial material is:

(1a) choosing doping content is 5 × 10 ¹⁴cm ^-3p type Si sheet, as substrate;

(1b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm at epitaxial si layer surface deposition one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, form N-type heavy doping buried region;

(1c) etch away the oxide layer of substrate surface, utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 1.5 μm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

(1d) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(1e) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(1f) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1g) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, this layer of Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1h) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 10nm;

(1i) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm;

Step 2, implementation method prepared by device deep trench isolation is:

(2a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation;

Step 3, implementation method prepared by collector electrode shallow-trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation;

Step 4, implementation method prepared by base stage shallow-trench isolation is:

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation, formed SiGeHBT;

Step 6, implementation method prepared by PMOS device active area epitaxial material is:

(6a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 2 μm;

(6b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 200nm, doping content 1 × 10 ¹⁵cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.7 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 25%, and doping content is 1 × 10 ¹⁸cm ^-3;

(6d) by the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one deck Ge component is 25% on the sige layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(6e) by the method for chemical vapor deposition (CVD), at 600 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 3nm, and doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 22nm, and as PMOS device channel region, doping content is 5 × 10 ¹⁶cm ^-3;

(6g) by the method for chemical vapor deposition (CVD), at 600 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 3nm, and doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6h) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 200nm is fixed as 25%, and as PMOS device source region, doping content is 5 × 10 ¹⁹cm ^-3, form PMOS device active area;

Step 7, implementation method prepared by nmos device active area materials is:

(7a) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 1.9 μm;

(7c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the P type Si resilient coating of 200nm in nmos device active area selective growth a layer thickness, doping content 1 × 10 ¹⁵cm ^- ³;

(7d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.8 μm, Ge component gradient distribution, and bottom is 0%, and top is 25%, and doping content is 1 × 10 ¹⁵cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one deck Ge component is 25% on the sige layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 × 10 ¹⁶cm ^-3;

(7f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow the P type strained si layer/that a layer thickness is 10nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁶cm ^-3, form nmos device active area;

Step 8, implementation method prepared by PMOS device isolation and leakage groove is:

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.3 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.4 μm of leakage groove;

(8e) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 9, the implementation method that PMOS device is formed is:

(9a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(9b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 μm of gate groove;

(9c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 300 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 6nm;

(9d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in gate groove, deposit doping content is 1 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 30%, is filled up by PMOS device gate groove;

(9e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grid and source electrode, finally form PMOS device;

Step 10, the implementation method that nmos device is formed is:

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(10b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of 6nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(10c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 30%, and thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^- ³;

(10d) photoetching gate medium and grid Poly-SiGe, forms grid;

(10e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(10f) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 3nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂form grid side wall;

(10g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 1 × 10 ²⁰cm ^-3, finally form nmos device;

Step 11, the implementation method forming BiCMOS integrated circuit is:

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(11b) lithography fair lead;

(11c) at substrate surface sputtering layer of metal nickel (Ni) alloy;

(11d) Metal Contact is formed; Depositing metal, photoetching goes between, and forms SiGe HBT, strain Si BiCMOS integrated device and circuit that MOS conducting channel is 22nm.

Tool of the present invention has the following advantages:

1. in the BiCMOS device architecture that the present invention manufactures, CMOS part have employed strain Si material and manufactures conducting channel, because strain Si material carrier mobility is far above body Si material, therefore by the circuit performance excellence that simulation and the hybrid digital-analog integrated circuit performance of the manufacture of this BiCMOS device architecture comparatively use body Si to manufacture;

2. the present invention manufacture BiCMOS device architecture in CMOS structure, take full advantage of the anisotropy of strain Si material stress, introduce tensile strain in the horizontal direction, improve nmos device electron mobility; Introduce compressive strain in the vertical direction, improve PMOS device hole mobility.Therefore, this performance such as device frequency and current driving ability is higher than the relaxation Si cmos device of same size;

3. in preparation process of the present invention, strained si layer/chemical vapor deposition (CVD) method deposit, accurately can control growth thickness, and the channel length of PMOS device in CMOS is the thickness of Si layer, thus avoid small size photoetching, decrease process complexity, reduce cost;

4. in the BiCMOS device architecture prepared of the present invention, the raceway groove of PMOS device is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

5. the CMOS structure in the BiCMOS device prepared of the present invention, MOS device have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of MOS device, enhance the electric property of cmos device;

6. the CMOS structure in the BiCMOS device prepared of the present invention, adopt Poly-SiGe material as gate electrode, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe, realizing CMOS threshold voltage can continuous setup, decreases processing step, reduces technology difficulty;

7. the present invention prepares strain Si vertical-channel cmos device is after bipolar device manufacture completes, and the maximum temperature related in its technical process is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

8. the present invention prepares the maximum temperature related in SiGe HBT device, strain Si BiCMOS integrated device process is 800 DEG C, lower than the technological temperature causing strain Si relaxation, therefore this preparation method can keep the characteristic of strain Si effectively, improves the performance of device and integrated circuit.

Accompanying drawing explanation

Fig. 1 is the realization flow figure of SiGe HBT device provided by the invention, strain Si BiCMOS integrated device and circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of SiGe HBT device, strain Si BiCMOS integrated device, described strain Si BiCMOS device adopts two polycrystal SiGe HBT device, strain Si planar channeling nmos device and strain Si vertical-channel PMOS device.

As a prioritization scheme of the embodiment of the present invention, described nmos device conducting channel is strain Si material, is tensile strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, described PMOS device strained Si channel is vertical-channel, is compressive strain along channel direction, and is hollow structure.

As a prioritization scheme of the embodiment of the present invention, the base of SiGe HBT device is strain SiGe material.

As a prioritization scheme of the embodiment of the present invention, the emitter of SiGe HBT device and base stage adopt polysilicon contact.

Referring to accompanying drawing 1, the technological process being prepared by the present invention to SiGe HBT device, strain Si BiCMOS integrated device and circuit is described in further detail.

Embodiment 1: prepare SiGe HBT device, strain Si BiCMOS integrated device and circuit that channel length is 22nm, concrete steps are as follows:

Step 1, prepared by epitaxial material.

(1i) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm.

Step 2, prepared by device deep trench isolation.

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by PMOS device active area epitaxial material.

(6h) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 200nm is fixed as 25%, and as PMOS device source region, doping content is 5 × 10 ¹⁹cm ^-3, form PMOS device active area.

Step 7, prepared by nmos device active area materials.

(7f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow the P type strained si layer/that a layer thickness is 10nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁶cm ^-3, form nmos device active area.

Step 8, PMOS device isolation and the preparation of leakage groove.

(8e) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 9, PMOS device is formed.

(9e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grid and source electrode, finally form PMOS device.

Step 10, nmos device is formed.

(10d) photoetching gate medium and grid Poly-SiGe, forms grid;

(10g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 1 × 10 ²⁰cm ^-3, finally form nmos device.

Step 11, forms BiCMOS integrated circuit.

(11b) lithography fair lead;

(11c) at substrate surface sputtering layer of metal nickel (Ni) alloy;

Embodiment 2: prepare SiGe HBT device, strain Si BiCMOS integrated device and circuit that channel length is 30nm, concrete steps are as follows:

Step 1, prepared by epitaxial material.

(1a) choosing doping content is 1 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm at epitaxial si layer surface deposition one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, form N-type heavy doping buried region;

(1c) etch away the oxide layer of substrate surface, utilize the method for chemical vapor deposition (CVD), at 700 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 1.8 μm, as collector region, this layer of doping content is 5 × 10 ¹⁶cm ^-3;

(1d) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(1e) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(1g) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiGe layer of 40nm in Grown a layer thickness, and as base, this layer of Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3;

(1h) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 15nm;

(1i) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 240nm.

Step 2, prepared by device deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(2d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 240nm;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 260nm;

(4e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 5 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 3 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by PMOS device active area epitaxial material.

(6a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 2.4 μm;

(6b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 300nm, doping content 3 × 10 ¹⁵cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 1.8 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 20%, and doping content is 3 × 10 ¹⁸cm ^-3;

(6d) by the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one deck Ge component is 20% on the sige layer, and thickness is the P type SiGe layer of 300nm, and doping content is 8 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(6e) by the method for chemical vapor deposition (CVD), at 700 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 4nm, and doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 30nm, and as PMOS device channel region, doping content is 1 × 10 ¹⁷cm ^-3;

(6g) by the method for chemical vapor deposition (CVD), at 700 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 4nm, and doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6h) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 300nm is fixed as 20%, and as PMOS device source region, doping content is 8 × 10 ¹⁹cm ^-3, form PMOS device active area.

Step 7, prepared by nmos device active area materials.

(7a) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 2.4 μm;

(7c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the P type Si resilient coating of 300nm in nmos device active area selective growth a layer thickness, doping content 3 × 10 ¹⁵cm ^- ³;

(7d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 2.1 μm, Ge component gradient distribution, and bottom is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one deck Ge component is 20% on the sige layer, and thickness is the P type SiGe layer of 300nm, and doping content is 1 × 10 ¹⁷cm ^-3;

(7f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, grow the P type strained si layer/that a layer thickness is 12nm on the sige layer, nmos device channel region, doping content is 1 × 10 ¹⁷cm ^-3, form nmos device active area.

Step 8, PMOS device isolation and the preparation of leakage groove.

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.4 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.5 μm of leakage groove;

(8e) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 9, PMOS device is formed.

(9a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(9b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.5 μm of gate groove;

(9c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 350 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 8nm;

(9d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in gate groove, deposit doping content is 3 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 20%, is filled up by PMOS device gate groove;

Step 10, nmos device is formed.

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(10b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of 8nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(10c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 20%, and thickness is 240nm, and doping content is 3 × 10 ²⁰cm ^- ³;

(10d) photoetching gate medium and grid Poly-SiGe, forms grid;

(10e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 3 × 10 ¹⁸cm ^-3;

(10f) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 4nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂, form grid side wall;

(10g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 3 × 10 ²⁰cm ^-3, finally form nmos device.

Step 11, forms BiCMOS integrated circuit.

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(11b) lithography fair lead;

(11c) at substrate surface sputtering layer of metal nickel (Ni) alloy;

(11d) Metal Contact is formed; Depositing metal, photoetching goes between, and forms SiGe HBT device, strain Si BiCMOS integrated device and circuit that MOS conducting channel is 30nm.

Embodiment 3: prepare SiGe HBT device, strain Si BiCMOS integrated device and circuit that channel length is 45nm, concrete steps are as follows:

Step 1, prepared by epitaxial material.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm at epitaxial si layer surface deposition one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, form N-type heavy doping buried region;

(1c) etch away the oxide layer of substrate surface, utilize the method for chemical vapor deposition (CVD), at 750 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2.5 μm, as collector region, this layer of doping content is 1 × 10 ¹⁷cm ^-3;

(1d) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(1e) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(1g) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the SiGe layer of 60nm in Grown a layer thickness, and as base, this layer of Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3;

(1h) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 20nm;

(1i) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 300nm.

Step 2, prepared by device deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(2d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 300nm;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 325nm;

(4e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes base contact zone doping content be 1 × 10 ²⁰cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, and making emitter connect district's doping content is 5 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector electrode;

(5f) to substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by PMOS device active area epitaxial material.

(6a) photoetching PMOS device active area, with dry etching method, in PMOS device active area, etches the deep trouth that the degree of depth is 2.9 μm;

(6b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, selective growth a layer thickness is the P type Si resilient coating of 400nm, doping content 5 × 10 ¹⁵cm ^-3;

(6c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 2.0 μm, is 0% bottom Ge component, and upper strata is the gradient distribution of 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(6d) by the method for chemical vapor deposition (CVD), at 750 DEG C, selective growth one deck Ge component is 15% on the sige layer, and thickness is the P type SiGe layer of 400nm, and doping content is 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device;

(6e) by the method for chemical vapor deposition (CVD), at 750 DEG C, in P type SiGe layer, selective growth a layer thickness is the P type strained si layer/of 5nm, and doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in P type strained si layer/, selective growth a layer thickness is the N-type strained si layer/of 45nm, and as PMOS device channel region, doping content is 5 × 10 ¹⁷cm ^-3;

(6g) by the method for chemical vapor deposition (CVD), at 750 DEG C, in N-type strained si layer/, selective growth a layer thickness is the P type strained si layer/of 5nm, and doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD);

(6h) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in strained si layer/, selective growth a layer thickness is the P type strained sige layer that the Ge component of 400nm is fixed as 15%, and as PMOS device source region, doping content is 1 × 10 ²⁰cm ^-3, form PMOS device active area.

Step 7, prepared by nmos device active area materials.

(7a) method of chemical vapor deposition (CVD) is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂;

(7b) photoetching nmos device active area, with dry etching method, in nmos device active area, etches the deep trouth that the degree of depth is 2.8 μm;

(7c) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the P type Si resilient coating of 400nm in nmos device active area selective growth a layer thickness, doping content 5 × 10 ¹⁵cm ^- ³;

(7d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, on Si resilient coating, selective growth a layer thickness is the P type SiGe layer of 2.3 μm, Ge component gradient distribution, and bottom is 0%, and top is 15%, and doping content is 5 × 10 ¹⁵cm ^-3;

(7e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, selective growth one deck Ge component is 15% on the sige layer, and thickness is the P type SiGe layer of 400nm, and doping content is 5 × 10 ¹⁷cm ^-3;

(7f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, grow the P type strained si layer/that a layer thickness is 15nm on the sige layer, nmos device channel region, doping content is 5 × 10 ¹⁷cm ^-3, form nmos device active area.

Step 8, PMOS device isolation and the preparation of leakage groove.

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.5 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is 0.6 μm of leakage groove;

(8e) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 9, PMOS device is formed.

(9a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(9b) photoetching gate groove window, utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.7 μm of gate groove;

(9c) atomic layer chemical vapor deposit (ALCVD) method is utilized, at 400 DEG C, at the HfO of substrate surface depositing high dielectric constant ₂layer, as the gate dielectric layer of PMOS device, thickness is 10nm;

(9d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in gate groove, deposit doping content is 5 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove;

Step 10, nmos device is formed.

(10a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(10b) photoetching nmos device active area, utilizes atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of 10nm in nmos device surfaces of active regions deposit a layer thickness ₂layer, as the gate medium of nmos device;

(10c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 10%, and thickness is 300nm, and doping content is 5 × 10 ²⁰cm ^- ³;

(10d) photoetching gate medium and grid Poly-SiGe, forms grid;

(10e) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, form N-type lightly-doped source drain structure (N-LDD), doping content is 5 × 10 ¹⁸cm ^-3;

(10f) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at the SiO of nmos device surfaces of active regions deposit one deck 5nm ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains SiO at Ploy-SiGe sidewall ₂form grid side wall;

(10g) utilize ion implantation technology, carry out N-type ion implantation to nmos device active area, autoregistration generates source region and the drain region of nmos device, and rapid thermal annealing, make the doping content of nmos device active area reach 5 × 10 ²⁰cm ^-3, finally form nmos device.

Step 11, forms BiCMOS integrated circuit.

(11a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer;

(11b) lithography fair lead;

(11c) at substrate surface sputtering layer of metal nickel (Ni) alloy;

(11d) Metal Contact is formed; Depositing metal, photoetching goes between, and forms SiGe HBT device, strain Si BiCMOS integrated device and circuit that MOS conducting channel is 45nm.

SiGe HBT device, strain Si BiCMOS integrated device and preparation method's tool that the embodiment of the present invention provides have the following advantages:

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1. a preparation method for SiGe HBT device strain Si BiCMOS integrated device, it is characterized in that, described preparation method comprises the steps:

3rd step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, be the N-type Si epitaxial loayer of 1.5 ~ 2 μm in Grown a layer thickness, as collector region, N-type Si outer layer doping concentration is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

8th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching base region, carries out p type impurity injection to photoetching base region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area;

9th step, photoetching emitting area, carry out N-type impurity injection to photoetching emitting area, makes doping content be 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3, form emitter region;

Tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to removal collector region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area; And to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT device;

11 step, photoetching PMOS device active area, by dry etch process, in PMOS device active area, etch the deep trouth that the degree of depth is 2 ~ 3 μm, carve the oxide layer in substrate; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, at PMOS device active area (i.e. deep trouth) selective epitaxial growth seven layer material: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.7 ~ 2.0 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device; The P type strained si layer/of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD); The N-type strained si layer/of layer 5 to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD); Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as the active area of PMOS device;

13 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in photoetching PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂, form shallow-trench isolation;

2. preparation method according to claim 1, is characterized in that, described PMOS device channel length is determined according to the N-type strained si layer/thickness of the 11 step deposit, and get 22 ~ 45nm, the channel length of nmos device is determined by technique, gets 22 ~ 45nm.

3. preparation method according to claim 1, is characterized in that, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20 ~ 60nm.

4. preparation method according to claim 1, is characterized in that, chemical vapor deposition (CVD) technological temperature involved in strain Si cmos device manufacture process in described preparation method, maximum temperature is less than or equal to 800 DEG C.

5. a preparation method for SiGe HBT device strain Si BiCMOS integrated circuit, it is characterized in that, described preparation method comprises the steps:

Step 1, implementation method prepared by epitaxial material is:

(1c) oxide layer of substrate surface is etched away, utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 1.5 μm, as collector region, N-type epitaxial si layer doping content is 1 × 10 ¹⁶cm ^-3;

(1g) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, SiGe layer Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

Step 2, implementation method prepared by device deep trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5d) photoetching emitter region, carries out N-type impurity injection to photoetching emitter region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to removal collector region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carries out impurity activation, forms SiGe HBT;

Step 7, implementation method prepared by nmos device active area materials is:

(7c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the P type Si resilient coating of 200nm in nmos device active area selective growth a layer thickness, doping content 1 × 10 ¹⁵cm ^-3;

Step 9, the implementation method that PMOS device is formed is:

Step 10, the implementation method that nmos device is formed is:

(10c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one deck Ploy-SiGe layer on gate dielectric layer, Ge component is 30%, and thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^-3;

(10d) photoetching gate medium and grid Poly-SiGe, forms grid;

Step 11, the implementation method forming BiCMOS integrated circuit is:

(11b) lithography fair lead;

(11c) at substrate surface sputtering layer of metal nickel (Ni) alloy;