CN102738161B

CN102738161B - The two strain mixing crystal face Si base BiCMOS integrated device of a kind of two polycrystalline and preparation method

Info

Publication number: CN102738161B
Application number: CN201210244314.7A
Authority: CN
Inventors: 张鹤鸣; 吕懿; 胡辉勇; 王海栋; 宋建军; 宣荣喜; 舒斌; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2015-12-16
Anticipated expiration: 2032-07-16
Also published as: CN102738161A

Abstract

The invention discloses the two strain mixing crystal face Si base BiCMOS integrated device of two polycrystalline and preparation method, first prepare SOI substrate, upper strata basis material is (110) crystal face, and underlying substrate material is (100) crystal face; N-Si is as bipolar device collector region in growth, and photoetching base, at base region growing P-SiGe/i-Si/i-Poly-Si, prepares emitter, base stage and collector electrode, form SiGe? HBT device; Preparation deep trench isolation; In PMOS device region, selective growth crystal face is the PMOS device active area of (110), preparation compressive strain Si vertical-channel PMOS device; Go out deep trouth at nmos device region etch, selective growth crystal face is the nmos device active area of (100), prepares strained Si channel nmos device; Make Si base BiCMOS integrated device and circuit.The present invention makes full use of tensile strain Si material electronics mobility higher than body Si material and compressive strain Si material hole mobility higher than body Si material and the anisotropic feature of mobility, has prepared two polycrystalline of performance enhancement, two strain mixing crystal face Si base BiCMOS integrated circuit.

Description

The two strain mixing crystal face Si base BiCMOS integrated device of a kind of two polycrystalline and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and preparation method.

Background technology

The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously.It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid.In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

Silicon materials experienced by more than 50 year as semi-conducting material application, traditional SiCMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law.At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.

But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology.Particularly when IC chip feature sizes enters nanoscale, from device angles, short channel effect in nanoscale devices, high-field effect, quantum effect, the impact of parasitic parameter, the problems such as technological parameter fluctuation are to device leakage current, subthreshold behavior, the impact of the performances such as ON state/off-state current is more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet novel, the demand of high-velocity electrons system.

In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that SiBiCMOS technology manufactures, especially frequency performance, is greatly limited; And for SiGeBiCMOS technology, although bipolar transistor have employed SiGeHBT, the unipolar device promoted for restriction BiCMOS integrated circuit frequency characteristic still adopts SiCMOS, promote further so these all limit BiCMOS performance of integrated circuits ground.

For this reason, will when not reducing a kind of mobility of charge carrier of types of devices, improve the mobility of the charge carrier of another kind of types of devices, this patent proposes one and utilizes strain gauge technique to prepare BiCMOS, i.e. the preparation of two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device.

Summary of the invention

The object of the present invention is to provide two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and preparation method, to realize utilizing tensile strain Si material electronics mobility higher than body Si material and compressive strain Si material hole mobility higher than body Si material and the anisotropic feature of mobility, prepare two polycrystalline of performance enhancement, two strain mixing crystal face Si base BiCMOS integrated device.

The object of the present invention is to provide a kind of two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device, nmos device and PMOS device are strain Si MOS device, and bipolar device is two polycrystal SiGe HBT devices.

Further, the conducting channel of nmos device is strain Si material, and the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

Further, the conducting channel of PMOS device is strain Si material, and the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel.

Further, nmos device be prepared in crystal face for (100) SOI substrate on, PMOS device be prepared in crystal face for (110) substrate on.

Further, the base of SiGeHBT device is strain SiGe material.

Further, the emitter of SiGeHBT device and base stage adopt polycrystalline silicon material.

Another object of the present invention is to the preparation method that a kind of pair of polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device are provided, comprise the steps:

The first step, choose two panels N-type doping Si sheet, wherein a slice crystal face is (110), and a slice crystal face is (100), and two panels doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm; Be the basis material of a slice as upper strata of (100) using crystal face, and in this basis material hydrogen injecting, be the basis material of a slice as lower floor of (110) using crystal face; Chemico-mechanical polishing (CMP) technique is adopted to carry out polishing to two oxide layer surfaces;

Second step, two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, at substrate surface growth Si epitaxial loayer, thickness is 2 ~ 3 μm, and N-type is adulterated, and doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3, as collector region;

4th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm, and at substrate surface growth trilaminate material: ground floor is SiGe layer, and Ge component is 15 ~ 25%, thickness is the doping of 20 ~ 60nm, P type, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, as base; The second layer is unadulterated intrinsic layer si layer, and thickness is 10 ~ 20nm; Third layer is unadulterated intrinsic Poly-Si layer, and thickness is 200 ~ 300nm, as base stage and emitter region;

5th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in deep trouth, fills SiO ₂;

6th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180 ~ 300nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

7th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215 ~ 325nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

8th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area;

9th step, photoetching emitting area, carry out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3, form emitter region;

Tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area.And to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGeHBT device;

11 step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

12 step, photoetching PMOS device active area, in PMOS device active area, utilize dry etching, etches the deep trouth that the degree of depth is 3.4 ~ 5.8 μm, the oxide layer of centre carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth seven layer material on the PMOS device active area of (110) crystal face substrate: ground floor is N-type Si resilient coating, and thickness is 1.5 ~ 2.5 μm, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be N-type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ²⁰cm ^-3, as the drain region of PMOS device; 4th layer is thickness is 3 ~ 5nmP type strained si layer/, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer; Layer 5 to be thickness the be N-type strain Si of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

13 step, photoetching nmos device active area, in nmos device active area, utilize dry etching, etch the deep trouth that the degree of depth is 1.9 ~ 2.8 μm, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3; The N-type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

14 step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600 ~ 800 DEG C, deposit one deck SiO ₂resilient coating and layer of sin, etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.3 ~ 0.7 μm of leakage groove; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, form PMOS device and leak trenched side-wall isolation; Dry etching is utilized to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-SiGe beyond flute surfaces, formed and leak bonding pad;

15 step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5 ~ 0.9 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

16 step, etch nmos device active area, utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100 ~ 300nm, Ge component is 10 ~ 30%, etching N MOS device grid; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Be the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, dry etching falls this layer of SiO ², as nmos device grid curb wall, form nmos device grid;

17 step, carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 ~ 5 × 10 ²⁰cm ^-3;

18 step, photoetching lead-in wire window, sputter layer of metal titanium (Ti) over the entire substrate, alloy, photoetching goes between, and forming conducting channel is two polycrystalline of 22 ~ 45nm, two strain mixing crystal face Si base BiCMOS integrated device.

Further, wherein, PMOS device channel length is determined according to the N-type strained si layer/layer thickness of the 11 step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

Further, maximum temperature involved in this preparation method determines to chemical vapor deposition (CVD) technological temperature in the 18 step according to the 4th step, and maximum temperature is less than or equal to 800 DEG C.

Further, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20 ~ 60nm.

Another object of the present invention is to the preparation method that a kind of pair of polycrystalline, two strain mixing crystal face Si base BiCMOS integrated circuit are provided, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as upper strata basis material, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as underlying substrate material;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, implementation method prepared by bipolar device active area is:

(2a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2 μm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

(2b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(2c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(2d) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(2e) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, this layer of Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(2f) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 10nm;

(2g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm;

Step 3, implementation method prepared by collector electrode shallow-trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation;

Step 4, implementation method prepared by base stage shallow-trench isolation is:

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation;

Step 5, the implementation method that SiGeHBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation, formed SiGeHBT;

Step 6, implementation method prepared by device deep trench isolation is:

(6a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(6b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(6c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5um;

(6d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation;

Step 7, implementation method prepared by PMOS device active area is:

(7a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 3.4 μm, oxide layer is carved thoroughly;

(7b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 1.5 μm along (110) crystal face, doping content is 1 × 10 ¹⁵cm ^-3;

(7c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(7e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(7f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 22nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of PMOS device;

(7g) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(7h) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

Step 8, implementation method prepared by nmos device active area is:

(8a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.9 μm;

(8b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 200nm, doping content is 1 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(8e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

Step 9, PMOS device is leaked the implementation method prepared bonding pad and is:

(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(9b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.3 μm of leakage groove;

(9c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(9d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 10, implementation method prepared by PMOS grid bonding pad is:

(10a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.5 μm of gate groove;

(10b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(10c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

Step 11, implementation method prepared by nmos device is:

(11a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(11b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(11c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(11d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(11e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(11f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device;

Step 12, implementation method prepared by formation BiCMOS integrated circuit is:

(12a) photoetching lead-in wire window;

(12b) sputter layer of metal titanium (Ti) over the entire substrate, alloy, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;

(12c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final formation CMOS conducting channel is two polycrystalline of 22nm, two strain mixing crystal face Si base BiCMOS integrated device and circuit.

tool of the present invention has the following advantages:

1. two polycrystalline, the two strain mixing crystal face Si base BiCMOS integrated device that prepared by the present invention have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, (110) crystal face is compressive strain for strain Si PMOS device, the mobility in its hole is higher than body Si material, and be tensile strain for strain Si nmos device on (100) crystal face, the mobility of its electronics is also higher than body Si material, therefore, this electric property such as device frequency and current driving ability is higher than the body SiCMOS device of same size;

2. two polycrystalline, the two strain mixing crystal face Si base BiCMOS integrated device prepared of the present invention, adopt selective epitaxial technology, respectively at nmos device and PMOS device active area selective growth strain Si material, improve the flexibility of device layout, enhance BiCMOS device and integrated circuit electric property;

3. the present invention prepares in two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device technique, adopt Poly-SiGe material as grid, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe grid, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

4. two polycrystalline, the maximum temperature that relates in two strain mixing crystal face Si base BiCMOS integrated device process that prepared by the present invention are 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

5. the present invention prepare two polycrystalline, the raceway groove of PMOS device is hollow in two strain mixing crystal face Si base BiCMOS integrated device, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

6. the present invention prepare two polycrystalline, in two strain mixing crystal face Si base BiCMOS integrated device, in order to effectively suppress short-channel effect in MOS device structure, introducing light dope source and drain (LDD) technique, improve device performance;

7. the present invention prepare two polycrystalline, in two strain mixing crystal face Si base BiCMOS integrated device structure, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device.

Accompanying drawing explanation

Fig. 1 is the realization flow figure of provided by the invention pair of polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device, nmos device and PMOS device are strain Si MOS device, and bipolar device is two polycrystal SiGe HBT.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of nmos device is strain Si material, and the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

As a prioritization scheme of the embodiment of the present invention, the conducting channel of PMOS device is strain Si material, and the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel.

As a prioritization scheme of the embodiment of the present invention, nmos device is prepared in the SOI substrate that crystal face is (100), and PMOS device is prepared on the substrate of crystal face for (110).

As a prioritization scheme of the embodiment of the present invention, the base of SiGeHBT device is strain SiGe material.

As a prioritization scheme of the embodiment of the present invention, the emitter of SiGeHBT device and base stage adopt polycrystalline silicon material.

The technological process prepared referring to accompanying drawing 1 couple of the present invention two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and circuit is described in further detail.

Embodiment 1: preparation 22nm two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by bipolar device active area.

(2g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGeHBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by device deep trench isolation.

(6d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 7, prepared by PMOS device active area.

(7h) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 8, prepared by nmos device active area.

(8e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device.

Step 9, PMOS device leaks bonding pad preparation.

(9d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 10, prepared by PMOS grid bonding pad.

(10c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 11, prepared by nmos device.

(11c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(11f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device.

Step 12, forms the preparation of BiCMOS integrated circuit.

(12a) photoetching lead-in wire window;

Embodiment 2: preparation 30nm two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material of lower floor;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 400 DEG C of temperature;

(1e) substrate temperature after bonding is raised 150 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 150nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by bipolar device active area.

(2a) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 2.5 μm, as collector region, this layer of doping content is 5 × 10 ¹⁶cm ^-3;

(2b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(2c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(2e) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiGe layer of 40nm in Grown a layer thickness, and as base, this layer of Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3;

(2f) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 15nm;

(2g) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 240nm.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 240nm;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 260nm;

(4e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGeHBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 5 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 3 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by device deep trench isolation.

(6a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(6b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(6c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5 μm;

(6d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 7, prepared by PMOS device active area.

(7a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 4.6 μm, oxide layer is carved thoroughly;

(7b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2 μm along (110) crystal face, doping content is 3 × 10 ¹⁵cm ^-3;

(7c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 2 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(7e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(7f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 30nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(7g) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(7h) utilize chemical vapor deposition (CVD) method, at 700 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 8, prepared by nmos device active area.

(8a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.3 μm;

(8b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 300nm, doping content is 3 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.75 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 3 × 10 ¹⁶cm ^-3;

(8e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, regrowth a layer thickness is the P type strained si layer/of 17nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 9, PMOS device leaks bonding pad preparation.

(9a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(9b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.5 μm of leakage groove;

(9c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(9d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 10, prepared by PMOS device grid bonding pad.

(10a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.7 μm of gate groove;

(10b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(10c) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 20%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 11, prepared by nmos device.

(11a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(11b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 200nm, Ge component is 20%;

(11c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(11d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 3 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(11e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one thickness is the SiO of 4nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(11f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 3 × 10 ²⁰cm ^-3, form nmos device.

Step 12, forms BiCMOS integrated circuit.

(12a) photoetching lead-in wire window;

(12c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final formation conducting channel is two polycrystalline of 30nm, two strain mixing crystal face Si base BiCMOS integrated device and circuit.

Embodiment 3: preparation 45nm two polycrystalline, two strain mixing crystal face Si base BiCMOS integrated device and circuit, concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material of lower floor's active layer;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 480 DEG C of temperature;

(1e) substrate temperature after bonding is raised 100 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 200nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by bipolar device active area.

(2a) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 3 μm, as collector region, this layer of doping content is 1 × 10 ¹⁷cm ^-3;

(2b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(2c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(2e) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the SiGe layer of 60nm in Grown a layer thickness, and as base, this layer of Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3;

(2f) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 20nm;

(2g) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 300nm.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 300nm;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 325nm;

(4e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGeHBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ²⁰cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 5 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector electrode;

(5f) to substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation, formed SiGeHBT.

Step 6, prepared by device deep trench isolation.

(6a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(6b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(6d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 7, prepared by PMOS device active area.

(7a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 5.8 μm, oxide layer is carved thoroughly;

(7b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2.5 μm along (110) crystal face, doping content is 5 × 10 ¹⁵cm ^-3;

(7c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 2.5 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(7d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device;

(7e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(7f) utilize chemical vapor deposition (CVD) method, at 750 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 45nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(7g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(7h) utilize chemical vapor deposition (CVD) method, at 750 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the source region of PMOS device.

Step 8, prepared by nmos device active area.

(8a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.8 μm;

(8b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 400nm, doping content is 5 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 2 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(8e) utilize chemical vapor deposition (CVD) method, at 750 DEG C, regrowth a layer thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 9, PMOS device leaks bonding pad preparation.

(9a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(9b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.7 μm of leakage groove;

(9c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(9d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 10, prepared by PMOS device grid bonding pad.

(10a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.9 μm of gate groove;

(10b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(10c) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 11, prepared by nmos device.

(11a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(11b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 300nm, Ge component is 30%;

(11c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(11d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(11e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one thickness is the SiO of 5nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device gate lateral wall, form nmos device grid;

(11f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 5 × 10 ²⁰cm ^-3, form nmos device.

Step 12, forms BiCMOS integrated circuit.

(12a) photoetching lead-in wire window;

(12c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final formation conducting channel is two polycrystalline of 45nm, two strain mixing crystal face Si base BiCMOS integrated device and circuit.

Two polycrystalline that the embodiment of the present invention provides, two strain mixing crystal face Si base BiCMOS integrated device and preparation method's tool have the following advantages:

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1. a preparation method for two polycrystalline two strain mixing crystal face Si base BiCMOS integrated device, is characterized in that, comprise the steps:

The first step, choose two panels N-type doping Si sheet, wherein a slice crystal face is (110), and a slice crystal face is (100), and two panels doping content is 1 × 10 ¹⁵cm ^-3~ 5 × 10 ¹⁵cm ^-3, be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm; Be the basis material of a slice as upper strata of (100) using crystal face, and in this basis material hydrogen injecting, be the basis material of a slice as lower floor of (110) using crystal face; Chemico-mechanical polishing (CMP) technique is adopted to carry out polishing to two oxide layer surfaces;

Tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, and to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGeHBT device;

12 step, photoetching PMOS device active area, in PMOS device active area, utilize dry etching, etches the deep trouth that the degree of depth is 3.4 ~ 5.8 μm, the oxide layer of centre carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth seven layer material on the PMOS device active area of (110) crystal face substrate: ground floor is N-type Si resilient coating, and thickness is 1.5 ~ 2.5 μm, and doping content is 1 × 10 ¹⁵cm ^-3~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be N-type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 × 10 ¹⁵cm ^-3~ 5 × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 × 10 ²⁰cm ^-3~ 10 × 10 ²⁰cm ^-3, as the drain region of PMOS device; 4th layer is thickness is 3 ~ 5nmP type strained si layer/, and doping content is 1 × 10 ¹⁸cm ^-~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer; Layer 5 to be thickness the be N-type strain Si of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 × 10 ¹⁸cm ^-3~ 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 × 10 ¹⁹cm ^-3~ 10 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

13 step, photoetching nmos device active area, in nmos device active area, utilize dry etching, etch the deep trouth that the degree of depth is 1.9 ~ 2.8 μm, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 × 10 ¹⁵cm ^-3~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be P type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 × 10 ¹⁵cm ^-3~ 5 × 10 ¹⁵cm ^-3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3; The N-type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

14 step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600 ~ 800 DEG C, deposit one deck SiO ₂resilient coating and layer of sin, etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.3 ~ 0.7 μm of leakage groove; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, form PMOS device and leak trenched side-wall isolation; Dry etching is utilized to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3~ 5 × 10 ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-SiGe beyond flute surfaces, formed and leak bonding pad;

15 step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5 ~ 0.9 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3~ 5 × 10 ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

16 step, etch nmos device active area, utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100 ~ 300nm, Ge component is 10 ~ 30%, etching N MOS device grid; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Be the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, dry etching falls this layer of SiO ₂, as nmos device grid curb wall, form nmos device grid;

17 step, carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3~ 5 × 10 ²⁰cm ^-3;

18 step, photoetching lead-in wire window, sputter layer of metal titanium (Ti) alloy over the entire substrate, photoetching goes between, and forming conducting channel is two polycrystalline of 22 ~ 45nm, two strain mixing crystal face Si base BiCMOS integrated device.

2. preparation method according to claim 1, wherein, PMOS device channel length is determined according to the N-type strained si layer/layer thickness of the 12 step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

3. preparation method according to claim 1, is characterized in that, maximum temperature involved in this preparation method determines to chemical vapor deposition (CVD) technological temperature in the 18 step according to the 4th step, and maximum temperature is less than or equal to 800 DEG C.

4. preparation method according to claim 1, is characterized in that, base thickness decides according to the 4th step SiGe layer thickness, gets 20 ~ 60nm.

5. a preparation method for two polycrystalline two strain mixing crystal face Si base BiCMOS integrated circuit, is characterized in that, comprise the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as upper strata basis material, and in this upper strata basis material hydrogen injecting;

Step 2, implementation method prepared by bipolar device active area is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

Step 5, the implementation method that SiGeHBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

Step 6, implementation method prepared by device deep trench isolation is:

Step 7, implementation method prepared by PMOS device active area is:

Step 8, implementation method prepared by nmos device active area is:

Step 10, implementation method prepared by PMOS grid bonding pad is:

Step 11, implementation method prepared by nmos device is:

(11c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(12a) photoetching lead-in wire window;

(12b) sputter layer of metal titanium (Ti) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms Metal Contact;