CN102751280B - A kind of strain SiGe hollow raceway groove BiCMOS integrated device and preparation method - Google Patents

Abstract

The invention discloses a strained SiGe back-channel BiCMOS integrated device and a preparation method thereof. The process is as follows: growing an N-type Si epitaxial layer on an SOI substrate as a collector area of a bipolar device, preparing deep trench isolation, and then sequentially preparing Base polycrystalline, base region, emitter region and collector to form SiGe HBT device; grow five layers of material in the active region of substrate NMOS device, prepare drain, gate and source region, and complete the preparation of NMOS device; in PMOS device Three layers of materials are grown in the active area, dummy gates are prepared, and the source and drain of PMOS devices are formed by self-alignment process implantation; dummy gates are etched to complete the preparation of PMOS devices, forming strained SiGe back channel BiCMOS integrated devices and circuits; In the preparation process of the invention, the full self-alignment process is adopted, which effectively reduces the parasitic resistance and capacitance, improves the current and frequency characteristics of the device, and the SiGe HBT emitter, base and collector are all polycrystalline, reducing the The area of the active area of the device and the size of the device are reduced, and the integration degree of the circuit is improved.

Description

A strained SiGe back channel BiCMOS integrated device and its preparation method

technical field

The invention belongs to the technical field of semiconductor integrated circuits, in particular to a strained SiGe back channel BiCMOS integrated device and a preparation method.

Background technique

Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars.

Si CMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. However, with the further increase of the scale of integrated circuits, the reduction of device feature size, the increase of integration and complexity, especially after the device feature size enters the nanometer scale, the limitations of materials and physical characteristics of Si CMOS devices have gradually emerged. out, limiting the further development of Si integrated circuits and their manufacturing processes. Although microelectronics has made great progress in the research of compound semiconductors and other new materials and their applications in some fields, they are far from being able to replace silicon-based processes. Moreover, according to the development law of science and technology, it generally takes 20 to 30 years for a new technology to become the main technology from its birth. Therefore, in order to meet the needs of traditional performance improvement, enhancing the performance of SiCMOS is considered to be the development direction of the microelectronics industry.

The use of strained Si/SiGe technology is to improve mobility and improve device performance by introducing stress into traditional bulk Si devices. It can improve the performance of products produced by silicon wafers by 30% to 60%, while the process complexity and cost only increase by 1% to 3%. For many existing integrated circuit production lines, if the strained SiGe material is used, not only can the performance of the produced Si CMOS integrated circuit chip be significantly improved without increasing the investment, but it can also greatly extend the integration time spent on the huge investment. The useful life of the circuit production line.

Contents of the invention

The object of the present invention is to utilize to prepare strained SiGe planar channel PMOS device, strained SiGe vertical channel NMOS device and SOI three polycrystalline SiGe HBT device on a substrate sheet, constitute strained SiGe back type channel BiCMOS integrated device and circuit, with Realize the optimization of device and integrated circuit performance.

The object of the present invention is to provide a strained SiGe back-type channel BiCMOS integrated device, the strained SiGe back-type channel Si-based BiCMOS integrated device adopts SOI three polycrystalline SiGe HBT devices, strained SiGe vertical channel NMOS devices and strained SiGe Planar channel PMOS devices.

Further, the conduction channel of the NMOS device is a strained SiGe material, and the tensile strain is in the direction of the channel.

Further, the conduction channel of the PMOS device is a strained SiGe material, and the direction of the channel is a compressive strain.

Further, the emitter, base and collector of the SiGe HBT device are all contacted by polysilicon.

Further, the strained SiGe back channel Si-based BiCMOS integrated device has a full planar structure.

Further, the conduction channel of the NMOS device is of a reverse shape, and the direction of the channel is perpendicular to the surface of the substrate.

Another object of the present invention is to provide a method for preparing a strained SiGe back channel BiCMOS integrated device, comprising the following steps:

The first step is to select an SOI substrate with an oxide layer thickness of 150-400nm, an upper Si thickness of 100-150nm, and an N-type doping concentration of 1×10 ¹⁶ to 1×10 ¹⁷ cm ^-3 ;

The second step is to use chemical vapor deposition chemical vapor deposition (CVD) method to grow an N-type Si epitaxial layer with a thickness of 50-100nm on the substrate at 600-750°C as the collector area. , the doping concentration of this layer is 1×10 ¹⁶ ~1×10 ¹⁷ cm ^-3 ;

The third step is to use the chemical vapor deposition (CVD) method to grow a layer of SiO ₂ with a thickness of 300-500nm on the surface of the epitaxial Si layer at 600-800°C, and to isolate the deep groove by photolithography. A deep groove with a depth of 2.5~3.5μm is etched by regional dry method, and then the chemical vapor deposition (CVD) method is used to fill the deep groove with SiO ₂ at 600~800°C; finally, chemical mechanical polishing (CMP ) method to remove the excess oxide layer on the surface to form deep trench isolation;

The fourth step is to use the method of chemical vapor deposition (CVD) to deposit a layer of SiO ₂ with a thickness of 200-300nm on the surface of the epitaxial Si layer at 600-800°C, and photolithography the collector contact area window. The substrate is implanted with phosphorus, so that the doping concentration of the collector contact area is 1×10 ¹⁹ to 1×10 ²⁰ cm ^-3 to form a collector contact area, and then the substrate is annealed at a temperature of 950-1100°C for 15-120s , for impurity activation;

The fifth step is to etch off the oxide layer on the surface of the substrate, and use the chemical vapor deposition (CVD) method to deposit two layers of materials on the surface of the substrate at 600-800°C: the first layer is SiO ₂ layer, the thickness 20~40nm; the second layer is a P-type Poly-Si layer with a thickness of 200~400nm and a doping concentration of 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ;

Step 6: Lithograph Poly-Si to form the extrinsic base region, and use chemical vapor deposition (CVD) method to deposit SiO ₂ layer on the surface of the substrate at 600-800°C with a thickness of 200-400nm. Mechanical polishing (CMP) method to remove SiO ₂ on the surface of Poly-Si;

Step 7: Deposit a SiN layer with a thickness of 50-100nm at 600-800°C by chemical vapor deposition (CVD), etch the SiN layer in the window of the emission area by photolithography and Poly-Si layer; and then use the chemical vapor deposition (CVD) method to deposit a layer of SiN layer on the surface of the substrate at 600-800°C with a thickness of 10-20nm, and dry-etch the emission window SiN, form side walls;

Step 8: Use wet etching to over-etch the SiO ₂ layer in the window to form a base area, and use chemical vapor deposition (CVD) method to selectively grow SiGe in the base area at 600-750°C In the base region, the Ge composition is 15~25%, the doping concentration is 5×10 ¹⁸ ~5×10 ¹⁹ cm ^-3 , and the thickness is 20~60nm;

Step 9: Lithograph the collector window, use the chemical vapor deposition (CVD) method to deposit Poly-Si on the surface of the substrate at 600-800°C with a thickness of 200-400nm, and then perform phosphorus implantation on the substrate , and use chemical mechanical polishing (CMP) to remove Poly-Si on the surface outside the emitter and collector regions to form emitters and collectors;

The tenth step, using the chemical vapor deposition (CVD) method, at 600 ~ 800 ℃, deposit a SiO ₂ layer on the surface of the substrate, photolithography the collector, and perform phosphorus implantation on the contact hole to improve the collector The doping concentration of Poly-Si is 1×10 ¹⁹ ~1×10 ²⁰ cm ^-3 , and finally the SiO ₂ layer on the surface is removed;

The eleventh step, using the chemical vapor deposition (CVD) method, deposit a _SiO2 layer on the substrate surface at 600-800°C, and anneal at 950-1100°C for 15-120s to activate impurities;

Step 12: Lithographically etch the active area of the NMOS device, using a dry etching process, etch a deep groove with a depth of 1.5-2.0 μm in the active area of the NMOS device, and use the method of chemical vapor deposition (CVD) , at 600-750°C, five layers of material are continuously grown in deep grooves: the first layer is an N-type Si epitaxial layer with a thickness of 1.3-1.6 μm, and the doping concentration is 5×10 ¹⁹ ～1×10 ²⁰ cm ^-3 , as the drain region of NMOS devices; the second layer is an N-type strained SiGe layer with a thickness of 3~5nm, a doping concentration of 1~5×10 ¹⁸ cm ^-3 , and a Ge composition of 10%. N-type lightly doped source-drain structure (N-LDD) layer; the third layer is a P-type strained SiGe layer with a thickness of 22-45nm and a doping concentration of 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 , the Ge group Divided into a gradient distribution, the lower layer is 10%, and the upper layer is a gradient distribution of 20-30%, which is used as the channel region of the NMOS device; the fourth layer is an N-type strained SiGe layer with a thickness of 3-5nm, and a doping concentration of 1-5 ×10 ¹⁸ cm ^-3 , Ge composition is 20-30%, as the second N-type lightly doped source-drain structure (N-LDD) layer of NMOS devices; the fifth layer is N-type with a thickness of 200-400nm The Si layer, with a doping concentration of 5×10 ¹⁹ to 1×10 ²⁰ cm ^-3 , serves as the source region of the NMOS device;

The thirteenth step, using the method of chemical vapor deposition (CVD), deposit a layer of SiO ₂ on the surface of the substrate at 600-780°C, photolithographically the active area of the PMOS device, and use chemical vapor deposition (CVD) ) method, at 600-750°C, selectively epitaxially grow a layer of N-type relaxed Si layer in the deep groove, the doping concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 , the thickness is 30-50 μm, Grow an N-type strained SiGe layer again, with a doping concentration of 5×10 ¹⁶ to 5×10 ¹⁷ cm ^-3 , a Ge composition of 10 to 30%, and a thickness of 10 to 20 nm, and finally grow an intrinsically relaxed Si cap layer, with a thickness of 3-5nm, filling the trench to form the active area of the PMOS device; using wet etching to etch away the SiO ₂ layer on the surface;

The fourteenth step, using the chemical vapor deposition (CVD) method, at 600-800 ° C, grow a layer of SiO ₂ with a thickness of 200-300 nm on the surface of the epitaxial Si layer, and isolate the shallow groove by photolithography. A shallow groove with a depth of 300-500nm is dry-etched in the isolation area, and then the chemical vapor deposition (CVD) method is used to fill the shallow groove with SiO ₂ at 600-800°C; finally, chemical mechanical polishing (CMP ) method to remove the excess oxide layer on the surface to form shallow trench isolation;

Step 15: Deposit a layer of SiO ₂ and a layer of SiN on the surface of the substrate by chemical vapor deposition (CVD) at 600-780°C to form a barrier layer; photolithographically NMOS device drain trench, use Dry etching process, etch a drain trench with a depth of 0.4-0.6 μm; use chemical vapor deposition (CVD) method to deposit a layer of SiO ₂ on the substrate surface at 600-780 ° C to form NMOS Device drain trench sidewall isolation, dry etching away the SiO ₂ on the surface, retaining SiO ₂ on the sidewall of the drain trench, using chemical vapor deposition (CVD) method, at 600-780°C, depositing doping concentration N-type Poly-Si of 1 to 5×10 ²⁰ cm ^-3 is used to fill the groove, and the excess Poly-Si on the substrate surface is removed by chemical mechanical polishing (CMP) to form the drain connection region of the NMOS device; wet etching is used , etch away the surface layer SiO ₂ and SiN;

The sixteenth step, using the chemical vapor deposition (CVD) method, deposit a layer of SiO ₂ and a layer of SiN on the surface of the substrate at 600-780 ° C to form a barrier layer again; photolithographically NMOS device gate window, use Dry etching process, etch a gate trench with a depth of 0.4-0.6 μm; use atomic layer chemical vapor deposition (ALCVD) method, at 300-400 ° C, deposit a layer with a thickness of 5 ～8nm HfO ₂ , form the gate dielectric layer of NMOS devices, and then use chemical vapor deposition (CVD) method, at 600～780℃, deposit doping concentration of 1～5×10 ²⁰ cm ^-3 on the substrate surface N-type Poly-Si, fill the gate trench of the NMOS device, and then remove the Poly-Si and HfO ₂ on the outer surface of the gate trench of the NMOS device to form the gate and source regions of the NMOS device, and finally form the NMOS device; use a wet method Corrosion, etch away the surface layer SiO ₂ and SiN;

The seventeenth step, using the chemical vapor deposition (CVD) method, deposit a layer of SiO ₂ on the substrate surface at 600-780 ° C, photolithographically PMOS device active area, using chemical vapor deposition (CVD) The method is to deposit a layer of SiO ₂ with a thickness of 10-15nm and a layer of Poly-Si with a thickness of 200-300nm on the surface of the substrate at 600-780°C, and photolithography Poly-Si and SiO ₂ to form a virtual PMOS device. gate; perform P-type ion implantation on PMOS devices to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1 to 5×10 ¹⁸ cm ^-3 ;

Step 18: Deposit a layer of SiO 2 with a thickness of 3-5nm on the substrate surface at 600-780°C by chemical vapor deposition (CVD), and dry-etch away the SiO ₂ on the substrate surface. SiO ₂ , keep the SiO ₂ of the Ploy-Si sidewall to form the sidewall of the gate electrode of the PMOS device; then perform P-type ion implantation on the active region of the PMOS device, and self-align to generate the source and drain regions of the PMOS device, so that the source and drain The doping concentration of the region reaches 5×10 ¹⁹ ～1×10 ²⁰ cm ^-3 ;

The nineteenth step, use the chemical vapor deposition (CVD) method to deposit a SiO ₂ layer on the substrate surface at 600-780 ° C, use the chemical mechanical polishing (CMP) method to smooth the surface, and then use the dry etching process Etch the surface SiO ₂ to the upper surface of the dummy gate to expose the dummy gate; wet etch the dummy gate to form a groove at the gate electrode; Deposit a layer of SiON on the bottom surface with a thickness of 1.5~5nm; use physical vapor deposition (PVD) to deposit W-TiN composite gate, use chemical mechanical polishing (CMP) to remove the surface metal, and use W-TiN composite gate as chemical mechanical polishing (CMP) termination layer, thereby forming the gate, and finally forming a PMOS device;

The twentieth step, using the chemical vapor deposition (CVD) method, at 600-780 ° C, deposit a _SiO2 layer on the substrate surface, photolithography lead holes, metallization, sputtering metal, photolithography leads, and form MOS The conductive channel of the device is a BiCMOS integrated device with a strained SiGe back channel of 22-45nm.

Further, the channel length of the NMOS device is determined according to the thickness of the P-type strained SiGe layer deposited in the twelfth step, which is 22-45 nm.

Further, the chemical vapor deposition (CVD) process temperature involved in the preparation method is determined, and the highest temperature is less than or equal to 800°C.

Further, wherein, the thickness of the base region is determined according to the thickness of the epitaxial layer of SiGe in the eighth step, which is 20-60 nm.

Another object of the present invention is to provide a method for preparing a strained SiGe back channel BiCMOS integrated circuit, comprising the steps of:

Step 1, the implementation method of epitaxial growth is:

(1a) Select the SOI substrate sheet, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 400nm, and the upper layer material is N-type Si with a doping concentration of 1×10 ¹⁷ cm ^-3 with a thickness of 150nm;

(1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 ¹⁷ cm ^-3 ;

Step 2, the implementation method of deep groove isolation preparation is:

(2a) Using chemical vapor deposition (CVD), at 800°C, grow a layer of SiO ₂ with a thickness of 500nm on the surface of the epitaxial Si layer;

(2b) Photoetched deep trench isolation regions;

(2c) Dry etching a deep trench with a depth of 2.5 μm in the deep trench isolation region;

(2d) Deposit SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD), and fill the deep groove;

(2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep groove isolation;

Step 3, the realization method of the preparation of the collector contact area is as follows:

(3a) By chemical vapor deposition (CVD), at 800°C, a _SiO2 layer with a thickness of 300nm should be deposited on the surface of the epitaxial Si layer;

(3b) Photolithographic collector contact area window;

(3c) Phosphorus is implanted into the substrate so that the doping concentration of the collector contact region is 1×10 ²⁰ cm ^-3 , forming a collector contact region;

(3d) annealing the substrate at a temperature of 1100°C for 15s to activate impurities;

Step 4, the implementation method of base contact preparation is:

(4a) Etch the oxide layer on the surface of the substrate, and deposit a layer of SiO ₂ with a thickness of 40nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

(4b) Deposit a P-type Poly-Si layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD) as the base contact region. The layer thickness is 400nm and the doping concentration is 1 ×10 ²¹ cm ^-3 ;

(4c) Lithograph Poly-Si to form an extrinsic base region, deposit a SiO ₂ layer on the substrate surface at 800°C with a thickness of 400nm, and remove SiO ₂ on the Poly-Si surface by chemical mechanical polishing (CMP);

(4d) Depositing a SiN layer on the surface of the substrate at 800° C. with a thickness of 100 nm by chemical vapor deposition (CVD);

(4e) Photolithography of the emission region window, etching away the SiN layer and Poly-Si layer in the emission region window;

(4f) Deposit a SiN layer on the surface of the substrate at 800°C with a thickness of 20 nm by chemical vapor deposition (CVD);

Step 5, the implementation method of base area material preparation is:

(5a) using a dry method to etch away the emission window SiN to form side walls;

(5b) Using wet etching, the _SiO2 layer in the window is over-etched to form a base region;

(5c) Using the chemical vapor deposition (CVD) method, at 750°C, selectively grow a SiGe base region in the base region, with a Ge composition of 25%, a doping concentration of 5×10 ¹⁹ cm ^-3 , and a thickness of 60nm;

Step 6, the implementation method of the emission area preparation is:

(6a) Photoetching the collector window, using the chemical vapor deposition (CVD) method, depositing Poly-Si on the surface of the substrate at 800°C with a thickness of 400nm;

(6b) Perform phosphorus implantation on the substrate, and use chemical mechanical polishing (CMP) to remove Poly-Si on the surface outside the emitter and collector regions to form emitters and collectors;

(6c) Deposit a _SiO2 layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

(6d) Lithograph the collector, and perform phosphorus implantation again in this area to increase the doping concentration of Poly-Si in the collector to 1×10 ²⁰ cm ^-3 , and finally remove the SiO ₂ layer on the surface;

(6e) Deposit a _SiO2 layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD), and anneal at 1100°C for 15s to activate the impurities;

Step 7, the implementation method of preparing the active regions of NMOS and PMOS devices is as follows:

(7a) Lithographically etching the active area of the NMOS device, using a dry etching process to etch a deep groove with a depth of 2 μm in the active area of the NMOS device;

(7b) Using chemical vapor deposition chemical vapor deposition (CVD), at 600 ° C, an N-type Si epitaxial layer with a thickness of 1.6 μm was selectively grown in the active region of the NMOS device, and the doping concentration was 5× 10 ¹⁹ cm ^-3 , as the drain region of NMOS devices;

(7c) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5 nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , The Ge composition is 10%, which is used as the first N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7d) Using chemical vapor deposition (CVD), at 600°C, selectively grow a P-type strained SiGe layer with a thickness of 45nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 , The Ge composition has a gradient distribution, the lower layer is 10%, and the upper layer is 30%, which is used as the channel region of the NMOS device;

(7e) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5 nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , The Ge composition is 30%, which is used as the second N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7f) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type Si layer with a thickness of 400nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁹ cm ^-3 , as NMOS device source area;

(7g) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

(7h) Lithograph the active region of the PMOS device, using the chemical vapor deposition (CVD) method, at 600°C, selectively grow an N-type relaxed Si layer in the deep groove of the active region of the PMOS device, the doping concentration is 5×10 ¹⁶ cm ^-3 , thickness 50nm;

(7i) Selectively grow an N-type strained SiGe layer with a doping concentration of 5×10 ¹⁶ cm ^-3 in the deep groove of the active region of the PMOS device at 600°C by chemical vapor deposition (CVD), The Ge component is 10%, and the thickness is 20nm;

(7j) Using chemical vapor deposition (CVD), at 600°C, selectively grow an intrinsically relaxed Si cap layer in the deep groove of the active region of the PMOS device, with a thickness of 5nm, to form an N well;

(7k) using wet etching to etch away the SiO ₂ layer on the surface;

Step 8, the implementation method of shallow groove isolation preparation is:

(8a) Using chemical vapor deposition (CVD), at 600-800°C, grow a layer of SiO ₂ with a thickness of 300nm on the surface of the epitaxial Si layer;

(8b) Shallow groove isolation by photolithography, using dry etching process to etch a shallow groove with a depth of 500nm in the isolation area;

(8c) Filling the shallow groove with SiO ₂ at 800°C by chemical vapor deposition (CVD);

(8d) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation;

Step 9, the realization method of NMOS device drain connection preparation is as follows:

(9a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 800°C by chemical vapor deposition (CVD) to form a barrier layer;

(9b) Lithographically etching the drain trench of the NMOS device, using a dry etching process to etch a drain trench with a depth of 0.6 μm;

(9c) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD) to form NMOS device drain trench sidewall isolation, and dry-etch away the SiO ₂ on the surface, leaving SiO ₂ on the sidewall of the drain trench;

(9d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the substrate surface at 800°C by chemical vapor deposition (CVD) to fill the drain trench of the NMOS device ;

(9e) Using a chemical mechanical polishing (CMP) method to remove excess Poly-Si on the surface of the substrate to form a drain connection region of an NMOS device;

(9f) using wet etching to etch away the surface layers SiO ₂ and SiN;

Step 10, the implementation method of NMOS device formation is:

(10a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 600°C by chemical vapor deposition (CVD) to form a barrier layer again;

(10b) Photoetching the gate window of the NMOS device, using a dry etching process to etch a gate trench with a depth of 0.6 μm;

(10c) Deposit a layer of HfO ₂ with a thickness of 5 nm on the surface of the substrate at 300° C. by atomic layer chemical vapor deposition (ALCVD) to form a gate dielectric layer for NMOS devices;

(10d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the substrate surface at 600°C by chemical vapor deposition (CVD) to fill the gate trenches of NMOS devices ;

(10e) Removing part of the Poly-Si and HfO ₂ layers on the surface of the gate trench of the NMOS device, forming the gate and source regions of the NMOS device, and finally forming the NMOS device;

(10f) using wet etching to etch away the SiO ₂ and SiN layers on the surface;

Step 11, the implementation method of preparing the virtual gate and source and drain of the PMOS device is as follows:

(11a) Deposit a layer of SiO ₂ on the surface of the active region of the NMOS device at 600°C by chemical vapor deposition (CVD);

(11b) Photoetching the active region of the PMOS device, using chemical vapor deposition (CVD) method, at 600°C, depositing a layer of SiO ₂ with a thickness of 10nm on the surface of the substrate;

(11c) Deposit a layer of Poly-Si with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

(11d) Photoetching Poly-Si and SiO ₂ to form a virtual gate of a PMOS device;

(11e) Perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

(11f) Deposit a layer of SiO ₂ with a thickness of 3nm on the substrate surface at 600°C by chemical vapor deposition (CVD), and dry-etch away the SiO ₂ on the substrate surface, leaving the Poly- SiO ₂ on the Si sidewall forms the gate electrode sidewall of the PMOS device;

(11g) P-type ion implantation is performed on the active region of the PMOS device, and the source and drain regions of the PMOS device are generated by self-alignment, so that the doping concentration of the source and drain regions reaches 5×10 ¹⁹ cm ^-3 ;

Step 12, the implementation method of PMOS device formation is:

(12a) Using chemical vapor deposition (CVD method, at 600°C, deposit a SiO ₂ layer on the substrate surface, use chemical mechanical polishing (CMP) to flatten the surface, and then etch the surface SiO ₂ by dry etching process to the upper surface of the dummy grid to expose the dummy grid;

(12b) Wet etching the dummy gate to form a groove at the gate electrode;

(12c) Deposit a layer of SiON on the surface of the substrate at 600°C with a thickness of 5 nm by chemical vapor deposition (CVD);

(12d) Deposit the W-TiN composite gate by physical vapor deposition (PVD), and remove the surface metal by chemical mechanical polishing (CMP);

(12e) Using the W-TiN composite gate as the stop layer of chemical mechanical polishing (CMP) to form the gate and finally form the PMOS device;

Step 13, the implementation method of forming a BiCMOS integrated circuit is:

(13a) Deposit a _SiO2 layer on the substrate surface at 600°C by chemical vapor deposition (CVD);

(13b) Photolithographic lead holes;

(13c) metallization;

(13d) Sputtering metal, photolithography leads, forming NMOS device drain metal leads, source metal leads and gate metal leads, PMOS device drain metal leads, source metal leads and gate metal leads, bipolar transistor emission Electrode metal leads, base metal leads, and collector metal leads form strained SiGe back-channel BiCMOS integrated devices and circuits with a 45nm conductive channel of the MOS device.

The present invention has the following advantages:

1. In the strained SiGe back channel BiCMOS integrated device prepared by the present invention, the anisotropic characteristics of strained SiGe material stress are fully utilized, and compressive strain is introduced in the horizontal direction to improve the hole mobility of the PMOS device; tension is introduced in the vertical direction. Strain improves the electron mobility of the NMOS device, so the performance of the device such as frequency and current drive capability is higher than that of the relaxed Si CMOS device of the same size;

2. In the process of preparing strained SiGe back channel BiCMOS integrated devices, the invention adopts selective epitaxy technology to selectively grow strained SiGe materials in the active regions of NMOS devices and PMOS devices respectively, which improves the flexibility of device design and enhances CMOS Electrical performance of devices and integrated circuits;

3. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the channel direction of the NMOS device is the vertical direction, and the channel is a strained SiGe layer prepared by chemical vapor deposition (CVD), and the thickness of the SiGe layer is The channel length of the NMOS device, therefore, avoids the photolithography of the small-sized gate in the preparation of the NMOS device, reduces the complexity of the process, and reduces the cost;

4. The channel of the NMOS device in the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention is a back type, that is, a gate can control the channels on four sides in the trench, so the device increases the channel in a limited area. The width of the track improves the current driving capability of the device, increases the integration level of the integrated circuit, and reduces the manufacturing cost per unit area of the integrated circuit;

5. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the Ge composition of the channel of the NMOS device has a gradient change, so a self-built electric field that accelerates electron transport can be generated in the direction of the channel, and the current carrying capacity of the channel is enhanced. Sub-transport capability, thereby improving the frequency characteristics and current drive capability of strained SiGe NMOS devices;

6. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the NMOS device adopts _HfO2 with a high K value as the gate dielectric, which improves the gate control capability of the NMOS device and enhances the electrical performance of the NMOS device;

7. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the PMOS device is a quantum well device, that is, the strained SiGe channel layer is between the Si cap layer and the bulk Si layer. Compared with the surface channel device, the device can Effectively reduce channel interface scattering and improve device electrical characteristics; at the same time, quantum wells can improve the problem of hot electron injection into the gate dielectric, increasing the reliability of devices and circuits;

8. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the PMOS device adopts SiON instead of traditional pure _SiO as the gate dielectric, which not only enhances the reliability of the device, but also utilizes the change of the dielectric constant of the gate dielectric to improve the The gate control capability of the device;

9. The highest temperature involved in the process of preparing the strained SiGe channel BiCMOS in the present invention is 800°C, which is lower than the process temperature that causes the stress relaxation of the strained SiGe channel, so the preparation method can effectively maintain the stress of the strained SiGe channel and improve performance of integrated circuits;

10. In the process of preparing the strained SiGe back channel BiCMOS integrated device of the present invention, the PMOS device adopts the metal gate damascene process (damascene process) to prepare the gate electrode, and the gate electrode is a metal W-TiN composite structure, due to the underlying TiN and strained Si and The work function difference of the strained SiGe material is small, which improves the electrical characteristics of the device, and the W on the upper layer can reduce the resistance of the gate electrode, realizing the optimization of the gate electrode;

11. The strained SiGe back channel BiCMOS integrated device prepared by the present invention adopts a fully self-aligned process during the preparation process, which effectively reduces the parasitic resistance and capacitance, and improves the current and frequency characteristics of the device;

12. The emitter, base and collector of the SiGe HBT device in the strained SiGe back-channel BiCMOS integrated device prepared by the present invention are all polycrystalline, and the polycrystalline can be partially fabricated on the oxide layer, reducing the active area of the device area, thereby reducing the size of the device and improving the integration of the circuit.

Description of drawings

Fig. 1 is a flowchart of the realization of the strained SiGe back channel BiCMOS integrated device and circuit preparation method of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

An embodiment of the present invention provides a strained SiGe back-channel BiCMOS integrated device, the strained SiGe back-channel Si-based BiCMOS integrated device adopts SOI triple polycrystalline/self-aligned SiGe HBT device, strained SiGe vertical channel NMOS devices and strained SiGe planar channel PMOS devices.

As an optimization scheme of the embodiment of the present invention, the conduction channel of the NMOS device is made of strained SiGe material, and the tensile strain is applied along the channel direction.

As an optimization scheme of the embodiment of the present invention, the conduction channel of the PMOS device is made of strained SiGe material, and the direction of the channel is compressively strained.

As an optimization scheme of the embodiment of the present invention, the emitter, base and collector of the SiGe HBT device are all contacted by polysilicon.

As an optimization scheme of the embodiment of the present invention, the strained SiGe back channel Si-based BiCMOS integrated device has a full planar structure.

Referring to the accompanying drawing 1, the technical process of manufacturing the strained SiGe back-channel BiCMOS integrated device and circuit of the present invention will be further described in detail.

Embodiment 1: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 45nm, the specific steps are as follows:

Step 1, epitaxial growth.

(1a) Select the SOI substrate sheet, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 400nm, and the upper layer material is N-type Si with a doping concentration of 1×10 ¹⁷ cm ^-3 with a thickness of 150nm;

(1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 ¹⁷ cm ^-3 .

Step 2, deep trench isolation preparation.

(2a) Using chemical vapor deposition (CVD), at 800°C, grow a layer of SiO ₂ with a thickness of 500nm on the surface of the epitaxial Si layer;

(2b) Photoetched deep trench isolation regions;

(2c) Dry etching a deep trench with a depth of 2.5 μm in the deep trench isolation region;

(2d) Deposit SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD), and fill the deep groove;

(2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

Step 3, preparation of the collector contact area.

(3a) By chemical vapor deposition (CVD), at 800°C, a _SiO2 layer with a thickness of 300nm should be deposited on the surface of the epitaxial Si layer;

(3b) Photolithographic collector contact area window;

(3c) Phosphorus is implanted into the substrate so that the doping concentration of the collector contact region is 1×10 ²⁰ cm ^-3 , forming a collector contact region;

(3d) Annealing the substrate at a temperature of 1100° C. for 15 s to perform impurity activation.

Step 4, base contact preparation.

(4a) Etch the oxide layer on the surface of the substrate, and deposit a layer of SiO ₂ with a thickness of 40nm on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

(4b) Deposit a P-type Poly-Si layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD) as the base contact region. The layer thickness is 400nm and the doping concentration is 1 ×10 ²¹ cm ^-3 ;

(4c) Lithograph Poly-Si to form an extrinsic base region, deposit a SiO ₂ layer on the substrate surface at 800°C with a thickness of 400nm, and remove SiO ₂ on the Poly-Si surface by chemical mechanical polishing (CMP);

(4d) Depositing a SiN layer on the surface of the substrate at 800° C. with a thickness of 100 nm by chemical vapor deposition (CVD);

(4e) Photolithography of the emission region window, etching away the SiN layer and Poly-Si layer in the emission region window;

(4f) Deposit a layer of SiN on the surface of the substrate at 800° C. with a thickness of 20 nm by chemical vapor deposition (CVD).

Step 5, base material preparation.

(5a) using a dry method to etch away the emission window SiN to form side walls;

(5b) Using wet etching, the _SiO2 layer in the window is over-etched to form a base region;

(5c) Using the chemical vapor deposition (CVD) method, at 750°C, selectively grow a SiGe base region in the base region, with a Ge composition of 25%, a doping concentration of 5×10 ¹⁹ cm ^-3 , and a thickness of 60nm.

Step 6, preparation of the emission area.

(6a) Photoetching the collector window, using the chemical vapor deposition (CVD) method, depositing Poly-Si on the surface of the substrate at 800°C with a thickness of 400nm;

(6b) Perform phosphorus implantation on the substrate, and use chemical mechanical polishing (CMP) to remove Poly-Si on the surface outside the emitter and collector regions to form emitters and collectors;

(6c) Deposit a _SiO2 layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD);

(6d) Lithograph the collector, and perform phosphorus implantation again in this area to increase the doping concentration of Poly-Si in the collector to 1×10 ²⁰ cm ^-3 , and finally remove the SiO ₂ layer on the surface;

(6e) Deposit a SiO ₂ layer on the surface of the substrate at 800°C by chemical vapor deposition (CVD), and anneal at 1100°C for 15s to activate the impurities.

Step 7, preparation of active regions of NMOS and PMOS devices.

(7a) Lithographically etching the active area of the NMOS device, using a dry etching process to etch a deep groove with a depth of 2 μm in the active area of the NMOS device;

(7b) Using chemical vapor deposition chemical vapor deposition (CVD), at 600 ° C, an N-type Si epitaxial layer with a thickness of 1.6 μm was selectively grown in the active region of the NMOS device, and the doping concentration was 5× 10 ¹⁹ cm ^-3 , as the drain region of NMOS devices;

(7c) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5 nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , The Ge composition is 10%, which is used as the first N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7d) Using chemical vapor deposition (CVD), at 600°C, selectively grow a P-type strained SiGe layer with a thickness of 45nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 , The Ge composition is a gradient distribution, the lower layer is 10%, and the upper layer is 30%, which is used as the channel region of the NMOS device;

(7e) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5 nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , The Ge composition is 30%, which is used as the second N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7f) Using chemical vapor deposition (CVD), at 600°C, selectively grow an N-type Si layer with a thickness of 400nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁹ cm ^-3 , as NMOS device source area;

(7g) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

(7h) Lithograph the active region of the PMOS device, using the chemical vapor deposition (CVD) method, at 600°C, selectively grow an N-type relaxed Si layer in the deep groove of the active region of the PMOS device, the doping concentration is 5×10 ¹⁶ cm ^-3 , thickness 50nm;

(7i) Selectively grow an N-type strained SiGe layer with a doping concentration of 5×10 ¹⁶ cm ^-3 in the deep groove of the active region of the PMOS device at 600°C by chemical vapor deposition (CVD), The Ge component is 10%, and the thickness is 20nm;

(7j) Using chemical vapor deposition (CVD), at 600°C, selectively grow an intrinsically relaxed Si cap layer in the deep groove of the active region of the PMOS device, with a thickness of 5nm, to form an N well;

(7k) using wet etching to etch away the SiO ₂ layer on the surface.

Step 8, shallow trench isolation preparation.

(8a) Using chemical vapor deposition (CVD), at 600-800°C, grow a layer of SiO ₂ with a thickness of 300nm on the surface of the epitaxial Si layer;

(8b) Shallow groove isolation by photolithography, using dry etching process to etch a shallow groove with a depth of 500nm in the isolation area;

(8c) Filling the shallow groove with SiO ₂ at 800°C by chemical vapor deposition (CVD);

(8d) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

Step 9, drain connection preparation of the NMOS device.

(9a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 800°C by chemical vapor deposition (CVD) to form a barrier layer;

(9b) Lithographically etching the drain trench of the NMOS device, using a dry etching process to etch a drain trench with a depth of 0.6 μm;

(9c) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition (CVD) to form NMOS device drain trench sidewall isolation, and dry-etch away the SiO ₂ on the surface, leaving SiO ₂ on the sidewall of the drain trench;

(5d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the substrate surface at 800°C by chemical vapor deposition (CVD) to fill the drain trench of the NMOS device ;

(9e) Using a chemical mechanical polishing (CMP) method to remove excess Poly-Si on the surface of the substrate to form a drain connection region of an NMOS device;

(9f) Use wet etching to etch away the SiO ₂ and SiN layers on the surface.

In step 10, an NMOS device is formed.

(10a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 600°C by chemical vapor deposition (CVD) to form a barrier layer again;

(10b) Photoetching the gate window of the NMOS device, using a dry etching process to etch a gate trench with a depth of 0.6 μm;

(10c) Deposit a layer of HfO ₂ with a thickness of 5 nm on the surface of the substrate at 300° C. by atomic layer chemical vapor deposition (ALCVD) to form a gate dielectric layer for NMOS devices;

(10d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the substrate surface at 600°C by chemical vapor deposition (CVD) to fill the gate trenches of NMOS devices ;

(10e) Removing part of the Poly-Si and HfO ₂ layers on the surface of the gate trench of the NMOS device, forming the gate and source regions of the NMOS device, and finally forming the NMOS device;

(10f) Etch away the SiO ₂ and SiN layers on the surface by wet etching.

Step 11, preparing the dummy gate and source and drain of the PMOS device.

(11a) Deposit a layer of SiO ₂ on the surface of the active region of the NMOS device at 600°C by chemical vapor deposition (CVD);

(11b) Photoetching the active region of the PMOS device, using chemical vapor deposition (CVD) method, at 600°C, depositing a layer of SiO ₂ with a thickness of 10nm on the surface of the substrate;

(11c) Deposit a layer of Poly-Si with a thickness of 200nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

(11d) Photoetching Poly-Si and SiO ₂ to form a virtual gate of a PMOS device;

(11e) Perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 1×10 ¹⁸ cm ^-3 ;

(11f) Deposit a layer of SiO ₂ with a thickness of 3nm on the substrate surface at 600°C by chemical vapor deposition (CVD), and dry-etch away the SiO ₂ on the substrate surface, leaving the Poly- SiO ₂ on the Si sidewall forms the gate electrode sidewall of the PMOS device;

(11g) P-type ion implantation is performed on the active region of the PMOS device, and the source and drain regions of the PMOS device are formed by self-alignment, so that the doping concentration of the source and drain regions reaches 5×10 ¹⁹ cm ^-3 .

Step 12, forming a PMOS device.

(12a) Using the chemical vapor deposition (CVD) method, at 600 ° C, deposit a _SiO2 layer on the substrate surface, use the chemical mechanical polishing (CMP) method to flatten the surface, and then use the dry etching process to etch the surface SiO2 ₂ to the upper surface of the dummy grid, exposing the dummy grid;

(12b) Wet etching the dummy gate to form a groove at the gate electrode;

(12c) Deposit a layer of SiON on the surface of the substrate at 600°C with a thickness of 5 nm by chemical vapor deposition (CVD);

(12d) Deposit the W-TiN composite gate by physical vapor deposition (PVD), and remove the surface metal by chemical mechanical polishing (CMP);

(12e) The W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP) to form the gate and finally form the PMOS device.

Step 13, forming a BiCMOS integrated circuit.

(13a) Deposit a _SiO2 layer on the substrate surface at 600°C by chemical vapor deposition (CVD);

(13b) Photolithographic lead holes;

(13c) Metallization;

(13d) Sputtering metal, photolithography leads, forming NMOS device drain metal leads, source metal leads and gate metal leads, PMOS device drain metal leads, source metal leads and gate metal leads, bipolar transistor emission Electrode metal leads, base metal leads, and collector metal leads form strained SiGe back-channel BiCMOS integrated devices and circuits with a 45nm conductive channel of the MOS device.

Embodiment 2: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:

Step 1, epitaxial growth.

(1a) Select the SOI substrate sheet, the support material of the lower layer of the substrate is Si, the middle layer is SiO ₂ , the thickness is 300nm, and the upper layer material is N-type Si with a doping concentration of 5×10 ¹⁶ cm ^-3 , the thickness is 120nm;

(1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 ¹⁶ cm ^-3 .

Step 2, deep trench isolation preparation.

(2a) Using chemical vapor deposition (CVD), at 700°C, grow a layer of SiO ₂ with a thickness of 400nm on the surface of the epitaxial Si layer;

(2b) Photoetched deep trench isolation regions;

(2c) Dry etching a deep trench with a depth of 3 μm in the deep trench isolation region;

(2d) Deposit SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD), and fill the deep groove;

(2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

Step 3, preparation of the collector contact area.

(3a) By chemical vapor deposition (CVD), at 700°C, a _SiO2 layer with a thickness of 240nm should be deposited on the surface of the epitaxial Si layer;

(3b) Photolithographic collector contact area window;

(3c) Phosphorus is implanted into the substrate so that the doping concentration of the collector contact region is 5×10 ¹⁹ cm ^-3 to form a collector contact region;

(3d) Annealing the substrate at a temperature of 1000° C. for 60 s to perform impurity activation.

Step 4, base contact preparation.

(4a) Etch the oxide layer on the surface of the substrate, and deposit a layer of SiO ₂ with a thickness of 30nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

(4b) Deposit a P-type Poly-Si layer on the surface of the substrate at 700°C by chemical vapor deposition (CVD) as the base contact region, with a thickness of 300nm and a doping concentration of 5 ×10 ²⁰ cm ^-3 ;

(4c) Lithograph Poly-Si to form an extrinsic base region, deposit a SiO ₂ layer on the substrate surface at 700°C with a thickness of 300nm, and remove SiO ₂ on the Poly-Si surface by chemical mechanical polishing (CMP);

(4d) Depositing a SiN layer on the surface of the substrate at 700° C. with a thickness of 80 nm by chemical vapor deposition (CVD);

(4e) Photolithography of the emission region window, etching away the SiN layer and Poly-Si layer in the emission region window;

(4f) Deposit a layer of SiN on the surface of the substrate at 700° C. with a thickness of 15 nm by chemical vapor deposition (CVD).

Step 5, base material preparation.

(5a) using a dry method to etch away the emission window SiN to form side walls;

(5b) Using wet etching, the _SiO2 layer in the window is over-etched to form a base region;

(5c) Using the chemical vapor deposition (CVD) method, at 700°C, selectively grow the SiGe base region in the base region, the Ge composition is 20%, the doping concentration is 1×10 ¹⁹ cm ^-3 , and the thickness is 40nm.

Step 6, preparation of the emission area.

(6a) Photoetching the collector window, using the chemical vapor deposition (CVD) method, depositing Poly-Si on the surface of the substrate at 700°C with a thickness of 300nm;

(6b) Perform phosphorus implantation on the substrate, and use chemical mechanical polishing (CMP) to remove Poly-Si on the surface outside the emitter and collector regions to form emitters and collectors;

(6c) Deposit a _SiO2 layer on the substrate surface at 700°C by chemical vapor deposition (CVD);

(6d) Lithograph the collector, and perform phosphorus implantation again in this area to increase the doping concentration of Poly-Si in the collector to 5×10 ¹⁹ cm ^-3 , and finally remove the SiO ₂ layer on the surface;

(6e) Deposit a SiO ₂ layer on the substrate surface at 700°C by chemical vapor deposition (CVD), and anneal at 1000°C for 60s to activate impurities.

Step 7, preparation of epitaxial materials for NMOS and PMOS devices.

(7a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 1.8 μm in the active area of the NMOS device;

(7b) Using chemical vapor deposition chemical vapor deposition (CVD), at 700 ° C, an N-type Si epitaxial layer with a thickness of 1.5 μm was selectively grown in the active region of the NMOS device, and the doping concentration was 8× 10 ¹⁹ cm ^-3 , as the drain region of NMOS devices;

(7c) Using chemical vapor deposition (CVD), at 700°C, selectively grow an N-type strained SiGe layer with a thickness of 4nm in the active region of the NMOS device, with a doping concentration of 3×10 ¹⁸ cm ^-3 , The Ge composition is 10%, which is used as the first N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7d) Using chemical vapor deposition (CVD), at 700°C, selectively grow a P-type strained SiGe layer 4 with a thickness of 30nm in the active region of the NMOS device, with a doping concentration of 1×10 ¹⁷ cm ^-3 , the Ge composition is a gradient distribution, the lower layer is 10%, and the upper layer is 20%, which is used as the channel region of the NMOS device;

(7e) Using chemical vapor deposition (CVD), at 700°C, selectively grow an N-type strained SiGe layer with a thickness of 4nm in the active region of the NMOS device, with a doping concentration of 3×10 ¹⁸ cm ^-3 , The Ge composition is 20%, which is used as the second N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7f) Using chemical vapor deposition (CVD), at 700°C, selectively grow an N-type Si layer with a thickness of 300nm in the active region of the NMOS device, with a doping concentration of 8×10 ¹⁹ cm ^-3 , as NMOS device source area;

(7g) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

(7h) Lithograph the active region of the PMOS device, using the method of chemical vapor deposition (CVD), at 700°C, selectively grow an N-type relaxed Si layer in the deep groove of the active region of the PMOS device, the doping concentration is 1×10 ¹⁷ cm ^-3 , thickness 40nm;

(7i) Selectively grow an N-type strained SiGe layer with a doping concentration of 1×10 ¹⁷ cm ^-3 in the deep groove of the active region of the PMOS device at 700°C by chemical vapor deposition (CVD), The Ge component is 20%, and the thickness is 15nm;

(7j) Using chemical vapor deposition (CVD), at 700°C, selectively grow an intrinsically relaxed Si cap layer in the deep groove of the active region of the PMOS device, with a thickness of 4nm, to form an N well;

(7k) using wet etching to etch away the SiO ₂ layer on the surface.

Step 8, shallow trench isolation preparation.

(8a) Using chemical vapor deposition (CVD), at 600-800°C, grow a _SiO2 layer with a thickness of 240nm on the surface of the epitaxial Si layer;

(8b) Shallow trench isolation by photolithography, using dry etching process to etch a shallow trench with a depth of 400nm in the isolation area;

(8c) Filling the shallow groove with SiO ₂ at 700°C by chemical vapor deposition (CVD);

(8d) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

Step 9, drain connection preparation of the NMOS device.

(9a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 700°C by chemical vapor deposition (CVD) to form a barrier layer;

(9b) Lithographically etching the drain trench of the NMOS device, using a dry etching process to etch a drain trench with a depth of 0.5 μm;

(9c) Deposit a layer of SiO ₂ on the surface of the substrate at 700°C by chemical vapor deposition (CVD) to form NMOS device drain trench sidewall isolation, and dry-etch away the SiO ₂ on the surface, leaving SiO ₂ on the sidewall of the drain trench;

(9d) Deposit N-type Poly-Si with a doping concentration of 3×10 ²⁰ cm ^-3 on the substrate surface at 700°C by chemical vapor deposition (CVD) to fill the drain trench of the NMOS device ;

(9e) Using a chemical mechanical polishing (CMP) method to remove excess Poly-Si on the surface of the substrate to form a drain connection region of an NMOS device;

(9f) Use wet etching to etch away the SiO ₂ and SiN layers on the surface.

In step 10, an NMOS device is formed.

(10a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 700°C by chemical vapor deposition (CVD) to form a barrier layer again;

(10b) Lithographically etching the gate window of the NMOS device, using a dry etching process to etch a gate trench with a depth of 0.5 μm;

(10c) Deposit a layer of HfO ₂ with a thickness of 6 nm on the surface of the substrate at 350°C by atomic layer chemical vapor deposition (ALCVD) to form the gate dielectric layer of the NMOS device;

(10d) Deposit N-type Poly-Si with a doping concentration of 3×10 ²⁰ cm ^-3 on the substrate surface at 700°C by chemical vapor deposition (CVD) to fill the gate trenches of NMOS devices ;

(10e) Removing part of the Poly-Si and HfO ₂ layers on the surface of the gate trench of the NMOS device, forming the gate and source regions of the NMOS device, and finally forming the NMOS device;

(10f) Etch away the SiO ₂ and SiN layers on the surface by wet etching.

Step 11, preparing the dummy gate and source and drain of the PMOS device.

(11a) Deposit a layer of SiO ₂ on the surface of the active region of the NMOS device at 700°C by chemical vapor deposition (CVD);

(11b) Photoetching the active region of the PMOS device, using the chemical vapor deposition (CVD) method, at 700°C, depositing a layer of SiO ₂ with a thickness of 12nm on the surface of the substrate;

(11c) Deposit a layer of Poly-Si with a thickness of 240nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD);

(11d) Photoetching Poly-Si and SiO ₂ to form a virtual gate of a PMOS device;

(11e) Perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 3×10 ¹⁸ cm ^-3 ;

(11f) Deposit a layer of SiO ₂ with a thickness of 4nm on the substrate surface at 700°C by chemical vapor deposition (CVD), and dry-etch away the SiO ₂ on the substrate surface, leaving the Poly- SiO ₂ on the Si sidewall forms the gate electrode sidewall of the PMOS device;

(11g) P-type ion implantation is performed on the active region of the PMOS device, and the source and drain regions of the PMOS device are formed by self-alignment, so that the doping concentration of the source and drain regions reaches 8×10 ¹⁹ cm ^-3 .

Step 12, forming a PMOS device.

(12a) Using the chemical vapor deposition (CVD) method, at 700 ° C, deposit a _SiO2 layer on the surface of the substrate, use the chemical mechanical polishing (CMP) method to flatten the surface, and then use the dry etching process to etch the surface SiO2 ₂ to the upper surface of the dummy grid, exposing the dummy grid;

(12b) Wet etching the dummy gate to form a groove at the gate electrode;

(12c) Deposit a layer of SiON on the surface of the substrate at 700°C with a thickness of 3 nm by chemical vapor deposition (CVD);

(12d) Deposit the W-TiN composite gate by physical vapor deposition (PVD), and remove the surface metal by chemical mechanical polishing (CMP);

(12e) The W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP) to form the gate and finally form the PMOS device.

Step 13, forming a BiCMOS integrated circuit.

(13a) Deposit a _SiO2 layer on the substrate surface at 700°C by chemical vapor deposition (CVD);

(13b) Photolithographic lead holes;

(13c) Metallization;

(13d) Sputtering metal, photolithography leads, forming NMOS device drain metal leads, source metal leads and gate metal leads, PMOS device drain metal leads, source metal leads and gate metal leads, bipolar transistor emission Electrode metal leads, base metal leads, and collector metal leads form a strained SiGe back-channel BiCMOS integrated device and circuit with a 30nm conductive channel of the MOS device.

Embodiment 3: The preparation of the strained SiGe back channel BiCMOS integrated device and circuit with a conductive channel of 22nm, the specific steps are as follows:

Step 1, epitaxial growth.

(1a) Select an SOI substrate, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 150nm, and the upper layer is N-type Si with a doping concentration of 1×10 ¹⁶ cm ^-3 with a thickness of 100nm;

(1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 ¹⁶ cm ^-3 .

Step 2, deep trench isolation preparation.

(2a) Using chemical vapor deposition (CVD), at 600°C, grow a layer of SiO ₂ with a thickness of 300nm on the surface of the epitaxial Si layer;

(2b) Photoetched deep trench isolation regions;

(2c) Dry etching a deep trench with a depth of 3.5 μm in the deep trench isolation region;

(2d) Deposit SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition (CVD), and fill the deep groove;

(2e) Use chemical mechanical polishing (CMP) to remove excess oxide layer on the surface to form deep trench isolation.

Step 3, preparation of the collector contact area.

(3a) By chemical vapor deposition (CVD), at 600°C, a _SiO2 layer with a thickness of 200nm should be deposited on the surface of the epitaxial Si layer;

(3b) Photolithographic collector contact area window;

(3c) Phosphorus is implanted into the substrate so that the doping concentration of the collector contact region is 1×10 ¹⁹ cm ^-3 , forming a collector contact region;

(3d) Annealing the substrate at a temperature of 950° C. for 120 s to activate impurities.

Step 4, base contact preparation.

(4a) Etch the oxide layer on the surface of the substrate, and deposit a layer of SiO ₂ with a thickness of 20nm on the surface of the substrate at 600°C by chemical vapor deposition (CVD);

(4b) Deposit a P-type Poly-Si layer on the surface of the substrate at 600°C by chemical vapor deposition (CVD) as the base contact region. The layer thickness is 200nm and the doping concentration is 1 ×10 ²⁰ cm ^-3 ;

(4c) Photoetching Poly-Si to form an extrinsic base region, deposit a SiO ₂ layer on the substrate surface at 600°C with a thickness of 200nm, and remove SiO ₂ on the Poly-Si surface by chemical mechanical polishing (CMP);

(4d) Depositing a SiN layer on the surface of the substrate at 600° C. with a thickness of 50 nm by chemical vapor deposition (CVD);

(4e) Photolithography of the emission region window, etching away the SiN layer and Poly-Si layer in the emission region window;

(4f) Deposit a layer of SiN on the surface of the substrate at 600° C. with a thickness of 10 nm by chemical vapor deposition (CVD).

Step 5, base material preparation.

(5a) using a dry method to etch away the emission window SiN to form side walls;

(5b) Using wet etching, the _SiO2 layer in the window is over-etched to form a base region;

(5c) Using the chemical vapor deposition (CVD) method, at 600°C, selectively grow a SiGe base region in the base region, with a Ge composition of 15%, a doping concentration of 5×10 ¹⁸ cm ^-3 , and a thickness of 20nm.

Step 6, preparation of the emission area.

(6a) Photoetching the collector window, using the chemical vapor deposition (CVD) method, depositing Poly-Si on the surface of the substrate at 600°C with a thickness of 200nm;

(6b) Perform phosphorus implantation on the substrate, and use chemical mechanical polishing (CMP) to remove Poly-Si on the surface outside the emitter and collector regions to form emitters and collectors;

(6c) Deposit a _SiO2 layer on the substrate surface at 600°C by chemical vapor deposition (CVD);

(6d) Lithograph the collector, and perform phosphorus implantation again in this area to increase the doping concentration of Poly-Si in the collector to 1×10 ¹⁹ cm ^-3 , and finally remove the SiO ₂ layer on the surface;

(6e) Deposit a SiO ₂ layer on the substrate surface at 600°C by chemical vapor deposition (CVD), and anneal at 950°C for 120s to activate impurities.

Step 7, preparation of epitaxial materials for NMOS and PMOS devices.

(7a) Photoetching the active area of the NMOS device, using a dry etching process to etch a deep groove with a depth of 1.5 μm in the active area of the NMOS device;

(7b) Using chemical vapor deposition (CVD), at 750°C, selectively grow an N-type Si epitaxial layer with a thickness of 1.3 μm in the active region of the NMOS device, with a doping concentration of 1×10 ²⁰ cm ^-3 , as the drain region of the NMOS device;

(7c) Using chemical vapor deposition (CVD), at 750°C, selectively grow an N-type strained SiGe layer with a thickness of 3nm in the active region of the NMOS device, with a doping concentration of 1×10 ¹⁸ cm ^-3 , The Ge composition is 10%, which is used as the first N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7d) Using chemical vapor deposition (CVD), at 750°C, selectively grow a P-type strained SiGe layer with a thickness of 22nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , The Ge composition has a gradient distribution, the lower layer is 10%, and the upper layer is 25%, which is used as the channel region of the NMOS device;

(7e) Using chemical vapor deposition (CVD), at 750°C, selectively grow an N-type strained SiGe layer with a thickness of 3nm in the active region of the NMOS device, with a doping concentration of 1×10 ¹⁸ cm ^-3 , The Ge composition is 25%, which is used as the second N-type lightly doped source-drain structure (N-LDD) layer of the NMOS device;

(7f) Using chemical vapor deposition (CVD), at 750°C, selectively grow an N-type Si layer with a thickness of 200nm in the active region of the NMOS device, with a doping concentration of 1×10 ²⁰ cm ^-3 , as NMOS device source area;

(7g) Deposit a layer of SiO ₂ on the surface of the substrate at 780°C by chemical vapor deposition (CVD);

(7h) Lithograph the active region of the PMOS device, using the chemical vapor deposition (CVD) method, at 750°C, selectively grow an N-type relaxed Si layer in the deep groove of the active region of the PMOS device, the doping concentration 5×10 ¹⁷ cm ^-3 , thickness 30nm;

(7i) Selectively grow an N-type strained SiGe layer with a doping concentration of 5×10 ¹⁷ cm ^-3 in the deep groove of the active region of the PMOS device at 750°C by chemical vapor deposition (CVD), The Ge component is 30%, and the thickness is 10nm;

(7j) Using chemical vapor deposition (CVD), at 750°C, selectively grow an intrinsically relaxed Si cap layer in the deep groove of the active region of the PMOS device, with a thickness of 3nm, to form an N well;

(7k) using wet etching to etch away the SiO ₂ layer on the surface.

Step 8, shallow trench isolation preparation.

(8a) Using chemical vapor deposition (CVD), at 600°C, grow a layer of SiO ₂ with a thickness of 200nm on the surface of the epitaxial Si layer;

(8b) Shallow groove isolation by photolithography, using dry etching process to etch a shallow groove with a depth of 300nm in the isolation area;

(8c) Filling the shallow groove with SiO ₂ at 600°C by chemical vapor deposition (CVD);

(8d) Use chemical mechanical polishing (CMP) to remove excess oxide layer and form shallow trench isolation.

Step 9, drain connection preparation of the NMOS device.

(9a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 780°C by chemical vapor deposition (CVD) to form a barrier layer;

(9b) Lithographically etching the drain trench of the NMOS device, using a dry etching process to etch a drain trench with a depth of 0.4 μm;

(9c) Deposit a layer of SiO ₂ on the surface of the substrate at 780°C by chemical vapor deposition (CVD) to form NMOS device drain trench sidewall isolation, and dry-etch away the SiO ₂ on the surface, leaving SiO ₂ on the sidewall of the drain trench;

(9d) Deposit N-type Poly-Si with a doping concentration of 5×10 ²⁰ cm ^-3 on the substrate surface at 780°C by chemical vapor deposition (CVD) to fill the drain trench of the NMOS device ;

(9e) Using a chemical mechanical polishing (CMP) method to remove excess Poly-Si on the surface of the substrate to form a drain connection region of an NMOS device;

(9f) Use wet etching to etch away the SiO ₂ and SiN layers on the surface.

In step 10, an NMOS device is formed.

(10a) Deposit a layer of SiO ₂ and a layer of SiN on the surface of the active region of the NMOS device at 780°C by chemical vapor deposition (CVD) to form a barrier layer again;

(10b) Lithographically etching the gate window of the NMOS device, using a dry etching process to etch a gate trench with a depth of 0.4 μm;

(10c) Deposit a layer of HfO ₂ with a thickness of 8nm on the surface of the substrate at 400°C by atomic layer chemical vapor deposition (ALCVD) to form the gate dielectric layer of the NMOS device;

(10d) Deposit N-type Poly-Si with a doping concentration of 5×10 ²⁰ cm ^-3 on the substrate surface at 780°C by chemical vapor deposition (CVD) to fill the gate trench of the NMOS device ;

(10e) Removing part of the Poly-Si and HfO ₂ layers on the surface of the gate trench of the NMOS device, forming the gate and source regions of the NMOS device, and finally forming the NMOS device;

(10f) Etch away the SiO ₂ and SiN layers on the surface by wet etching.

Step 11, preparing the dummy gate and source and drain of the PMOS device.

(11a) Deposit a layer of SiO ₂ on the surface of the active region of the NMOS device at 780°C by chemical vapor deposition (CVD);

(11b) Photoetching the active region of the PMOS device, using chemical vapor deposition (CVD) method, at 780°C, depositing a layer of SiO ₂ with a thickness of 15nm on the surface of the substrate;

(11c) Deposit a layer of Poly-Si with a thickness of 300nm on the surface of the substrate at 780°C by chemical vapor deposition (CVD);

(11d) Photoetching Poly-Si and SiO ₂ to form a virtual gate of a PMOS device;

(11e) Perform P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure (P-LDD) with a doping concentration of 5×10 ¹⁸ cm ^-3 ;

(11f) Deposit a layer of SiO ₂ with a thickness of 3nm on the substrate surface at 780°C by chemical vapor deposition (CVD), and dry-etch away the SiO ₂ on the substrate surface, leaving the Poly- SiO ₂ on the Si sidewall forms the gate electrode sidewall of the PMOS device;

(11g) P-type ion implantation is performed on the active region of the PMOS device, and the source and drain regions of the PMOS device are self-aligned, so that the doping concentration of the source and drain regions reaches 1×10 ²⁰ cm ^-3 .

Step 12, forming a PMOS device.

(12a) Using the chemical vapor deposition (CVD) method, at 780 ° C, deposit a _SiO2 layer on the substrate surface, use the chemical mechanical polishing (CMP) method to flatten the surface, and then etch the surface SiO2 using a dry etching process ₂ to the upper surface of the dummy grid, exposing the dummy grid;

(12b) Wet etching the dummy gate to form a groove at the gate electrode;

(12c) Deposit a layer of SiON on the surface of the substrate at 780°C with a thickness of 1.5 nm by chemical vapor deposition (CVD);

(12d) Deposit the W-TiN composite gate by physical vapor deposition (PVD), and remove the surface metal by chemical mechanical polishing (CMP);

(12e) The W-TiN composite gate is used as the stop layer of chemical mechanical polishing (CMP) to form the gate and finally form the PMOS device.

Step 13, forming a BiCMOS integrated circuit.

(13a) Deposit a _SiO2 layer on the substrate surface at 780°C by chemical vapor deposition (CVD);

(13b) Photolithographic lead holes;

(13c) Metallization;

(13d) Sputtering metal, photolithography leads, forming NMOS device drain metal leads, source metal leads and gate metal leads, PMOS device drain metal leads, source metal leads and gate metal leads, bipolar transistor emission Electrode metal leads, base metal leads, and collector metal leads constitute a strained SiGe back-channel BiCMOS integrated device circuit with a 22nm conductive channel of the MOS device.

The strained SiGe back channel BiCMOS integrated device and the preparation method provided by the embodiments of the present invention have the following advantages:

1. In the strained SiGe back channel BiCMOS integrated device prepared by the present invention, the anisotropic characteristics of strained SiGe material stress are fully utilized, and compressive strain is introduced in the horizontal direction to improve the hole mobility of the PMOS device; tension is introduced in the vertical direction. Strain improves the electron mobility of the NMOS device, so the performance of the device such as frequency and current drive capability is higher than that of the relaxed Si CMOS device of the same size;

2. In the process of preparing strained SiGe back channel BiCMOS integrated devices, the invention adopts selective epitaxy technology to selectively grow strained SiGe materials in the active regions of NMOS devices and PMOS devices respectively, which improves the flexibility of device design and enhances CMOS Electrical performance of devices and integrated circuits;

3. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the channel direction of the NMOS device is the vertical direction, and the channel is a strained SiGe layer prepared by chemical vapor deposition (CVD), and the thickness of the SiGe layer is The channel length of the NMOS device, therefore, avoids the photolithography of the small-sized gate in the preparation of the NMOS device, reduces the complexity of the process, and reduces the cost;

4. The channel of the NMOS device in the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention is a back type, that is, a gate can control the channels on four sides in the trench, so the device increases the channel in a limited area. The width of the track improves the current driving capability of the device, increases the integration level of the integrated circuit, and reduces the manufacturing cost per unit area of the integrated circuit;

5. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the Ge composition of the channel of the NMOS device has a gradient change, so a self-built electric field that accelerates electron transport can be generated in the direction of the channel, and the current carrying capacity of the channel is enhanced. Sub-transport capability, thereby improving the frequency characteristics and current drive capability of strained SiGe NMOS devices;

6. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the NMOS device adopts _HfO2 with a high K value as the gate dielectric, which improves the gate control capability of the NMOS device and enhances the electrical performance of the NMOS device;

7. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the PMOS device is a quantum well device, that is, the strained SiGe channel layer is between the Si cap layer and the bulk Si layer. Compared with the surface channel device, the device can Effectively reduce channel interface scattering and improve device electrical characteristics; at the same time, quantum wells can improve the problem of hot electron injection into the gate dielectric, increasing the reliability of devices and circuits;

8. In the strained SiGe back channel BiCMOS integrated device structure prepared by the present invention, the PMOS device adopts SiON instead of traditional pure _SiO as the gate dielectric, which not only enhances the reliability of the device, but also utilizes the change of the dielectric constant of the gate dielectric to improve the The gate control capability of the device;

9. The highest temperature involved in the process of preparing the strained SiGe channel BiCMOS in the present invention is 800°C, which is lower than the process temperature that causes the stress relaxation of the strained SiGe channel, so the preparation method can effectively maintain the stress of the strained SiGe channel and improve performance of integrated circuits;

10. In the process of preparing the strained SiGe back channel BiCMOS integrated device of the present invention, the PMOS device adopts the metal gate damascene process (damascene process) to prepare the gate electrode, and the gate electrode is a metal W-TiN composite structure, due to the underlying TiN and strained Si and The work function difference of the strained SiGe material is small, which improves the electrical characteristics of the device, and the W on the upper layer can reduce the resistance of the gate electrode, realizing the optimization of the gate electrode;

11. The strained SiGe back channel BiCMOS integrated device prepared by the present invention adopts a fully self-aligned process during the preparation process, which effectively reduces the parasitic resistance and capacitance, and improves the current and frequency characteristics of the device;

12. The emitter, base and collector of the SiGe HBT device in the strained SiGe back-channel BiCMOS integrated device prepared by the present invention are all polycrystalline, and the polycrystalline can be partially fabricated on the oxide layer, reducing the active area of the device area, thereby reducing the size of the device and improving the integration of the circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (5)

1. a preparation method of a strained SiGe back type channel BiCMOS integrated device, is characterized in that, comprises the steps: The first step is to select an SOI substrate with an oxide layer thickness of 150-400nm, an upper Si thickness of 100-150nm, and an N-type doping concentration of 1×10 ¹⁶ to 1×10 ¹⁷ cm ^-3 ; The second step is to use the method of chemical vapor deposition to grow an N-type Si epitaxial layer with a thickness of 50-100 nm on the substrate at 600-750 ° C, as the collector region, and the doping concentration of this layer is 1× 10 ¹⁶ ～1×10 ¹⁷ cm ^-3 ; The third step is to use the method of chemical vapor deposition to grow a layer of SiO ₂ with a thickness of 300-500nm on the surface of the epitaxial Si layer at 600-800°C, and to etch the deep trench isolation by photolithography. Etch a deep groove with a depth of 2.5-3.5μm, and then use the chemical vapor deposition method to fill the deep groove with SiO ₂ at 600-800°C; finally, use chemical mechanical polishing to remove the excess oxide layer on the surface to form deep trench isolation; The fourth step is to deposit a layer of _SiO2 with a thickness of 200-300nm on the surface of the epitaxial Si layer at 600-800°C by chemical vapor deposition, and photolithographically open the contact area of the collector to phosphorize the substrate. Implantation, so that the doping concentration of the collector contact area is 1×10 ¹⁹ ~ 1×10 ²⁰ cm ^-3 to form a collector contact area, and then the substrate is annealed at a temperature of 950~1100°C for 15~120s to activate the impurity ; The fifth step is to etch off the oxide layer on the surface of the substrate, and use chemical vapor deposition method to deposit two layers of materials on the surface of the substrate at 600-800°C: the first layer is a _SiO2 layer with a thickness of 20-40nm ; The second layer is a P-type polysilicon layer with a thickness of 200-400nm and a doping concentration of 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ; The sixth step is to photolithographically polysilicon to form an outer base region, and use chemical vapor deposition to deposit a _SiO2 layer on the surface of the substrate at 600-800°C with a thickness of 200-400nm, and remove the polysilicon by chemical mechanical polishing Surface SiO ₂ ; The seventh step is to deposit a SiN layer with a thickness of 50-100nm at 600-800°C by chemical vapor deposition method, and photolithographically etch the SiN layer and polysilicon layer in the window of the emission region; Then use the chemical vapor deposition method to deposit a layer of SiN on the surface of the substrate at 600-800°C, with a thickness of 10-20nm, and dry-etch the emission window SiN to form side walls; The eighth step is to use wet etching to over-etch the _SiO2 layer in the window to form a base area, and use chemical vapor deposition method to selectively grow a SiGe base area in the base area at 600-750 °C, Ge The composition is 15-25%, the doping concentration is 5×10 ¹⁸ ～5×10 ¹⁹ cm ^-3 , and the thickness is 20-60nm; Step 9: Lithograph the collector window, use chemical vapor deposition method, deposit polysilicon on the surface of the substrate at 600-800°C with a thickness of 200-400nm, then implant phosphorus into the substrate, and use chemical mechanical polishing Remove the polysilicon on the surface outside the emitter and collector regions to form the emitter and collector; The tenth step, using the chemical vapor deposition method, at 600-800 ° C, deposit a _SiO2 layer on the surface of the substrate, photolithography the collector, and perform phosphorus implantation on the contact hole to increase the doping of polysilicon in the collector concentration to reach 1×10 ¹⁹ ～1×10 ²⁰ cm ^-3 , and finally remove the SiO ₂ layer on the surface; Step 11: Deposit a _SiO2 layer on the surface of the substrate at 600-800°C by chemical vapor deposition, and anneal at 950-1100°C for 15-120s to activate impurities; The twelfth step, photoetching the active area of the NMOS device, using a dry etching process, etch a deep groove with a depth of 1.5-2.0 μm in the active area of the NMOS device, and using the method of chemical vapor deposition, at 600-2.0 μm 750°C, five layers of materials are continuously grown in deep grooves: the first layer is an N-type Si epitaxial layer with a thickness of 1.3-1.6 μm, and a doping concentration of 5×10 ¹⁹ to 1×10 ²⁰ cm ^-3 , used as an NMOS device Drain region; the second layer is an N-type strained SiGe layer with a thickness of 3-5nm, a doping concentration of 1-5×10 ¹⁸ cm ^-3 , and a Ge composition of 10%, as the first N-type lightly doped SiGe layer of an NMOS device. Impurity source-drain structure layer; the third layer is a P-type strained SiGe layer with a thickness of 22-45nm, doping concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 , the Ge composition is a gradient distribution, and the lower layer is 10% , the upper layer has a gradient distribution of 20-30%, which is used as the channel region of NMOS devices; the fourth layer is an N-type strained SiGe layer with a thickness of 3-5nm, and a doping concentration of 1-5×10 ¹⁸ cm ^-3 , Ge group Divided into 20-30%, as the second N-type lightly doped source-drain structure layer of NMOS devices; the fifth layer is an N-type Si layer with a thickness of 200-400nm, and a doping concentration of 5×10 ¹⁹ to 1× 10 ²⁰ cm ^-3 , as the source region of the NMOS device; Step 13: Deposit a layer of SiO ₂ on the surface of the substrate at 600-780°C by chemical vapor deposition, and photolithography the active area of the PMOS device. ℃, selectively epitaxially grow a layer of N-type relaxed Si layer in the deep groove, the doping concentration is 5×10 ¹⁶ ～5×10 ¹⁷ cm ^-3 , and the thickness is 30-50 μm, and then grow an N-type strained SiGe layer , the doping concentration is 5×10 ¹⁶ ~5×10 ¹⁷ cm ^-3 , the Ge composition is 10~30%, the thickness is 10~20nm, and finally an intrinsically relaxed Si cap layer is grown with a thickness of 3~5nm. Fill the trench to form the active area of the PMOS device; use wet etching to etch away the SiO ₂ layer on the surface; The fourteenth step, using the chemical vapor deposition method, at 600-800 ° C, grow a layer of SiO ₂ layer with a thickness of 200-300 nm on the surface of the epitaxial Si layer, photolithography shallow trench isolation, dry method in the shallow trench isolation area Etch a shallow groove with a depth of 300-500nm, and then use chemical vapor deposition to fill the shallow groove with SiO ₂ at 600-800°C; finally, use chemical mechanical polishing to remove the excess oxide layer on the surface to form shallow trench isolation; Step 15: Deposit a layer of SiO ₂ and a layer of SiN on the surface of the substrate at 600-780°C by chemical vapor deposition to form a barrier layer; photolithographically etch the drain trench of the NMOS device and use dry etching process, etch a drain trench with a depth of 0.4-0.6 μm; use chemical vapor deposition method, at 600-780 ° C, deposit a layer of SiO ₂ on the surface of the substrate to form NMOS device drain trench sidewall isolation, Dry etch away the SiO ₂ on the surface, retain the SiO ₂ on the sidewall of the drain trench, and deposit N with a doping concentration of 1-5×10 ²⁰ cm ^-3 at 600-780°C by chemical vapor deposition Type polysilicon, fill the groove, and remove excess polysilicon on the surface of the substrate by chemical mechanical polishing to form the drain connection area of the NMOS device; use wet etching to etch off the surface layers SiO ₂ and SiN; Step 16: Deposit a layer of SiO ₂ and a layer of SiN on the surface of the substrate at 600-780°C by chemical vapor deposition to form a barrier layer again; photolithographically etch the gate window of the NMOS device and use dry etching process, etch a gate trench with a depth of 0.4-0.6 μm; use atomic layer chemical vapor deposition method, at 300-400 ° C, deposit a layer of HfO ₂ with a thickness of 5-8 nm on the substrate surface to form NMOS The device gate dielectric layer, and then use the chemical vapor deposition method to deposit N-type polysilicon with a doping concentration of 1-5×10 ²⁰ cm ^-3 on the substrate surface at 600-780 ° C to fill the gate trench of the NMOS device Then remove the polysilicon and HfO ₂ on the surface outside the gate trench of the NMOS device to form the gate and source regions of the NMOS device, and finally form the NMOS device; use wet etching to etch away the SiO ₂ and SiN layers on the surface; Step 17: Deposit a layer of SiO ₂ on the surface of the substrate at 600-780°C by chemical vapor deposition method, and photolithography the active area of the PMOS device, at 600-780°C by chemical vapor deposition method Deposit a layer of SiO ₂ with a thickness of 10-15nm and a layer of polysilicon with a thickness of 200-300nm on the surface of the substrate, photolithographically polysilicon and SiO ₂ to form a virtual gate of a PMOS device; perform P-type ion implantation on a PMOS device to form P-type lightly doped source-drain structure with a doping concentration of 1-5×10 ¹⁸ cm ^-3 ; Step 18: Deposit a layer of SiO _{2 with a thickness of 3-5 nm on the surface of the substrate at 600-780°C by chemical vapor deposition, etch away the SiO 2 on} the surface of the substrate by dry method, leaving SiO ₂ on the sidewall of Ploy-Si forms the sidewall of the gate electrode of the PMOS device; then performs P-type ion implantation on the active region of the PMOS device, and self-aligns to generate the source region and drain region of the PMOS device, so that the doping concentration of the source and drain regions Reach 5×10 ¹⁹ ～1×10 ²⁰ cm ^-3 ; The nineteenth step, use chemical vapor deposition method, at 600 ~ 780 ℃, deposit SiO ₂ layer on the substrate surface, use chemical mechanical polishing method to smooth the surface, and then use dry etching process to etch the surface SiO ₂ to the void The upper surface of the gate is exposed to the dummy gate; the dummy gate is wet-etched to form a groove at the gate electrode; a layer of SiON is deposited on the surface of the substrate at 600-780°C by chemical vapor deposition with a thickness of 1.5 ~5nm; use physical vapor deposition to deposit W-TiN composite gate, use chemical mechanical polishing to remove the surface metal, use W-TiN composite gate as the stop layer of chemical mechanical polishing to form the gate, and finally form a PMOS device; The twentieth step, use chemical vapor deposition method, at 600 ~ 780 ℃, deposit SiO ₂ layer on the surface of the substrate, photolithography lead hole, metallization, sputtering metal, photolithography lead, to form the conductive channel of MOS device It is a 22-45nm strained SiGe back channel BiCMOS integrated device. 2. The method according to claim 1, wherein the channel length of the NMOS device is determined according to the thickness of the P-type strained SiGe layer deposited in the twelfth step, and is 22-45 nm. 3. The preparation method according to claim 1, wherein the chemical vapor deposition process involved in the preparation method is determined by the temperature, and the maximum temperature is less than or equal to 800°C. 4. The preparation method according to claim 1, wherein the thickness of the base region is determined according to the thickness of the epitaxial layer of SiGe in the eighth step, and is 20-60 nm. 5. a preparation method of a strained SiGe back type channel BiCMOS integrated circuit, is characterized in that, comprises the steps: Step 1, the implementation method of epitaxial growth is: (1a) Select an SOI substrate, the lower support material of the substrate is Si, the middle layer is SiO ₂ with a thickness of 400nm, and the upper layer material is N-type Si with a doping concentration of 1×10 ¹⁷ cm ^-3 , with a thickness of 150nm; (1b) Using the chemical vapor deposition chemical vapor deposition method, at 750°C, grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper Si material, as the collector region, and the doping concentration of this layer is 1× 10 ¹⁷ cm ^-3 ; Step 2, the implementation method of deep groove isolation preparation is: (2a) Utilize the method for chemical vapor deposition, at 800 ℃, grow one layer of thickness on the surface of epitaxial Si layer and be the _SiO2 layer of 500nm; (2b) Photoetched deep trench isolation regions; (2c) Dry etching a deep trench with a depth of 2.5 μm in the deep trench isolation region; (2d) Deposit SiO ₂ on the substrate surface at 800°C by chemical vapor deposition method, and fill the deep groove; (2e) Use chemical mechanical polishing to remove excess oxide layer on the surface to form deep groove isolation; Step 3, the realization method of the preparation of the collector contact area is as follows: (3a) Utilize the method of chemical vapor deposition, at 800 ℃, on the surface of epitaxial Si layer, should deposit one layer of thickness to be the _SiO2 layer of 300nm; (3b) photolithographic collector contact area window; (3c) Phosphorus is implanted into the substrate so that the doping concentration of the collector contact region is 1×10 ²⁰ cm ^-3 , forming a collector contact region; (3d) annealing the substrate at a temperature of 1100°C for 15s to activate impurities; Step 4, the implementation method of base contact preparation is: (4a) Etch the oxide layer on the surface of the substrate, and deposit a _SiO2 layer with a thickness of 40nm on the surface of the substrate at 800°C by chemical vapor deposition; (4b) Deposit a P-type Poly-Si layer on the surface of the substrate at 800°C by chemical vapor deposition as the base contact region. The layer thickness is 400nm and the doping concentration is 1×10 ²¹ cm ^-3 ; (4c) Photoetching Poly-Si to form an extrinsic base region, depositing a SiO ₂ layer on the substrate surface at 800° C. with a thickness of 400 nm, and removing SiO ₂ on the Poly-Si surface by chemical mechanical polishing; (4d) Depositing a SiN layer on the surface of the substrate at 800° C. with a thickness of 100 nm by chemical vapor deposition; (4e) photolithography of the emission region window, etching away the SiN layer and the Poly-Si layer in the emission region window; (4f) Depositing a layer of SiN on the surface of the substrate at 800° C. with a thickness of 20 nm by chemical vapor deposition; Step 5, the implementation method of base area material preparation is: (5a) using a dry method to etch away the emission window SiN to form side walls; (5b) using wet etching to over-etch the _SiO2 layer in the window to form a base region; (5c) using a chemical vapor deposition method, at 750°C, selectively grow a SiGe base region in the base region, with a Ge composition of 25%, a doping concentration of 5×10 ¹⁹ cm ^-3 , and a thickness of 60 nm; Step 6, the implementation method of the emission area preparation is: (6a) photoetching the collector window, using a chemical vapor deposition method, at 800 ° C, depositing Poly-Si on the surface of the substrate with a thickness of 400 nm; (6b) Perform phosphorous implantation on the substrate, and use chemical mechanical polishing to remove the Poly-Si on the surface outside the emitter and collector regions to form the emitter and collector; (6c) Deposit a _SiO2 layer on the surface of the substrate at 800° C. by chemical vapor deposition; (6d) Lithograph the collector, and perform phosphorus implantation again in this area to increase the doping concentration of Poly-Si in the collector to 1×10 ²⁰ cm ^-3 , and finally remove the SiO ₂ layer on the surface; (6e) Deposit a _SiO2 layer on the surface of the substrate at 800°C by chemical vapor deposition, and anneal at 1100°C for 15s to activate the impurities; Step 7, the implementation method of preparing the active regions of NMOS and PMOS devices is as follows: (7a) Photoetching the active area of the NMOS device, using a dry etching process, etching a deep groove with a depth of 2 μm in the active area of the NMOS device; (7b) Using chemical vapor deposition, at 600°C, selectively grow an N-type Si epitaxial layer with a thickness of 1.6 μm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁹ cm ^-3 , as an NMOS device drain area; (7c) Using chemical vapor deposition, at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , and a Ge composition of 10%, as the first N-type lightly doped source-drain structure layer of NMOS devices; (7d) Using chemical vapor deposition, at 600°C, selectively grow a P-type strained SiGe layer with a thickness of 45nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 , and a Ge composition of Gradient distribution, the lower layer is 10%, and the upper layer is 30%, which is used as the channel region of the NMOS device; (7e) Using chemical vapor deposition, at 600°C, selectively grow an N-type strained SiGe layer with a thickness of 5nm in the active region of the NMOS device, with a doping concentration of 5×10 ¹⁷ cm ^-3 , and a Ge composition of 30%, as the second N-type lightly doped source-drain structure layer of the NMOS device; (7f) Selectively grow an N-type Si layer with a thickness of 400nm in the active region of the NMOS device at 600°C by chemical vapor deposition with a doping concentration of 5×10 ¹⁹ cm ^-3 as the source region of the NMOS device ; (7g) Deposit a layer of SiO ₂ on the surface of the substrate at 600°C by chemical vapor deposition; (7h) Lithograph the active region of the PMOS device, using the method of chemical vapor deposition, at 600°C, selectively grow an N-type relaxed Si layer in the deep groove of the active region of the PMOS device, with a doping concentration of 5×10 ¹⁶ cm ^-3 , the thickness is 50nm; (7i) Selectively grow an N-type strained SiGe layer in the deep trench in the active region of the PMOS device at 600°C by chemical vapor deposition, with a doping concentration of 5×10 ¹⁶ cm ^-3 and a Ge composition of 10%, with a thickness of 20nm; (7j) Using chemical vapor deposition, at 600°C, selectively grow an intrinsically relaxed Si cap layer in the deep groove of the active region of the PMOS device, with a thickness of 5nm, to form an N well; (7k) using wet etching to etch away the layer SiO ₂ on the surface; Step 8, the implementation method of shallow groove isolation preparation is: (8a) using chemical vapor deposition, at 600-800°C, growing a _SiO2 layer with a thickness of 300nm on the surface of the epitaxial Si layer; (8b) Photolithographic shallow groove isolation, using a dry etching process to etch a shallow groove with a depth of 500nm in the isolation region; (8c) Filling the shallow groove with SiO ₂ at 800°C by chemical vapor deposition; (8d) Using chemical mechanical polishing to remove excess oxide layer to form shallow trench isolation; Step 9, the realization method of NMOS device drain connection preparation is as follows: (9a) Deposit a layer of _SiO2 and a layer of SiN on the surface of the active region of the NMOS device at 800°C by chemical vapor deposition to form a barrier layer; (9b) Lithographically etching the drain trench of the NMOS device, using a dry etching process to etch a drain trench with a depth of 0.6 μm; (9c) Deposit a layer of SiO ₂ on the surface of the substrate at 800°C by chemical vapor deposition to form the sidewall isolation of the drain trench of the NMOS device, and dry-etch away the SiO ₂ on the surface, leaving the side of the drain trench wall SiO ₂ ; (9d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the surface of the substrate at 800°C by chemical vapor deposition to fill the drain trench of the NMOS device; (9e) using a chemical mechanical polishing method to remove excess Poly-Si on the surface of the substrate to form a drain connection region of an NMOS device; (9f) Utilize wet etching, etch away the layer SiO ₂ and SiN on the surface; Step 10, the implementation method of NMOS device formation is: (10a) Deposit a layer of _SiO2 and a layer of SiN on the surface of the active region of the NMOS device at 600°C by chemical vapor deposition to form a barrier layer again; (10b) Lithographically etching the gate window of the NMOS device, using a dry etching process to etch a gate trench with a depth of 0.6 μm; (10c) Depositing a layer of HfO ₂ with a thickness of 5 nm on the surface of the substrate at 300° C. by atomic layer chemical vapor deposition to form a gate dielectric layer for NMOS devices; (10d) Deposit N-type Poly-Si with a doping concentration of 1×10 ²⁰ cm ^-3 on the surface of the substrate at 600° C. by chemical vapor deposition to fill the gate trench of the NMOS device; (10e) removing part of the Poly _- Si and HfO layers on the surface of the gate trench of the NMOS device, forming the gate and source regions of the NMOS device, and finally forming the NMOS device; (10f) utilizing wet etching to etch away the _SiO2 and SiN layers on the surface; Step 11, the implementation method of preparing the virtual gate and source and drain of the PMOS device is as follows: (11a) Deposit a layer of SiO ₂ on the surface of the active region of the NMOS device at 600° C. by chemical vapor deposition; (11b) Photoetching the active region of the PMOS device, using a chemical vapor deposition method, at 600 ° C, depositing a layer of SiO ₂ with a thickness of 10 nm on the surface of the substrate; (11c) Deposit a layer of Poly-Si with a thickness of 200 nm on the surface of the substrate at 600° C. by chemical vapor deposition; (11d) photoetching Poly-Si and SiO ₂ to form a dummy gate of a PMOS device; (11e) performing P-type ion implantation on the PMOS device to form a P-type lightly doped source-drain structure with a doping concentration of 1×10 ¹⁸ cm ^-3 ; (11f) Deposit a layer of SiO ₂ with a thickness of 3nm on the substrate surface at 600°C by chemical vapor deposition method, dry-etch away the SiO ₂ on the substrate surface, and keep the sidewall of Poly-Si SiO ₂ , forming the sidewall of the gate electrode of the PMOS device; (11g) P-type ion implantation is performed on the active region of the PMOS device, and the source region and the drain region of the PMOS device are generated by self-alignment, so that the doping concentration of the source and drain regions reaches 5×10 ¹⁹ cm ^-3 ; Step 12, the implementation method of PMOS device formation is: (12a) Deposit a _SiO2 layer on the surface of the substrate at 600°C by chemical vapor deposition, level the surface by chemical mechanical polishing, etch the surface _SiO2 to the upper surface of the dummy gate by a dry etching process, exposed dummy gate; (12b) Wet etching the dummy gate to form a groove at the gate electrode; (12c) Deposit a layer of SiON on the surface of the substrate at 600° C. with a thickness of 5 nm by chemical vapor deposition; (12d) Deposit the W-TiN composite gate by physical vapor deposition, and remove the surface metal by chemical mechanical polishing; (12e) using the W-TiN composite gate as a stop layer for chemical mechanical polishing, thereby forming a gate, and finally forming a PMOS device; Step 13, the implementation method of forming a BiCMOS integrated circuit is: (13a) Depositing a SiO layer _on the surface of the substrate at 600° C. by chemical vapor deposition; (13b) Photolithographic lead holes; (13c) Metallization; (13d) sputtering metal, lithography leads, forming NMOS device drain metal leads, source metal leads and gate metal leads, PMOS device drain metal leads, source metal leads and gate metal leads, bipolar transistor emission Electrode metal leads, base metal leads, and collector metal leads form a strained SiGe back-channel BiCMOS integrated device and circuit with a 45nm conductive channel of the MOS device.