CN102751280A - Strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method thereof - Google Patents
Strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a strain SiGe square-in-square type channel BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a preparation method thereof. The preparation method comprises the steps of: growing an N type epitaxial layer on an SOI (Silicon On Insulator) substrate to be used as a bipolar device collector region, preparing a deep channel for isolation, then sequentially preparing a base electrode polycrystalline, a base region, an emitter region and a collector electrode to form a SiGe HBT (Heterojunction Bipolar Transistor) device; growing five layers of materials in a substrate NMOS (N-channel Metal Oxide Semiconductor) device active region, preparing a drain electrode, a grid electrode and an active region to process an NMOS device; growing three layers of materials in a PMOS (P-channel Metal Oxide Semiconductor) device active region, preparing a virtual grid electrode, carrying out injection by using an automatic alignment process to form PMOS device source region and drain region; etching the virtual grid electrode to prepare a PMOS device, and forming the strain SiGe square-in-square type channel BiCMOS integrated device and a circuit. According to the invention, in a preparation process, by adopting the fully-automatic alignment process, parasitic resistance and capacitance are effectively reduced, current and frequency characteristics of the device are improved; and an emitter electrode, a base electrode and a collector electrode of a SiGe HBT (Heterojunction Bipolar Transistor) are all made of polycrystalline, thus the area of a device active region and the size of the device are reduced, and the integration of the circuit is increased.
Description
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of strain SiGe and return type raceway groove BiCMOS integrated device and preparation method.
Background technology
Semiconductor integrated circuit is the basis of electronics industry, and people impel the development in this field very rapid to the great demand of electronics industry.In decades in the past, the fast development of electronics industry has produced tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very big share, the output value has surpassed 10,000 hundred million dollars in the world market.
Si CMOS integrated circuit has advantages such as low-power consumption, high integration, low noise and high reliability, in the semiconductor integrated circuit industry, has occupied ascendancy.Yet increase along with the reducing of the further increase of integrated circuit scale, device feature size, integrated level and complexity; Especially device feature size gets into after the nanoscale; The material of Si cmos device, the limitation of physical features have progressively manifested to come out, and have limited further developing of Si integrated circuit and manufacturing process thereof.Although microelectronics has obtained remarkable progress in research aspect compound semiconductor and other new material and the application in some field, far do not possess the condition that substitutes silica-based technology.And based on the science and technology development rule, a kind of new technology main force's technology from be born to becoming generally needs the time in twenty or thirty year.So in order to satisfy the needs that traditional performance improves, the performance that strengthens SiCMOS is considered to the developing direction of microelectronics industry.
Adopting strain Si/SiGe technology is to improve mobility through in traditional body Si device, introducing stress, improves device performance.The properties of product that silicon chip is produced improve 30%～60%, and process complexity and cost only increase by 1%～3%.As far as existing many integrated circuit production lines; If adopt the strain SiGe material that the Si CMOS ic core piece performance of producing is obviously improved, but also can prolong service life of the integrated circuit production line that the cost huge investment builds up greatly.
Summary of the invention
The objective of the invention is to be utilized in preparation strain SiGe planar channeling PMOS device, strain SiGe vertical-channel nmos device and SOI three polycrystal SiGe HBT devices on the substrate slice; Constitute strain SiGe and return type raceway groove BiCMOS integrated device and circuit, to realize the optimization of device and performance of integrated circuits.
The object of the present invention is to provide a kind of strain SiGe to return type raceway groove BiCMOS integrated device; Said strain SiGe returns type raceway groove Si base BiCMOS integrated device and adopts SOI three polycrystal SiGe HBT devices, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS device.
Further, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
Further, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
Further, emitter, base stage and the collector electrode of said SiGe HBT device all adopt polysilicon to contact.
Further, to return type raceway groove Si base BiCMOS integrated device be the whole plane structure to said strain SiGe.
Further, the nmos device conducting channel is back type, and channel direction is vertical with substrate surface.
Another object of the present invention is to provide a kind of strain SiGe to return the preparation method of type raceway groove BiCMOS integrated device, comprise the steps:
The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10
16～1 * 10
17Cm
-3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10
16～1 * 10
17Cm
-3
The 3rd step, utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 300 ~ 500nm at the epitaxy Si laminar surface layer thickness of growing
2Layer, the photoetching deep trench isolation, dry etching goes out the deep trouth that the degree of depth is 2.5 ~ 3.5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method again, at 600～800 ℃, in deep trouth, fills SiO
2At last,, remove the unnecessary oxide layer in surface, form deep trench isolation with chemico-mechanical polishing (CMP) method;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at epitaxy Si laminar surface deposit one layer thickness
2Layer, photoetching collector electrode contact zone window carries out phosphorus to substrate and injects, and making collector electrode contact zone doping content is 1 * 10
19～1 * 10
20Cm
-3, form collector contact area, again with substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The 5th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit two layer materials: ground floor is SiO
2Layer, thickness is 20 ~ 40nm; The second layer is a P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 * 10
20～1 * 10
21Cm
-3
The 6th step, photoetching Poly-Si form outer base area, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
The 7th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit layer of sin layer, thickness are 50～100nm, and the photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window; Utilize chemical vapor deposition (CVD) method again, at 600～800 ℃, at substrate surface deposit layer of sin layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;
The 8th the step, utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base, utilizes chemical vapor deposition (CVD) method, at 600～750 ℃, and the regioselectivity growth SiGe base in the base, the Ge component is 15 ~ 25%, doping content is 5 * 10
18~ 5 * 10
19Cm
-3, thickness is 20 ~ 60nm;
The 9th step, photoetching collector electrode window; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit Poly-Si; Thickness is 200 ~ 400nm; Again substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
The tenth the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, photoetching collector electrode, and this contact hole is carried out phosphorus inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
19~ 1 * 10
20Cm
-3, remove the SiO on surface at last
2Layer;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The 12 step, photoetching nmos device active area; Utilize dry etch process; Etch the deep trouth that the degree of depth is 1.5～2.0 μ m at the nmos device active area, utilize the method for chemical vapor deposition (CVD), at 600～750 ℃; Continuous growth five layer materials in deep trouth: ground floor is that thickness is the N type Si epitaxial loayer of 1.3～1.6 μ m, and doping content is 5 * 10
19～1 * 10
20Cm
-3, as the nmos device drain region; The second layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 1～5 * 10
18Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10
16～5 * 10
17Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20～30% Gradient distribution, as the nmos device channel region; The 4th layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 1～5 * 10
18Cm
-3, the Ge component is for being 20～30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10
19～1 * 10
20Cm
-3, as the nmos device source region;
The 13 goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～780 ℃, at substrate surface deposit one deck SiO
2, photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and selective epitaxial growth one deck N type relaxation Si layer in deep trouth, doping content is 5 * 10
16～5 * 10
17Cm
-3, thickness is 30～50 μ m, regrowth one N type strain SiGe layer, and doping content is 5 * 10
16～5 * 10
17Cm
-3, the Ge component is 10～30%, thickness is 10～20nm, and the intrinsic relaxation Si cap layer of growing at last, thickness is 3～5nm, and groove is filled up, and forms the PMOS device active region; Utilize wet etching, etch away the layer SiO on surface
2
The 14 step, utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer, the photoetching shallow-trench isolation goes out the shallow slot that the degree of depth is 300 ~ 500nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method again, at 600～800 ℃, in shallow slot, fills SiO
2At last,, remove the unnecessary oxide layer in surface, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2And layer of sin, form the barrier layer; The photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4～0.6 μ m; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, the deposit doping content is 1～5 * 10
20Cm
-3N type Ploy-Si, groove is filled up, chemico-mechanical polishing (CMP) method is removed the unnecessary Ploy-Si of substrate surface, forms nmos device and leaks the bonding pad; Utilize wet etching, etch away the layer SiO on surface
2And SiN;
The 16 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2And layer of sin, form the barrier layer once more; Photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4～0.6 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of 5～8nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer, utilize chemical vapor deposition (CVD) method then, at 600～780 ℃, be 1～5 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up, get rid of the nmos device gate groove again with outer surface part Poly-Si and HfO
2, form nmos device grid, source region, finally form nmos device; Utilize wet etching, etch away the layer SiO on surface
2And SiN;
The 17 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2, photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600～780 ℃, is the SiO of 10～15nm at substrate surface deposit one layer thickness
2With a layer thickness be the Poly-Si of 200～300nm, photoetching Poly-Si and SiO
2, form the empty grid of PMOS device; The PMOS device is carried out P type ion inject, forming doping content is 1～5 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
The 18 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, deposit one layer thickness is the SiO of 3～5nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall; Again the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10
19～1 * 10
20Cm
-3
The 19 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid; The empty grid of wet etching form a groove at the gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; With physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing, with the stop layer of W-TiN composite grid as chemico-mechanical polishing (CMP), thereby forms grid, finally forms the PMOS device;
The 20 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO
2Layer, lithography fair lead, metallization, splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22 ~ 45nm returns type raceway groove BiCMOS integrated device.
Further, the nmos device channel length confirms according to the P type strain SiGe layer thickness of the 12 step deposit, gets 22～45nm.
Further, related chemical vapor deposition (CVD) technological temperature determines that maximum temperature is smaller or equal to 800 ℃ among this preparation method.
Further, wherein, base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20～60nm.
Another object of the present invention is to provide a kind of strain SiGe to return the preparation method of type raceway groove BiCMOS integrated circuit, comprise the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO
2, thickness is 400nm, upper layer of material is that doping content is 1 * 10
17Cm
-3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 100nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10
17Cm
-3
Step 2, the implementation method of deep trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(2b) photoetching deep trench isolation zone;
(2c) dry etching goes out the deep trouth that the degree of depth is 2.5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2, and with filling up in the deep trouth;
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 3, the implementation method of collector electrode contact zone preparation is:
(3a) utilize the method for chemical vapor deposition (CVD), at 800 ℃, answering deposit one layer thickness at the epitaxy Si laminar surface is the SiO of 300nm
2Layer;
(3b) photoetching collector electrode contact zone window;
(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10
20Cm
-3, form collector contact area;
(3d) with substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation;
Step 4, the implementation method of base contact preparation is:
(4a) etching away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at substrate surface deposit one layer thickness
2Layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck P type Poly-Si layer, as the contact zone, base, this layer thickness is 400nm, and doping content is 1 * 10
21Cm
-3
(4c) photoetching Poly-Si forms outer base area, at 800 ℃, at substrate surface deposit SiO
2Layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
(4d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one SiN layer, thickness is 100nm;
(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;
(4f) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit layer of sin layer, thickness is 20nm;
Step 5, the implementation method of base material preparation is:
(5a) utilize dry method, etch away emitter window SiN, form side wall;
(5b) utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base;
(5c) utilize chemical vapor deposition (CVD) method, at 750 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 25%, doping content is 5 * 10
19Cm
-3, thickness is 60nm;
Step 6, the implementation method of emitter region preparation is:
(6a) photoetching collector electrode window utilizes chemical vapor deposition (CVD) method, and at 800 ℃, at substrate surface deposit Poly-Si, thickness is 400nm;
(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
(6c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer;
(6d) photoetching collector electrode, and phosphorus is carried out in this zone once more inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
20Cm
-3, remove the SiO on surface at last
2Layer;
(6e) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer, the 15s that under 1100 ℃ of temperature, anneals, activator impurity;
Step 7, the implementation method of NMOS and the preparation of PMOS device active region is:
(7a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 2 μ m at the nmos device active area;
(7b) utilizing the method for chemical vapor deposition chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 1.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device drain region;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10
16Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(7e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device source region;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO
2
(7h) photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 600 ℃, and selective growth one N type relaxation Si layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, thickness is 50nm;
(7i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one N type strain SiGe layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, the Ge component is 10%, thickness is 20nm;
(7j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one intrinsic relaxation Si cap layer in PMOS device active region deep trouth, thickness is 5nm, forms the N trap;
(7k) utilize wet etching, etch away the layer SiO on surface
2
Step 8, the implementation method of shallow-trench isolation preparation is:
(8a) utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(8b) photoetching shallow-trench isolation is utilized dry etch process, etches the shallow slot that the degree of depth is 500nm in isolated area;
(8c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃
2
(8d), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 9, nmos device are leaked the implementation method that connects preparation and are:
(9a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer;
(9b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(9c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2
(9d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Ploy-Si, nmos device is leaked groove fills up;
(9e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(9f) utilize wet etching, etch away the layer SiO on surface
2And SiN;
Step 10, the implementation method that nmos device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer once more;
(10b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(10c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer;
(10d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up;
(10e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again
2Layer forms nmos device grid, source region, finally forms nmos device;
(10f) utilize wet etching, etch away the SiO on surface
2With the SiN layer;
Step 11, the implementation method that preparation is leaked in empty grid of PMOS device and source is:
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2
(11b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness
2
(11c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(11d) photoetching Poly-Si and SiO
2, form the empty grid of PMOS device;
(11e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
(11f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall;
(11g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10
19Cm
-3
Step 12, the implementation method that the PMOS device forms is:
(the CVD method is at 600 ℃, at substrate surface deposit SiO (12a) to utilize chemical vapor deposition
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid;
(12b) the empty grid of wet etching form a groove at the gate electrode place;
(12c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(12d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(12e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP);
Step 13, the implementation method that constitutes the BiCMOS integrated circuit is:
(13a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer;
(13b) lithography fair lead;
(13c) metallization;
(13d) splash-proofing sputtering metal; The photoetching lead-in wire; Form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire; PMOS device drain metal lead wire, source metal go between and the gate metal lead-in wire, and bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, formation MOS device conducting channel are that the strain SiGe of 45nm returns type raceway groove BiCMOS integrated device and circuit.
The present invention has following advantage:
1. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device, has made full use of the anisotropic characteristic of strain SiGe material stress, introduces compressive strain in the horizontal direction, has improved PMOS device hole mobility; Introduce tensile strain in vertical direction, improved the nmos device electron mobility, therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
2. the present invention returns in the type raceway groove BiCMOS integrated device process at the preparation strain SiGe; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth strain SiGe material; Improve the flexibility of designs, strengthened cmos device and integrated circuit electric property;
3. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device structure; The channel direction of nmos device is a vertical direction, and raceway groove is the strain SiGe layer of chemical vapor deposition (CVD) method preparation, and the thickness of SiGe layer is the channel length of nmos device; Therefore; In the preparation of nmos device, avoid the photoetching of small size grid, reduced process complexity, reduced cost;
4. the strain SiGe of the present invention preparation raceway groove that returns nmos device in the type raceway groove BiCMOS integrated device structure is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the strain SiGe of the present invention preparation returns that nmos device raceway groove Ge component changes in gradient in the type raceway groove BiCMOS integrated device structure; Therefore can produce the built-in field that an accelerated electron transports at channel direction; Strengthen the carrier transport ability of raceway groove, thereby improved the frequency characteristic and the current driving ability of strain SiGe nmos device;
6. the strain SiGe of the present invention preparation returns the HfO that nmos device in the type raceway groove BiCMOS integrated device structure has adopted high K value
2As gate medium, improved the grid-control ability of nmos device, strengthened the electric property of nmos device;
7. the strain SiGe of the present invention preparation returns that the PMOS device is a quantum well devices in the type raceway groove BiCMOS integrated device structure; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
8. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device structure, and the PMOS device adopts SiON to replace traditional pure SiO
2Do gate medium, not only strengthened the reliability of device, and utilize the variation of gate medium dielectric constant, improved the grid-control ability of device;
9. to return the maximum temperature that relates in the type raceway groove BiCMOS process be 800 ℃ at the preparation strain SiGe in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;
10. the present invention prepares strain SiGe and returns in the type raceway groove BiCMOS integrated device process; The PMOS device has adopted metal gate mosaic technology (damascene process) preparation gate electrode; This gate electrode is a metal W-TiN composite construction, because the TiN of lower floor and strain Si and strain SiGe material work function difference are less, has improved electric properties of devices; The W on upper strata then can reduce the resistance of gate electrode, has realized the optimization of gate electrode;
11. the strain SiGe of the present invention's preparation returns type raceway groove BiCMOS integrated device, in the preparation process, adopts fully self aligned technology, has reduced dead resistance and electric capacity effectively, has improved the electric current and the frequency characteristic of device;
12. the strain SiGe of the present invention's preparation returns emitter, base stage and the collector electrode of SiGe HBT device in the type raceway groove BiCMOS integrated device and all adopts polycrystalline; Polycrystalline can partly be produced on above the oxide layer; Reduced the area of device active region; Thereby reduce device size, improve the integrated level of circuit.
Description of drawings
Fig. 1 is the realization flow figure that strain SiGe of the present invention returns type raceway groove BiCMOS integrated device and circuit preparation method.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain SiGe to return type raceway groove BiCMOS integrated device; Said strain SiGe returns type raceway groove Si base BiCMOS integrated device and adopts SOI three polycrystalline/autoregistration SiGe HBT device, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS device.
As a prioritization scheme of the embodiment of the invention, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
As a prioritization scheme of the embodiment of the invention, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
As a prioritization scheme of the embodiment of the invention, emitter, base stage and the collector electrode of said SiGe HBT device all adopts polysilicon to contact.
As a prioritization scheme of the embodiment of the invention, it is the whole plane structure that said strain SiGe returns type raceway groove Si base BiCMOS integrated device.
Following with reference to accompanying drawing 1, the technological process of strain SiGe of the present invention being returned type raceway groove BiCMOS integrated device and circuit preparation describes in further detail.
Embodiment 1: the preparation conducting channel is that the strain SiGe of 45nm returns type raceway groove BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO
2, thickness is 400nm, upper layer of material is that doping content is 1 * 10
17Cm
-3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 100nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10
17Cm
-3
Step 2, the deep trench isolation preparation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(2b) photoetching deep trench isolation zone;
(2c) dry etching goes out the deep trouth that the degree of depth is 2.5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2, and with filling up in the deep trouth;
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 3, the preparation of collector electrode contact zone.
(3a) utilize the method for chemical vapor deposition (CVD), at 800 ℃, answering deposit one layer thickness at the epitaxy Si laminar surface is the SiO of 300nm
2Layer;
(3b) photoetching collector electrode contact zone window;
(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10
20Cm
-3, form collector contact area;
(3d) with substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation.
Step 4, the base contact preparation.
(4a) etching away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at substrate surface deposit one layer thickness
2Layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck P type Poly-Si layer, as the contact zone, base, this layer thickness is 400nm, and doping content is 1 * 10
21Cm
-3
(4c) photoetching Poly-Si forms outer base area, at 800 ℃, at substrate surface deposit SiO
2Layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
(4d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one SiN layer, thickness is 100nm;
(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;
(4f) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit layer of sin layer, thickness is 20nm.
Step 5, the base material preparation.
(5a) utilize dry method, etch away emitter window SiN, form side wall;
(5b) utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base;
(5c) utilize chemical vapor deposition (CVD) method, at 750 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 25%, doping content is 5 * 10
19Cm
-3, thickness is 60nm.
Step 6, the emitter region preparation.
(6a) photoetching collector electrode window utilizes chemical vapor deposition (CVD) method, and at 800 ℃, at substrate surface deposit Poly-Si, thickness is 400nm;
(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
(6c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer;
(6d) photoetching collector electrode, and phosphorus is carried out in this zone once more inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
20Cm
-3, remove the SiO on surface at last
2Layer;
(6e) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer, the 15s that under 1100 ℃ of temperature, anneals, activator impurity.
Step 7, NMOS and the preparation of PMOS device active region.
(7a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 2 μ m at the nmos device active area;
(7b) utilizing the method for chemical vapor deposition chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 1.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device drain region;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10
16Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(7e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device source region;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO
2
(7h) photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 600 ℃, and selective growth one N type relaxation Si layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, thickness is 50nm;
(7i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one N type strain SiGe layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, the Ge component is 10%, thickness is 20nm;
(7j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one intrinsic relaxation Si cap layer in PMOS device active region deep trouth, thickness is 5nm, forms the N trap;
(7k) utilize wet etching, etch away the layer SiO on surface
2
Step 8, the shallow-trench isolation preparation.
(8a) utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(8b) photoetching shallow-trench isolation is utilized dry etch process, etches the shallow slot that the degree of depth is 500nm in isolated area;
(8c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃
2
(8d), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method.
Step 9, nmos device are leaked and are connected preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer;
(9b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(9c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2
(5d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Ploy-Si, nmos device is leaked groove fills up;
(9e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(9f) utilize wet etching, etch away the layer SiO on surface
2And SiN.
Step 10, nmos device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer once more;
(10b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(10c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer;
(10d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up;
(10e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again
2Layer forms nmos device grid, source region, finally forms nmos device;
(10f) utilize wet etching, etch away the SiO on surface
2With the SiN layer.
Step 11, preparation is leaked in empty grid of PMOS device and source.
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2
(11b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness
2
(11c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(11d) photoetching Poly-Si and SiO
2, form the empty grid of PMOS device;
(11e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
(11f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall;
(11g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10
19Cm
-3
Step 12, the PMOS device forms.
(12a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid;
(12b) the empty grid of wet etching form a groove at the gate electrode place;
(12c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(12d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(12e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 13 constitutes the BiCMOS integrated circuit.
(13a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer;
(13b) lithography fair lead;
(13c) metallization;
(13d) splash-proofing sputtering metal; The photoetching lead-in wire; Form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire; PMOS device drain metal lead wire, source metal go between and the gate metal lead-in wire, and bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, formation MOS device conducting channel are that the strain SiGe of 45nm returns type raceway groove BiCMOS integrated device and circuit.
Embodiment 2: the preparation conducting channel is that the strain SiGe of 30nm returns type raceway groove BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO
2, thickness is 300nm, upper layer of material is that doping content is 5 * 10
16Cm
-3N type Si, thickness is 120nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type epitaxy Si layer of 80nm on the Si material of upper strata, and as collector region, this layer doping content is 5 * 10
16Cm
-3
Step 2, the deep trench isolation preparation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(2b) photoetching deep trench isolation zone;
(2c) dry etching goes out the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO
2, and with filling up in the deep trouth;
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 3, the preparation of collector electrode contact zone.
(3a) utilize the method for chemical vapor deposition (CVD), at 700 ℃, answering deposit one layer thickness at the epitaxy Si laminar surface is the SiO of 240nm
2Layer;
(3b) photoetching collector electrode contact zone window;
(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 5 * 10
19Cm
-3, form collector contact area;
(3d) with substrate under 1000 ℃ of temperature, annealing 60s, carry out impurity activation.
Step 4, the base contact preparation.
(4a) etching away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 700 ℃, is the SiO of 30nm at substrate surface deposit one layer thickness
2Layer;
(4b) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck P type Poly-Si layer, as the contact zone, base, this layer thickness is 300nm, and doping content is 5 * 10
20Cm
-3
(4c) photoetching Poly-Si forms outer base area, at 700 ℃, at substrate surface deposit SiO
2Layer, thickness is 300nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
(4d) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one SiN layer, thickness is 80nm;
(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;
(4f) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit layer of sin layer, thickness is 15nm.
Step 5, the base material preparation.
(5a) utilize dry method, etch away emitter window SiN, form side wall;
(5b) utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base;
(5c) utilize chemical vapor deposition (CVD) method, at 700 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 20%, doping content is 1 * 10
19Cm
-3, thickness is 40nm.
Step 6, the emitter region preparation.
(6a) photoetching collector electrode window utilizes chemical vapor deposition (CVD) method, and at 700 ℃, at substrate surface deposit Poly-Si, thickness is 300nm;
(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
(6c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO
2Layer;
(6d) photoetching collector electrode, and phosphorus is carried out in this zone once more inject, the doping content with the Poly-Si that improves collector electrode makes it reach 5 * 10
19Cm
-3, remove the SiO on surface at last
2Layer;
(6e) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO
2Layer, the 60s that under 1000 ℃ of temperature, anneals, activator impurity.
Step 7, NMOS and the preparation of PMOS device epitaxial material.
(7a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 1.8 μ m at the nmos device active area;
(7b) utilizing the method for chemical vapor deposition chemical vapor deposition (CVD), at 700 ℃, is the N type Si epitaxial loayer of 1.5 μ m at nmos device active area selective growth thickness, and doping content is 8 * 10
19Cm
-3, as the nmos device drain region;
(7c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type strain SiGe layer of 4nm at nmos device active area selective growth thickness, and doping content is 3 * 10
18Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7d) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the P type strain SiGe layer 4 of 30nm at nmos device active area selective growth thickness, and doping content is 1 * 10
17Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20%, as the nmos device channel region;
(7e) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type strain SiGe layer of 4nm at nmos device active area selective growth thickness, and doping content is 3 * 10
18Cm
-3, the Ge component is 20%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7f) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type Si layer of 300nm at nmos device active area selective growth thickness, and doping content is 8 * 10
19Cm
-3, as the nmos device source region;
(7g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, at substrate surface deposit one deck SiO
2
(7h) photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 700 ℃, and selective growth one N type relaxation Si layer in PMOS device active region deep trouth, doping content is 1 * 10
17Cm
-3, thickness is 40nm;
(7i) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one N type strain SiGe layer in PMOS device active region deep trouth, doping content is 1 * 10
17Cm
-3, the Ge component is 20%, thickness is 15nm;
(7j) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one intrinsic relaxation Si cap layer in PMOS device active region deep trouth, thickness is 4nm, forms the N trap;
(7k) utilize wet etching, etch away the layer SiO on surface
2
Step 8, the shallow-trench isolation preparation.
(8a) utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 240nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(8b) photoetching shallow-trench isolation is utilized dry etch process, etches the shallow slot that the degree of depth is 400nm in isolated area;
(8c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃
2
(8d), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method.
Step 9, nmos device are leaked and are connected preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer;
(9b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.5 μ m;
(9c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2
(9d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content
20Cm
-3N type Ploy-Si, nmos device is leaked groove fills up;
(9e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(9f) utilize wet etching, etch away the layer SiO on surface
2And SiN.
Step 10, nmos device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer once more;
(10b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.5 μ m;
(10c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of 6nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer;
(10d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up;
(10e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again
2Layer forms nmos device grid, source region, finally forms nmos device;
(10f) utilize wet etching, etch away the SiO on surface
2With the SiN layer.
Step 11, preparation is leaked in empty grid of PMOS device and source.
(11a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO
2
(11b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 700 ℃, is the SiO of 12nm at substrate surface deposit one layer thickness
2
(11c) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the Poly-Si of 240nm at substrate surface deposit one layer thickness;
(11d) photoetching Poly-Si and SiO
2, form the empty grid of PMOS device;
(11e) the PMOS device is carried out P type ion and inject, forming doping content is 3 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
(11f) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one layer thickness is the SiO of 4nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall;
(11g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 8 * 10
19Cm
-3
Step 12, the PMOS device forms.
(12a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid;
(12b) the empty grid of wet etching form a groove at the gate electrode place;
(12c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiON, thickness is 3nm;
(12d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(12e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 13 constitutes the BiCMOS integrated circuit.
(13a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO
2Layer;
(13b) lithography fair lead;
(13c) metallization;
(13d) splash-proofing sputtering metal; The photoetching lead-in wire; Form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire; PMOS device drain metal lead wire, source metal go between and the gate metal lead-in wire, and bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, formation MOS device conducting channel are that the strain SiGe of 30nm returns type raceway groove BiCMOS integrated device and circuit.
Embodiment 3: the preparation conducting channel is that the strain SiGe of 22nm returns type raceway groove BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO
2, thickness is 150nm, upper layer of material is that doping content is 1 * 10
16Cm
-3N type Si, thickness is 100nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10
16Cm
-3
Step 2, the deep trench isolation preparation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(2b) photoetching deep trench isolation zone;
(2c) dry etching goes out the deep trouth that the degree of depth is 3.5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2, and with filling up in the deep trouth;
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 3, the preparation of collector electrode contact zone.
(3a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, answering deposit one layer thickness at the epitaxy Si laminar surface is the SiO of 200nm
2Layer;
(3b) photoetching collector electrode contact zone window;
(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10
19Cm
-3, form collector contact area;
(3d) with substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation.
Step 4, the base contact preparation.
(4a) etching away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 20nm at substrate surface deposit one layer thickness
2Layer;
(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck P type Poly-Si layer, as the contact zone, base, this layer thickness is 200nm, and doping content is 1 * 10
20Cm
-3
(4c) photoetching Poly-Si forms outer base area, at 600 ℃, at substrate surface deposit SiO
2Layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
(4d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiN layer, thickness is 50nm;
(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;
(4f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit layer of sin layer, thickness is 10nm.
Step 5, the base material preparation.
(5a) utilize dry method, etch away emitter window SiN, form side wall;
(5b) utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base;
(5c) utilize chemical vapor deposition (CVD) method, at 600 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 15%, doping content is 5 * 10
18Cm
-3, thickness is 20nm.
Step 6, the emitter region preparation.
(6a) photoetching collector electrode window utilizes chemical vapor deposition (CVD) method, and at 600 ℃, at substrate surface deposit Poly-Si, thickness is 200nm;
(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
(6c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer;
(6d) photoetching collector electrode, and phosphorus is carried out in this zone once more inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
19Cm
-3, remove the SiO on surface at last
2Layer;
(6e) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer, the 120s that under 950 ℃ of temperature, anneals, activator impurity.
Step 7, NMOS and the preparation of PMOS device epitaxial material.
(7a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 1.5 μ m at the nmos device active area;
(7b) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type Si epitaxial loayer of 1.3 μ m at nmos device active area selective growth thickness, and doping content is 1 * 10
20Cm
-3, as the nmos device drain region;
(7c) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type strain SiGe layer of 3nm at nmos device active area selective growth thickness, and doping content is 1 * 10
18Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7d) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the P type strain SiGe layer of 22nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 25%, as the nmos device channel region;
(7e) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type strain SiGe layer of 3nm at nmos device active area selective growth thickness, and doping content is 1 * 10
18Cm
-3, the Ge component is 25%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7f) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type Si layer of 200nm at nmos device active area selective growth thickness, and doping content is 1 * 10
20Cm
-3, as the nmos device source region;
(7g) utilize the method for chemical vapor deposition (CVD), at 780 ℃, at substrate surface deposit one deck SiO
2
(7h) photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 750 ℃, and selective growth one N type relaxation Si layer in PMOS device active region deep trouth, doping content is 5 * 10
17Cm
-3, thickness is 30nm;
(7i) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one N type strain SiGe layer in PMOS device active region deep trouth, doping content is 5 * 10
17Cm
-3, the Ge component is 30%, thickness is 10nm;
(7j) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one intrinsic relaxation Si cap layer in PMOS device active region deep trouth, thickness is 3nm, forms the N trap;
(7k) utilize wet etching, etch away the layer SiO on surface
2
Step 8, the shallow-trench isolation preparation.
(8a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(8b) photoetching shallow-trench isolation is utilized dry etch process, etches the shallow slot that the degree of depth is 300nm in isolated area;
(8c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃
2
(8d), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method.
Step 9, nmos device are leaked and are connected preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer;
(9b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4 μ m;
(9c) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2
(9d) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is 5 * 10 in substrate surface deposit doping content
20Cm
-3N type Ploy-Si, nmos device is leaked groove fills up;
(9e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(9f) utilize wet etching, etch away the layer SiO on surface
2And SiN.
Step 10, nmos device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer once more;
(10b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4 μ m;
(10c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of 8nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer;
(10d) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is 5 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up;
(10e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again
2Layer forms nmos device grid, source region, finally forms nmos device;
(10f) utilize wet etching, etch away the SiO on surface
2With the SiN layer.
Step 11, preparation is leaked in empty grid of PMOS device and source.
(11a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO
2
(11b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 780 ℃, is the SiO of 15nm at substrate surface deposit one layer thickness
2
(11c) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is the Poly-Si of 300nm at substrate surface deposit one layer thickness;
(11d) photoetching Poly-Si and SiO
2, form the empty grid of PMOS device;
(11e) the PMOS device is carried out P type ion and inject, forming doping content is 5 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
(11f) utilize chemical vapor deposition (CVD) method, at 780 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall;
(11g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 1 * 10
20Cm
-3
Step 12, the PMOS device forms.
(12a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid;
(12b) the empty grid of wet etching form a groove at the gate electrode place;
(12c) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5nm;
(12d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(12e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 13 constitutes the BiCMOS integrated circuit.
(13a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit SiO
2Layer;
(13b) lithography fair lead;
(13c) metallization;
(13d) splash-proofing sputtering metal; The photoetching lead-in wire; Form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire; PMOS device drain metal lead wire, source metal go between and the gate metal lead-in wire, and bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22nm returns type raceway groove BiCMOS integrated device circuit.
The strain SiGe that the embodiment of the invention provides returns type raceway groove BiCMOS integrated device and the preparation method has following advantage:
1. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device, has made full use of the anisotropic characteristic of strain SiGe material stress, introduces compressive strain in the horizontal direction, has improved PMOS device hole mobility; Introduce tensile strain in vertical direction, improved the nmos device electron mobility, therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
2. the present invention returns in the type raceway groove BiCMOS integrated device process at the preparation strain SiGe; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth strain SiGe material; Improve the flexibility of designs, strengthened cmos device and integrated circuit electric property;
3. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device structure; The channel direction of nmos device is a vertical direction, and raceway groove is the strain SiGe layer of chemical vapor deposition (CVD) method preparation, and the thickness of SiGe layer is the channel length of nmos device; Therefore; In the preparation of nmos device, avoid the photoetching of small size grid, reduced process complexity, reduced cost;
4. the strain SiGe of the present invention preparation raceway groove that returns nmos device in the type raceway groove BiCMOS integrated device structure is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the strain SiGe of the present invention preparation returns that nmos device raceway groove Ge component changes in gradient in the type raceway groove BiCMOS integrated device structure; Therefore can produce the built-in field that an accelerated electron transports at channel direction; Strengthen the carrier transport ability of raceway groove, thereby improved the frequency characteristic and the current driving ability of strain SiGe nmos device;
6. the strain SiGe of the present invention preparation returns the HfO that nmos device in the type raceway groove BiCMOS integrated device structure has adopted high K value
2As gate medium, improved the grid-control ability of nmos device, strengthened the electric property of nmos device;
7. the strain SiGe of the present invention preparation returns that the PMOS device is a quantum well devices in the type raceway groove BiCMOS integrated device structure; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
8. the strain SiGe of the present invention's preparation returns in the type raceway groove BiCMOS integrated device structure, and the PMOS device adopts SiON to replace traditional pure SiO
2Do gate medium, not only strengthened the reliability of device, and utilize the variation of gate medium dielectric constant, improved the grid-control ability of device;
9. to return the maximum temperature that relates in the type raceway groove BiCMOS process be 800 ℃ at the preparation strain SiGe in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;
10. the present invention prepares strain SiGe and returns in the type raceway groove BiCMOS integrated device process; The PMOS device has adopted metal gate mosaic technology (damascene process) preparation gate electrode; This gate electrode is a metal W-TiN composite construction, because the TiN of lower floor and strain Si and strain SiGe material work function difference are less, has improved electric properties of devices; The W on upper strata then can reduce the resistance of gate electrode, has realized the optimization of gate electrode;
11. the strain SiGe of the present invention's preparation returns type raceway groove BiCMOS integrated device, in the preparation process, adopts fully self aligned technology, has reduced dead resistance and electric capacity effectively, has improved the electric current and the frequency characteristic of device;
12. the strain SiGe of the present invention's preparation returns emitter, base stage and the collector electrode of SiGe HBT device in the type raceway groove BiCMOS integrated device and all adopts polycrystalline; Polycrystalline can partly be produced on above the oxide layer; Reduced the area of device active region; Thereby reduce device size, improve the integrated level of circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a strain SiGe returns type raceway groove BiCMOS integrated device; It is characterized in that; Said strain SiGe returns type raceway groove Si base BiCMOS integrated device and adopts SOI three polycrystal SiGe HBT devices, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS device.
2. strain SiGe according to claim 1 returns type raceway groove BiCMOS integrated device, it is characterized in that, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
3. strain SiGe according to claim 1 returns type raceway groove BiCMOS integrated device, it is characterized in that, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
4. strain SiGe according to claim 1 returns type raceway groove BiCMOS integrated device, it is characterized in that, emitter, base stage and the collector electrode of said SiGe HBT device all adopts polysilicon to contact.
5. strain SiGe according to claim 1 returns type raceway groove BiCMOS integrated device, it is characterized in that, it is the whole plane structure that said strain SiGe returns type raceway groove Si base BiCMOS integrated device.
6. strain SiGe according to claim 1 returns type raceway groove BiCMOS integrated device, it is characterized in that the nmos device conducting channel is back type, and channel direction is vertical with substrate surface.
7. a strain SiGe returns the preparation method of type raceway groove BiCMOS integrated device, it is characterized in that, comprises the steps:
The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10
16～1 * 10
17Cm
-3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10
16～1 * 10
17Cm
-3
The 3rd step, utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 300 ~ 500nm at the epitaxy Si laminar surface layer thickness of growing
2Layer, the photoetching deep trench isolation, dry etching goes out the deep trouth that the degree of depth is 2.5 ~ 3.5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method again, at 600～800 ℃, in deep trouth, fills SiO
2At last,, remove the unnecessary oxide layer in surface, form deep trench isolation with chemico-mechanical polishing (CMP) method;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at epitaxy Si laminar surface deposit one layer thickness
2Layer, photoetching collector electrode contact zone window carries out phosphorus to substrate and injects, and making collector electrode contact zone doping content is 1 * 10
19～1 * 10
20Cm
-3, form collector contact area, again with substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The 5th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit two layer materials: ground floor is SiO
2Layer, thickness is 20 ~ 40nm; The second layer is a P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 * 10
20～1 * 10
21Cm
-3
The 6th step, photoetching Poly-Si form outer base area, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
The 7th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit layer of sin layer, thickness are 50 ~ 100nm, and the photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window; Utilize chemical vapor deposition (CVD) method again, at 600～800 ℃, at substrate surface deposit layer of sin layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;
The 8th the step, utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base, utilizes chemical vapor deposition (CVD) method, at 600～750 ℃, and the regioselectivity growth SiGe base in the base, the Ge component is 15 ~ 25%, doping content is 5 * 10
18~ 5 * 10
19Cm
-3, thickness is 20 ~ 60nm;
The 9th step, photoetching collector electrode window; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit Poly-Si; Thickness is 200 ~ 400nm; Again substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
The tenth the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, photoetching collector electrode, and this contact hole is carried out phosphorus inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
19~ 1 * 10
20Cm
-3, remove the SiO on surface at last
2Layer;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO
2Layer, under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The 12 step, photoetching nmos device active area; Utilize dry etch process; Etch the deep trouth that the degree of depth is 1.5～2.0 μ m at the nmos device active area, utilize the method for chemical vapor deposition (CVD), at 600～750 ℃; Continuous growth five layer materials in deep trouth: ground floor is that thickness is the N type Si epitaxial loayer of 1.3～1.6 μ m, and doping content is 5 * 10
19～1 * 10
20Cm
-3, as the nmos device drain region; The second layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 1～5 * 10
18Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10
16～5 * 10
17Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20～30% Gradient distribution, as the nmos device channel region; The 4th layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 1～5 * 10
18Cm
-3, the Ge component is for being 20～30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10
19～1 * 10
20Cm
-3, as the nmos device source region;
The 13 goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～780 ℃, at substrate surface deposit one deck SiO
2, photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and selective epitaxial growth one deck N type relaxation Si layer in deep trouth, doping content is 5 * 10
16～5 * 10
17Cm
-3, thickness is 30～50 μ m, regrowth one N type strain SiGe layer, and doping content is 5 * 10
16～5 * 10
17Cm
-3, the Ge component is 10～30%, thickness is 10～20nm, and the intrinsic relaxation Si cap layer of growing at last, thickness is 3～5nm, and groove is filled up, and forms the PMOS device active region; Utilize wet etching, etch away the layer SiO on surface
2
The 14 step, utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer, the photoetching shallow-trench isolation goes out the shallow slot that the degree of depth is 300 ~ 500nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method again, at 600～800 ℃, in shallow slot, fills SiO
2At last,, remove the unnecessary oxide layer in surface, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2And layer of sin, form the barrier layer; The photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4～0.6 μ m; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, the deposit doping content is 1～5 * 10
20Cm
-3N type Ploy-Si, groove is filled up, chemico-mechanical polishing (CMP) method is removed the unnecessary Ploy-Si of substrate surface, forms nmos device and leaks the bonding pad; Utilize wet etching, etch away the layer SiO on surface
2And SiN;
The 16 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2And layer of sin, form the barrier layer once more; Photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4～0.6 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of 5～8nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer, utilize chemical vapor deposition (CVD) method then, at 600～780 ℃, be 1～5 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up, get rid of the nmos device gate groove again with outer surface part Poly-Si and HfO
2, form nmos device grid, source region, finally form nmos device; Utilize wet etching, etch away the layer SiO on surface
2And SiN;
The 17 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO
2, photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600～780 ℃, is the SiO of 10～15nm at substrate surface deposit one layer thickness
2With a layer thickness be the Poly-Si of 200～300nm, photoetching Poly-Si and SiO
2, form the empty grid of PMOS device; The PMOS device is carried out P type ion inject, forming doping content is 1～5 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
The 18 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, deposit one layer thickness is the SiO of 3～5nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall; Again the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10
19～1 * 10
20Cm
-3
The 19 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid; The empty grid of wet etching form a groove at the gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; With physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing, with the stop layer of W-TiN composite grid as chemico-mechanical polishing (CMP), thereby forms grid, finally forms the PMOS device;
The 20 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO
2Layer, lithography fair lead, metallization, splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22 ~ 45nm returns type raceway groove BiCMOS integrated device.
8. method according to claim 7 is characterized in that, the nmos device channel length is confirmed according to the P type strain SiGe layer thickness of the 12 step deposit, got 22～45nm.
9. preparation method according to claim 7, chemical vapor deposition (CVD) technological temperature related among this preparation method determines that maximum temperature is smaller or equal to 800 ℃.
10. preparation method according to claim 7, wherein, base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20～60nm.
11. a strain SiGe returns the preparation method of type raceway groove BiCMOS integrated circuit, it is characterized in that, comprises the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO
2, thickness is 400nm, upper layer of material is that doping content is 1 * 10
17Cm
-3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 100nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10
17Cm
-3
Step 2, the implementation method of deep trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(2b) photoetching deep trench isolation zone;
(2c) dry etching goes out the deep trouth that the degree of depth is 2.5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2, and with filling up in the deep trouth;
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 3, the implementation method of collector electrode contact zone preparation is:
(3a) utilize the method for chemical vapor deposition (CVD), at 800 ℃, answering deposit one layer thickness at the epitaxy Si laminar surface is the SiO of 300nm
2Layer;
(3b) photoetching collector electrode contact zone window;
(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10
20Cm
-3, form collector contact area;
(3d) with substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation;
Step 4, the implementation method of base contact preparation is:
(4a) etching away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at substrate surface deposit one layer thickness
2Layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck P type Poly-Si layer, as the contact zone, base, this layer thickness is 400nm, and doping content is 1 * 10
21Cm
-3
(4c) photoetching Poly-Si forms outer base area, at 800 ℃, at substrate surface deposit SiO
2Layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface
2
(4d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one SiN layer, thickness is 100nm;
(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;
(4f) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit layer of sin layer, thickness is 20nm;
Step 5, the implementation method of base material preparation is:
(5a) utilize dry method, etch away emitter window SiN, form side wall;
(5b) utilize wet etching, to SiO in the window
2Layer carries out excessive erosion, forms the zone, base;
(5c) utilize chemical vapor deposition (CVD) method, at 750 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 25%, doping content is 5 * 10
19Cm
-3, thickness is 60nm;
Step 6, the implementation method of emitter region preparation is:
(6a) photoetching collector electrode window utilizes chemical vapor deposition (CVD) method, and at 800 ℃, at substrate surface deposit Poly-Si, thickness is 400nm;
(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter and collector zone, form emitter and collector with outer surface;
(6c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer;
(6d) photoetching collector electrode, and phosphorus is carried out in this zone once more inject, the doping content with the Poly-Si that improves collector electrode makes it reach 1 * 10
20Cm
-3, remove the SiO on surface at last
2Layer;
(6e) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO
2Layer, the 15s that under 1100 ℃ of temperature, anneals, activator impurity;
Step 7, the implementation method of NMOS and the preparation of PMOS device active region is:
(7a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 2 μ m at the nmos device active area;
(7b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 1.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device drain region;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10
16Cm
-3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(7e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10
17Cm
-3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(7f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10
19Cm
-3, as the nmos device source region;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO
2
(7h) photoetching PMOS device active region utilizes the method for chemical vapor deposition (CVD), at 600 ℃, and selective growth one N type relaxation Si layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, thickness is 50nm;
(7i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one N type strain SiGe layer in PMOS device active region deep trouth, doping content is 5 * 10
16Cm
-3, the Ge component is 10%, thickness is 20nm;
(7j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one intrinsic relaxation Si cap layer in PMOS device active region deep trouth, thickness is 5nm, forms the N trap;
(7k) utilize wet etching, etch away the layer SiO on surface
2
Step 8, the implementation method of shallow-trench isolation preparation is:
(8a) utilizing the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 300nm at the epitaxy Si laminar surface layer thickness of growing
2Layer;
(8b) photoetching shallow-trench isolation is utilized dry etch process, etches the shallow slot that the degree of depth is 500nm in isolated area;
(8c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃
2
(8d), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 9, nmos device are leaked the implementation method that connects preparation and are:
(9a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer;
(9b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(9c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO
2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface
2, keep the SiO that leaks trenched side-wall
2
(9d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Ploy-Si, nmos device is leaked groove fills up;
(9e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(9f) utilize wet etching, etch away the layer SiO on surface
2And SiN;
Step 10, the implementation method that nmos device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2And layer of sin, form the barrier layer once more;
(10b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(10c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness
2, form the nmos device gate dielectric layer;
(10d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content
20Cm
-3N type Poly-Si, the nmos device gate groove is filled up;
(10e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again
2Layer forms nmos device grid, source region, finally forms nmos device;
(10f) utilize wet etching, etch away the SiO on surface
2With the SiN layer;
Step 11, the implementation method that preparation is leaked in empty grid of PMOS device and source is:
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO
2
(11b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness
2
(11c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(11d) photoetching Poly-Si and SiO
2, form the empty grid of PMOS device;
(11e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10
18Cm
-3P type lightly-doped source drain structure (P-LDD);
(11f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface
2, dry etching falls the SiO on the substrate surface
2, the SiO of reservation Ploy-Si sidewall
2, form PMOS device gate electrode side wall;
(11g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10
19Cm
-3
Step 12, the implementation method that the PMOS device forms is:
(12a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again
2To empty grid upper surface, expose empty grid;
(12b) the empty grid of wet etching form a groove at the gate electrode place;
(12c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(12d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(12e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP);
Step 13, the implementation method that constitutes the BiCMOS integrated circuit is:
(13a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO
2Layer;
(13b) lithography fair lead;
(13c) metallization;
(13d) splash-proofing sputtering metal; The photoetching lead-in wire; Form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire; PMOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire constitute the MOS device
The part conducting channel is that the strain SiGe of 45nm returns type raceway groove BiCMOS integrated device and circuit.
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Citations (3)
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|---|---|---|---|---|
| US20080237637A1 (en) * | 2003-06-17 | 2008-10-02 | International Business Machines Corporation | ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL n-CHANNEL MISFETS AND METHODS THEREOF |
| CN101295647A (en) * | 2008-01-16 | 2008-10-29 | 清华大学 | Method for reinforcing MOS device channel region strain |
| CN102184898A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
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2012
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|---|---|---|---|---|
| US20080237637A1 (en) * | 2003-06-17 | 2008-10-02 | International Business Machines Corporation | ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL n-CHANNEL MISFETS AND METHODS THEREOF |
| CN101295647A (en) * | 2008-01-16 | 2008-10-29 | 清华大学 | Method for reinforcing MOS device channel region strain |
| CN102184898A (en) * | 2011-04-22 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor) |
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