CN102751281B

CN102751281B - A kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT and preparation method

Info

Publication number: CN102751281B
Application number: CN201210243689.1A
Authority: CN
Inventors: 宋建军; 胡辉勇; 李妤晨; 宣荣喜; 张鹤鸣; 舒斌; 戴显英; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2016-03-30
Anticipated expiration: 2032-07-16
Also published as: CN102751281A

Abstract

The invention discloses a kind of based on three polycrystal SiGes? the strain BiCMOS integrated device of HBT and preparation method, first utilize self-registered technology on Si substrate slice, prepare three polycrystal SiGe HBT; Then on substrate nmos device and PMOS device active area, N-type Si epitaxial loayer, N-type strained sige layer, P type strained sige layer, N-type strained sige layer, N-type Si layer and N-type Si layer, N-type strained sige layer, N-type Si cap layers is grown respectively, carry out the drain electrode of nmos device active area, grid and source region preparation, complete nmos device preparation; Prepare empty grid in PMOS device active area, dielectric layer deposited forms grid side wall, and self-registered technology is injected and formed PMOS device source, leakage; Form grid, complete PMOS device preparation, form strain BiCMOS integrated device and circuit that MOS raceway groove is 22 ~ 45nm; Do the present invention makes full use of compressive strain sige material, and electron mobility and horizontal direction hole mobility, higher than the feature of relaxation Si, under low temperature process, produce three polycrystal SiGes of performance enhancement in the vertical direction? the strain BiCMOS integrated circuit of HBT.

Description

A kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT and preparation method.

Background technology

Semiconductor integrated circuit is the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid.In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy; At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

SiCMOS integrated circuit has the advantages such as low-power consumption, high integration, low noise and high reliability, ascendancy is occupied in semiconductor IC industry, but along with the increase of the reduction of the further increase of footprint, device feature size, integrated level and complexity, especially after device feature size enters nanoscale, the material of SiCMOS device, the limitation of physical features progressively manifest out, limit further developing of Si integrated circuit and manufacturing process thereof; Although the research of microelectronics in compound semiconductor and other new material and having made great progress in the application in some field, far do not possess the condition of alternative silica-based technique; And according to the rule of development of science and technology, a kind of new technology main force's technology from be born to becoming generally needs the time in twenty or thirty year.So in order to the needs that satisfied traditional performance improves, the performance strengthening SiCMOS is considered to the developing direction of microelectronics industry.

Employing strain Si, SiGe technology improve mobility by introducing stress in traditional body Si device, improves device performance.The properties of product that silicon chip can be made to produce improve 30% ~ 60%, and process complexity and cost only increase by 1% ~ 3%.For existing many integrated circuit production lines, if adopt strain SiGe material that the SiCMOS ic core piece performance produced not only can be made obviously to improve when substantially not increasing investment, but also greatly can extend the service life of the integrated circuit production line that cost huge investment is built up.

Summary of the invention

The object of the present invention is to provide a kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT and preparation method, with realize utilizing strain SiGe material in the vertical direction electron mobility and horizontal direction hole mobility higher than the feature of relaxation Si, under low temperature process, produce strain BiCMOS integrated device and the circuit of three polycrystal SiGe HBT of performance enhancement.

The object of the present invention is to provide a kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT, described two strain plane BiCMOS integrated device adopts three polycrystal SiGe HBT, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS device.

Further, described nmos device conducting channel is strain SiGe material, is tensile strain along channel direction.

Further, described PMOS device conducting channel is strain SiGe material, is compressive strain along channel direction.

Further, described nmos device conducting channel is hollow, and channel direction is vertical with substrate surface.

Further, SiGeHBT device emitter, base stage and collector electrode all adopt polysilicon contact.

Further, its preparation process adopts self-registered technology, and is whole plane structure.

Another object of the present invention is to the preparation method that a kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT is provided, comprise the steps:

The first step, to choose doping content be 5 × 10 ¹⁴~ 5 × 10 ¹⁵cm ^-3p type Si sheet as substrate;

Second step, be the SiO of 300 ~ 500nm at substrate surface thermal oxidation one thickness ₂layer, photoetching buried region, carries out the injection of N-type impurity to buried region, and at 800 ~ 950 DEG C, annealing 30 ~ 90min activator impurity, forms N-type heavy doping buried region;

The oxide layer of the 3rd step, removal excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 2 ~ 3 μm, as collector region;

4th step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

5th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer, photoetching collector contact district window, carries out phosphorus injection to substrate, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, then by substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

6th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit two layer material: ground floor is SiO ₂layer, thickness is 20 ~ 40nm; The second layer is P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 × 10 ²⁰~ 1 × 10 ²¹cm ^-3;

7th step, photoetching Poly-Si, form outer base area, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

8th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit layer of sin layer, thickness is 50 ~ 100nm, photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;

9th step, utilize wet etching, to SiO in window ₂layer carries out excessive erosion, forms region, base, utilizes chemical vapor deposition (CVD) method, and at 600 ~ 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, thickness is 20 ~ 60nm;

Tenth step, photoetching collector electrode window, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit Poly-Si, thickness is 200 ~ 400nm, again phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

11 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, photoetching collector electrode, and phosphorus injection is carried out to this region, to improve the doping content of the Poly-Si in collector electrode, make it reach 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer;

12 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

13 step, photoetching nmos device active area, utilize dry etch process, the deep trouth that the degree of depth is 1.02 ~ 1.92 μm is etched in nmos device active area, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, continuous growth five layer materials in deep trouth: ground floor to be thickness the be N-type Si epitaxial loayer of 0.5 ~ 1.0 μm, doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as nmos device drain region; The N-type strained sige layer of the second layer to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first N-type lightly-doped source drain structure (N-LDD) layer of nmos device; The P type strained sige layer of third layer to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is gradient distribution, and lower floor is 10%, and upper strata is the gradient distribution of 20 ~ 30%, as nmos device channel region; The N-type strained sige layer of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, Ge component for being 20 ~ 30%, as the second N-type lightly-doped source drain structure (N-LDD) layer of nmos device; The N-type Si layer of layer 5 to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as nmos device source region;

14 step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 780 DEG C, at substrate surface deposit one deck SiO ₂, photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the shallow slot that the degree of depth is 100 ~ 140nm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, selective epitaxial growth one deck N-type relaxation Si layer in deep trouth, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, thickness is 90 ~ 120nm, and regrowth one N-type strained sige layer, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is 10 ~ 30%, and thickness is 10 ~ 20nm, and finally grow an intrinsic relaxation Si cap layers, thickness is 3 ~ 5nm, is filled up by groove, forms PMOS device active area; Utilize wet etching, etch away the layer SiO on surface ₂;

15 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer; Photoetching nmos device source and drain isolated area, utilizes dry etch process, goes out at this region etch the shallow slot that the degree of depth is 0.3 ~ 0.5 μm; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, fills SiO in shallow slot ₂, form shallow-trench isolation;

16 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, form barrier layer; Photoetching nmos device leaks groove, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.4 ~ 0.6 μm; Utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiO ₂, form nmos device and leak trenched side-wall isolation, dry etching falls the SiO on surface ₂, retain the SiO leaking trenched side-wall ₂, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, deposit doping content is 1 ~ 5 × 10 ²⁰cm ^-3n-type Ploy-Si, filled up by groove, chemico-mechanical polishing (CMP) method removes substrate surface unnecessary Ploy-Si, forms nmos device and leaks bonding pad; Utilize wet etching, etch away the layer SiO on surface ₂and SiN;

17 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiO ₂and layer of sin, again form barrier layer; Photoetching nmos device grid window, utilizes dry etch process, etches the gate groove that the degree of depth is 0.4 ~ 0.6 μm; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of 5 ~ 8nm in substrate surface deposit a layer thickness ₂, form nmos device gate dielectric layer, then utilizing chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si, nmos device gate groove is filled up, then gets rid of nmos device gate groove with outer surface part Poly-Si and HfO ₂, form nmos device grid, source region, finally form nmos device; Utilize wet etching, etch away the layer SiO on surface ₂and SiN;

18 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiO ₂, photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, is the SiO of 10 ~ 15nm in substrate surface deposit a layer thickness ₂be the Poly-Si of 200 ~ 300nm with a layer thickness, photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device; Carry out P type ion implantation to PMOS device, forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

19 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3 ~ 5nm ₂, dry etching falls the SiO on substrate surface ₂, retain the SiO of Ploy-Si sidewall ₂, form PMOS device gate electrode side wall; Carry out P type ion implantation to PMOS device active area again, autoregistration generates source region and the drain region of PMOS device, makes source-drain area doping content reach 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3;

20 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit SiO ₂layer, with chemico-mechanical polishing (CMP) method flat surface, then uses dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; By physical vapor deposition (PVD) deposit W-TiN composite grid, remove surface metal with chemico-mechanical polishing (CMP), the stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form grid, finally form PMOS device;

21 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit SiO ₂layer, lithography fair lead, metallization, splash-proofing sputtering metal, photoetching goes between, and forms the strain BiCMOS integrated device based on three polycrystal SiGe HBT that MOS conducting channel is 22 ~ 45nm.

Further, described nmos device channel length determines according to the P type strain SiGe layer thickness of the 13 step deposit, and get 22 ~ 45nm, PMOS device channel length is controlled by photoetching process.

Further, maximum temperature involved in this preparation method determines to chemical vapor deposition (CVD) technological temperature in the 21 step according to the 9th step, and maximum temperature is less than or equal to 780 DEG C.

Further, base thickness decides according to the epitaxy layer thickness of the 9th step SiGe, gets 20 ~ 60nm.

Another object of the present invention is to the preparation method that a kind of strain BiCMOS integrated circuit based on three polycrystal SiGe HBT is provided, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1a) choosing doping content is 5 × 10 ¹⁴cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 800 DEG C, annealing 90min activator impurity, forms N-type heavy doping buried region;

Step 2, implementation method prepared by isolated area is:

(2a) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁶cm ^-3si layer, thickness is 2 μm, as collector region;

(2b) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

Step 3, implementation method prepared by collector contact district is:

(3a) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, answer deposit a layer thickness to be the SiO of 200nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector contact area;

(3d) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation;

Step 4, implementation method prepared by base contact is:

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 DEG C, is the SiO of 20nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 600 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm;

Step 5, implementation method prepared by base material is:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) wet etching is utilized, to SiO in window ₂layer carries out excessive erosion, forms region, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm;

Step 6, implementation method prepared by emitter region is:

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 600 DEG C, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

(6c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector electrode, and again phosphorus injection is carried out to this region, to improve the doping content of the Poly-Si in collector electrode, make it reach 1 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer;

(6e) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer, anneal 120s at 950 DEG C of temperature, activator impurity;

(6f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 7, implementation method prepared by MOS device epitaxial material is:

(7a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.92 μm;

(7b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type Si epitaxial loayer of 1.0 μm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁹cm ^-3, as nmos device drain region;

(7c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type strained sige layer of 5nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is 10%, as the first N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained sige layer of 45nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁶cm ^-3, Ge component is gradient distribution, and lower floor is 10%, and upper strata is 30%, as nmos device channel region;

(7e) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type strained sige layer of 5nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is 30%, as the second N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the N-type Si layer of 400nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁹cm ^-3, as nmos device source region;

(7g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂;

(7h) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the shallow slot that the degree of depth is 140nm;

(7i) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one N-type relaxation Si layer in the shallow slot of PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3, thickness is 120nm;

(7j) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, selective growth one N-type strained sige layer in the shallow slot of PMOS device active area, doping content is 5 × 10 ¹⁶cm ^-3, Ge component is 10%, and thickness is 20nm;

(7k) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, selective growth one intrinsic relaxation Si cap layers in the shallow slot of PMOS device active area, thickness is 5nm, forms N trap;

(7l) utilize wet etching, etch away the layer SiO on surface ₂;

Step 8, nmos device leaks the implementation method connecting preparation and is:

(9a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.5 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, form barrier layer;

(8e) photoetching nmos device leaks groove, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.6 μm;

(8f) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, form nmos device and leak trenched side-wall isolation, dry etching falls the SiO on surface ₂, retain the SiO leaking trenched side-wall ₂;

(8g) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Ploy-Si, nmos device is leaked groove and fills up;

(8h) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak bonding pad;

(8i) utilize wet etching, etch away the layer SiO on surface ₂and SiN;

Step 9, the implementation method that nmos device is formed is:

(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, again form barrier layer;

(9b) photoetching nmos device grid window, utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μm;

(9c) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of 5nm in substrate surface deposit a layer thickness ₂, form nmos device gate dielectric layer;

(9d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si, nmos device gate groove is filled up;

(9e) part Poly-Si and the HfO on nmos device gate groove surface is got rid of again ₂layer, forms nmos device grid, source region, finally forms nmos device;

(9f) utilize wet etching, etch away the SiO on surface ₂and SiN layer;

Step 10, implementation method prepared by the empty grid of PMOS device and source and drain is:

(10a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂;

(10b) photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 600 DEG C, is the SiO of 10nm in substrate surface deposit a layer thickness ₂;

(10c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the Poly-Si of 200nm in substrate surface deposit a layer thickness;

(10d) photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device;

(10e) carry out P type ion implantation to PMOS device, forming doping content is 1 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

(10f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm ₂, dry etching falls the SiO on substrate surface ₂, retain the SiO of Ploy-Si sidewall ₂, form PMOS device gate electrode side wall;

(10g) carry out P type ion implantation to PMOS device active area, autoregistration generates source region and the drain region of PMOS device, makes source-drain area doping content reach 5 × 10 ¹⁹cm ^-3;

Step 11, the implementation method that PMOS device is formed is:

(11a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer, with chemico-mechanical polishing (CMP) method flat surface, then uses dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid;

(11b) the empty grid of wet etching, form a groove at gate electrode place;

(11c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit one deck SiON, thickness is 5nm;

(11d) by physical vapor deposition (PVD) deposit W-TiN composite grid, surface metal is removed with chemico-mechanical polishing (CMP);

(11e) stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form grid, finally form PMOS device;

Step 12, the implementation method forming BiCMOS integrated circuit is:

(12a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer;

(12b) lithography fair lead;

(12c) metallize;

(12d) splash-proofing sputtering metal, photoetching goes between, form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, PMOS device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, form the strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit that MOS conducting channel is 45nm.

tool of the present invention has the following advantages:

1. the present invention prepare based in the strain BiCMOS integrated device of three polycrystal SiGe HBT, take full advantage of the anisotropic characteristic of strain SiGe material stress, introduce compressive strain in the horizontal direction, improve PMOS device hole mobility; Introduce tensile strain in the vertical direction, improve nmos device electron mobility, therefore, this performance such as device frequency and current driving ability is higher than the relaxation SiCMOS device of same size;

2. the present invention is being prepared based in the strain BiCMOS integrated device process of three polycrystal SiGe HBT, adopt selective epitaxial technology, respectively at nmos device and PMOS device active area selective growth strain SiGe material, improve the flexibility of device layout, enhance cmos device and integrated circuit electric property;

3. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, the channel direction of nmos device is vertical direction, raceway groove is strained sige layer prepared by chemical vapor deposition (CVD) method, the thickness of SiGe layer is the channel length of nmos device, therefore, in the preparation of nmos device, avoid the photoetching of small size grid, decrease process complexity, reduce cost;

4. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, the raceway groove of nmos device is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

5. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, nmos device raceway groove Ge component changes in gradient, therefore can produce at channel direction the built-in field that is accelerated electron transport, enhance the carrier transport ability of raceway groove, thus improve frequency characteristic and the current driving ability of strain SiGe nmos device;

6. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, nmos device have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of nmos device, enhance the electric property of nmos device;

7. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, PMOS device is quantum well devices, namely strain SiGe channel layer is between Si cap layers and body Si layer, compared with surface channel device, this device can reduce channel interface scattering effectively, improves device electrology characteristic; Meanwhile, quantum well can make the problem in hot electron injection grid medium improve, and adds the reliability of device and circuit;

8. the present invention prepare based in the strain BiCMOS integrated device structure of three polycrystal SiGe HBT, PMOS device adopt SiON replace traditional pure SiO ₂do gate medium, not only increase the reliability of device, and utilize the change of gate medium dielectric constant, improve the grid-control ability of device;

9. the maximum temperature that the present invention relates in preparation is based on the strain BiCMOS integrated device process of three polycrystal SiGe HBT is 800 DEG C, lower than the technological temperature causing strain SiGe channel stress relaxation, therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

10. the present invention's preparation is based in the strain BiCMOS integrated device process of three polycrystal SiGe HBT, PMOS device have employed metal gate mosaic technology (damasceneprocess) and prepares gate electrode, this gate electrode is metal W-TiN composite construction, due to the TiN of lower floor and strain Si and strain SiGe material work functions difference less, improve the electrology characteristic of device, the W on upper strata then can reduce the resistance of gate electrode, achieves the optimization of gate electrode;

11. the present invention prepare based in the strain BiCMOS integrated device process of three polycrystal SiGe HBT, SiGeHBT adopts Fully self-aligned process, efficiently reduces dead resistance and electric capacity, improves electric current and the frequency characteristic of device;

12. the present invention prepare based in the strain BiCMOS integrated device process of three polycrystal SiGe HBT, the emitter of SiGeHBT, base stage and collector electrode all adopt polycrystalline, polycrystalline can partly be produced on above oxide layer, reduce the area of device active region, thus reduction device size, improve the integrated level of circuit.

Accompanying drawing explanation

Fig. 1 is the strain BiCMOS integrated device of the present invention three polycrystal SiGe HBT and the realization flow figure of circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of strain BiCMOS integrated device based on three polycrystal SiGe HBT, described two strain plane BiCMOS integrated device adopts three polycrystal SiGe HBT, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS device.

As a prioritization scheme of the embodiment of the present invention, described nmos device conducting channel is strain SiGe material, is tensile strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, described PMOS device conducting channel is strain SiGe material, is compressive strain along channel direction.

As a prioritization scheme of the embodiment of the present invention, described nmos device conducting channel is hollow, and channel direction is vertical with substrate surface.

As a prioritization scheme of the embodiment of the present invention, the emitter of SiGeHBT device, base stage and collector electrode all adopt polysilicon contact.

As a prioritization scheme of the embodiment of the present invention, its preparation process adopts self-registered technology, and is whole plane structure.

Referring to accompanying drawing 1, technological process prepared by the strain BiCMOS integrated device and circuit that the present invention is based on three polycrystal SiGe HBT is described in further detail.

Embodiment 1: prepare the strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit that conducting channel is 45nm, concrete steps are as follows:

Step 1, epitaxial growth.

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 800 DEG C, annealing 90min activator impurity, forms N-type heavy doping buried region.

Step 2, prepared by isolated area.

(2e) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation.

Step 3, prepared by collector contact district.

(3b) photoetching collector contact district window;

(3d) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation.

Step 4, prepared by base contact.

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm.

Step 6, prepared by emitter region.

(6f) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 7, prepared by MOS device epitaxial material.

(7l) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, nmos device leaks and connects preparation.

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

(8i) utilize wet etching, etch away the layer SiO on surface ₂and SiN.

Step 9, nmos device is formed.

(9f) utilize wet etching, etch away the SiO on surface ₂and SiN layer.

Step 10, the empty grid of PMOS device and source and drain preparation.

(10d) photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device;

(10g) carry out P type ion implantation to PMOS device active area, autoregistration generates source region and the drain region of PMOS device, makes source-drain area doping content reach 5 × 10 ¹⁹cm ^-3.

Step 11, PMOS device is formed.

(11b) the empty grid of wet etching, form a groove at gate electrode place;

(11e) stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form grid, finally form PMOS device.

Step 12, forms BiCMOS integrated circuit.

(12b) lithography fair lead;

(12c) metallize;

Embodiment 2: preparing conducting channel is strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choosing doping content is 1 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 900 DEG C, annealing 60min activator impurity, forms N-type heavy doping buried region.

Step 2, prepared by isolated area.

(2a) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 5 × 10 ¹⁶cm ^-3si layer, thickness is 2.5 μm, as collector region;

(2b) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 4 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂;

Step 3, prepared by collector contact district.

(3a) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, answer deposit a layer thickness to be the SiO of 240nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector contact area;

(3d) by substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 700 DEG C, is the SiO of 30nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 300nm, and doping content is 5 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 700 DEG C, at substrate surface deposit SiO ₂layer, thickness is 300nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in substrate surface deposit one SiN layer, thickness is 80nm;

(4f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit layer of sin layer, thickness is 15nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in base regioselectivity growth SiGe base, Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3, thickness is 40nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 700 DEG C, at substrate surface deposit Poly-Si, thickness is 300nm;

(6c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector electrode, and again phosphorus injection is carried out to this region, to improve the doping content of the Poly-Si in collector electrode, make it reach 5 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer;

(6e) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer, anneal 60s at 1000 DEG C of temperature, activator impurity.

Step 7, prepared by MOS device epitaxial material.

(7a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.52 μm;

(7b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type Si epitaxial loayer of 0.8 μm at nmos device active area selective growth thickness, doping content is 8 × 10 ¹⁹cm ^-3, as nmos device drain region;

(7c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type strained sige layer of 4nm at nmos device active area selective growth thickness, doping content is 3 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained sige layer 4 of 30nm at nmos device active area selective growth thickness, doping content is 1 × 10 ¹⁷cm ^-3, Ge component is gradient distribution, and lower floor is 10%, and upper strata is 20%, as nmos device channel region;

(7e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type strained sige layer of 4nm at nmos device active area selective growth thickness, doping content is 3 × 10 ¹⁸cm ^-3, Ge component is 20%, as the second N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7f) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the N-type Si layer of 300nm at nmos device active area selective growth thickness, doping content is 8 × 10 ¹⁹cm ^-3, as nmos device source region;

(7g) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂;

(7h) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the shallow slot that the degree of depth is 120nm;

(7i) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one N-type relaxation Si layer in the shallow slot of PMOS device active area, doping content is 1 × 10 ¹⁷cm ^-3, thickness is 100nm;

(7j) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, selective growth one N-type strained sige layer in the shallow slot of PMOS device active area, doping content is 1 × 10 ¹⁷cm ^-3, Ge component is 20%, and thickness is 15nm;

(7k) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, selective growth one intrinsic relaxation Si cap layers in the shallow slot of PMOS device active area, thickness is 4nm, forms N trap;

(7l) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, nmos device leaks and connects preparation.

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.4 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, form barrier layer;

(8e) photoetching nmos device leaks groove, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.5 μm;

(8f) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂, form nmos device and leak trenched side-wall isolation, dry etching falls the SiO on surface ₂, retain the SiO leaking trenched side-wall ₂;

(8g) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Ploy-Si, nmos device is leaked groove and fills up;

(8i) utilize wet etching, etch away the layer SiO on surface ₂and SiN.

Step 9, nmos device is formed.

(9a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, again form barrier layer;

(9b) photoetching nmos device grid window, utilizes dry etch process, etches the gate groove that the degree of depth is 0.5 μm;

(9c) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of 6nm in substrate surface deposit a layer thickness ₂, form nmos device gate dielectric layer;

(9d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si, nmos device gate groove is filled up;

(9f) utilize wet etching, etch away the SiO on surface ₂and SiN layer.

Step 10, the empty grid of PMOS device and source and drain preparation.

(10a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂;

(10b) photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 700 DEG C, is the SiO of 12nm in substrate surface deposit a layer thickness ₂;

(10c) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the Poly-Si of 240nm in substrate surface deposit a layer thickness;

(10d) photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device;

(10e) carry out P type ion implantation to PMOS device, forming doping content is 3 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

(10f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 4nm ₂, dry etching falls the SiO on substrate surface ₂, retain the SiO of Ploy-Si sidewall ₂, form PMOS device gate electrode side wall;

(10g) carry out P type ion implantation to PMOS device active area, autoregistration generates source region and the drain region of PMOS device, makes source-drain area doping content reach 8 × 10 ¹⁹cm ^-3.

Step 11, PMOS device is formed.

(11a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer, with chemico-mechanical polishing (CMP) method flat surface, then uses dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid;

(11b) the empty grid of wet etching, form a groove at gate electrode place;

(11c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit one deck SiON, thickness is 3nm;

Step 12, forms BiCMOS integrated circuit.

(12a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer;

(12b) lithography fair lead;

(12c) metallize;

(12d) splash-proofing sputtering metal, photoetching goes between, form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, PMOS device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, form the strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit that MOS conducting channel is 30nm.

Embodiment 3: prepare the strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit that conducting channel is 22nm, concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choosing doping content is 5 × 10 ¹⁵cm ^-3p type Si sheet, as substrate;

(1b) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(1c) photoetching buried region, carries out the injection of N-type impurity to buried region, and at 950 DEG C, annealing 30min activator impurity, forms N-type heavy doping buried region.

Step 2, prepared by isolated area.

(2a) remove the oxide layer of excess surface, epitaxial growth one deck doping content is 1 × 10 ¹⁷cm ^-3si layer, thickness is 3 μm, as collector region;

(2b) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2c) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 5 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂;

Step 3, prepared by collector contact district.

(3a) utilize the method for chemical vapor deposition (CVD), at 800 DEG C, answer deposit a layer thickness to be the SiO of 300nm on epitaxial si layer surface ₂layer;

(3b) photoetching collector contact district window;

(3c) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector contact area;

(3d) by substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 DEG C, is the SiO of 40nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 400nm, and doping content is 1 × 10 ²¹cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in substrate surface deposit one SiN layer, thickness is 100nm;

(4f) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 20nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3, thickness is 60nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 800 DEG C, at substrate surface deposit Poly-Si, thickness is 400nm;

(6c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector electrode, and again phosphorus injection is carried out to this region, to improve the doping content of the Poly-Si in collector electrode, make it reach 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer;

(6e) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer, anneal 15s at 1100 DEG C of temperature, activator impurity.

Step 7, prepared by MOS device epitaxial material.

(7a) photoetching nmos device active area, utilizes dry etch process, etches in nmos device active area the deep trouth that the degree of depth is 1.02 μm;

(7b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type Si epitaxial loayer of 0.5 μm at nmos device active area selective growth thickness, doping content is 1 × 10 ²⁰cm ^-3, as nmos device drain region;

(7c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type strained sige layer of 3nm at nmos device active area selective growth thickness, doping content is 1 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained sige layer of 22nm at nmos device active area selective growth thickness, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is gradient distribution, and lower floor is 10%, and upper strata is 25%, as nmos device channel region;

(7e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type strained sige layer of 3nm at nmos device active area selective growth thickness, doping content is 1 × 10 ¹⁸cm ^-3, Ge component is 25%, as the second N-type lightly-doped source drain structure (N-LDD) layer of nmos device;

(7f) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the N-type Si layer of 200nm at nmos device active area selective growth thickness, doping content is 1 × 10 ²⁰cm ^-3, as nmos device source region;

(7g) method of chemical vapor deposition (CVD) is utilized, at 780 DEG C, at substrate surface deposit one deck SiO ₂;

(7h) photoetching PMOS device active area, utilizes dry etch process, etches in PMOS device active area the shallow slot that the degree of depth is 100nm;

(7i) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, selective growth one N-type relaxation Si layer in the shallow slot of PMOS device active area, doping content is 5 × 10 ¹⁷cm ^-3, thickness is 90nm;

(7j) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, selective growth one N-type strained sige layer in the shallow slot of PMOS device active area, doping content is 5 × 10 ¹⁷cm ^-3, Ge component is 30%, and thickness is 10nm;

(7k) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, selective growth one intrinsic relaxation Si cap layers in the shallow slot of PMOS device active area, thickness is 3nm, forms N trap;

(7l) utilize wet etching, etch away the layer SiO on surface ₂.

Step 8, nmos device leaks and connects preparation.

(8a) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 780 DEG C, deposit one SiO ₂layer;

(8b) photoetching PMOS device source and drain isolated area, utilizes dry etch process, etches in PMOS device source and drain isolated area the shallow slot that the degree of depth is 0.3 μm;

(8c) utilize chemical vapor deposition (CVD) method, at 780 DEG C, in shallow slot, fill SiO ₂, form source and drain shallow-trench isolation;

(8d) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, form barrier layer;

(8e) photoetching nmos device leaks groove, utilizes dry etch process, etches the leakage groove that the degree of depth is 0.4 μm;

(8f) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at substrate surface deposit one deck SiO ₂, form nmos device and leak trenched side-wall isolation, dry etching falls the SiO on surface ₂, retain the SiO leaking trenched side-wall ₂;

(8g) utilizing chemical vapor deposition (CVD) method, at 780 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Ploy-Si, nmos device is leaked groove and fills up;

(8i) utilize wet etching, etch away the layer SiO on surface ₂and SiN.

Step 9, nmos device is formed.

(9a) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂and layer of sin, again form barrier layer;

(9b) photoetching nmos device grid window, utilizes dry etch process, etches the gate groove that the degree of depth is 0.4 μm;

(9c) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of 8nm in substrate surface deposit a layer thickness ₂, form nmos device gate dielectric layer;

(9d) utilizing chemical vapor deposition (CVD) method, at 780 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3n-type Poly-Si, nmos device gate groove is filled up;

(9f) utilize wet etching, etch away the SiO on surface ₂and SiN layer.

Step 10, the empty grid of PMOS device and source and drain preparation.

(10a) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at nmos device surfaces of active regions deposit one deck SiO ₂;

(10b) photoetching PMOS device active area, utilizes chemical vapor deposition (CVD) method, at 780 DEG C, is the SiO of 15nm in substrate surface deposit a layer thickness ₂;

(10c) utilizing chemical vapor deposition (CVD) method, at 780 DEG C, is the Poly-Si of 300nm in substrate surface deposit a layer thickness;

(10d) photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device;

(10e) carry out P type ion implantation to PMOS device, forming doping content is 5 × 10 ¹⁸cm ^-3p type lightly-doped source drain structure (P-LDD);

(10f) utilize chemical vapor deposition (CVD) method, at 780 DEG C, deposit a layer thickness is on the surface of a substrate the SiO of 3nm ₂, dry etching falls the SiO on substrate surface ₂, retain the SiO of Ploy-Si sidewall ₂, form PMOS device gate electrode side wall;

(10g) carry out P type ion implantation to PMOS device active area, autoregistration generates source region and the drain region of PMOS device, makes source-drain area doping content reach 1 × 10 ²⁰cm ^-3.

Step 11, PMOS device is formed.

(11a) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at substrate surface deposit SiO ₂layer, with chemico-mechanical polishing (CMP) method flat surface, then uses dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid;

(11b) the empty grid of wet etching, form a groove at gate electrode place;

(11c) utilize chemical vapor deposition (CVD) method, at 780 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5nm;

Step 12, forms BiCMOS integrated circuit.

(12a) chemical vapor deposition (CVD) method is utilized, at 780 DEG C, at substrate surface deposit SiO ₂layer;

(12b) lithography fair lead;

(12c) metallize;

(12d) splash-proofing sputtering metal, photoetching goes between, form nmos device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, PMOS device drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, form the strain BiCMOS integrated device based on three polycrystal SiGe HBT and circuit that MOS conducting channel is 22nm.

The strain BiCMOS integrated device based on three polycrystal SiGe HBT that the embodiment of the present invention provides and preparation method's tool have the following advantages:

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1., based on a preparation method for the strain BiCMOS integrated device of three polycrystal SiGe HBT, it is characterized in that, comprise the steps:

13 step, photoetching nmos device active area, utilize dry etch process, the deep trouth that the degree of depth is 1.02 ~ 1.92 μm is etched in nmos device active area, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, continuous growth five layer materials in deep trouth: ground floor to be thickness the be N-type Si epitaxial loayer of 0.5 ~ 1.0 μm, doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as nmos device drain region; The N-type strained sige layer of the second layer to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, Ge component is 10%, as the first N-type lightly-doped source drain structure (N-LDD) layer of nmos device; The P type strained sige layer of third layer to be thickness be 22 ~ 45nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3, Ge component is gradient distribution, and lower floor is 10%, and upper strata is the gradient distribution of 20 ~ 30%, as nmos device channel region; The N-type strained sige layer of the 4th layer of to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, Ge component is 20 ~ 30%, as the second N-type lightly-doped source drain structure (N-LDD) layer of nmos device; The N-type Si layer of layer 5 to be thickness be 200 ~ 400nm, doping content is 5 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, as nmos device source region;

20 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit SiO ₂layer, with chemico-mechanical polishing (CMP) method flat surface, then uses dry etch process etching surface SiO ₂to empty grid upper surface, expose empty grid; The empty grid of wet etching, form a groove at gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600 ~ 780 DEG C, at substrate surface deposit one deck SiON, thickness is 1.5 ~ 5nm; By physical vapour deposition (PVD) (PVD) deposit W-TiN composite grid, surface metal is removed with chemico-mechanical polishing (CMP), stop layer using W-TiN composite grid as chemico-mechanical polishing (CMP), thus form grid, finally form PMOS device;

2. preparation method according to claim 1, is characterized in that, described nmos device channel length is determined according to the P type strain SiGe layer thickness of the 13 step deposit, and get 22 ~ 45nm, PMOS device channel length is controlled by photoetching process.

3. preparation method according to claim 1, is characterized in that, base thickness decides according to the epitaxy layer thickness of the 9th step SiGe, gets 20 ~ 60nm.

4., based on a preparation method for the strain BiCMOS integrated circuit of three polycrystal SiGe HBT, it is characterized in that, comprise the steps:

Step 1, epitaxially grown implementation method is:

Step 2, implementation method prepared by isolated area is:

Step 3, implementation method prepared by collector contact district is:

(3b) photoetching collector contact district window;

Step 4, implementation method prepared by base contact is:

Step 5, implementation method prepared by base material is:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

Step 6, implementation method prepared by emitter region is:

Step 7, implementation method prepared by MOS device epitaxial material is:

(7l) utilize wet etching, etch away the layer SiO on surface ₂;

(8i) utilize wet etching, etch away the layer SiO on surface ₂and SiN;

Step 9, the implementation method that nmos device is formed is:

(9f) utilize wet etching, etch away the SiO on surface ₂and SiN layer;

(10d) photoetching Poly-Si and SiO ₂, form the empty grid of PMOS device;

Step 11, the implementation method that PMOS device is formed is:

(11b) the empty grid of wet etching, form a groove at gate electrode place;

(11d) by physical vapour deposition (PVD) (PVD) deposit W-TiN composite grid, surface metal is removed with chemico-mechanical polishing (CMP);

Step 12, the implementation method forming BiCMOS integrated circuit is:

(12b) lithography fair lead;

(12c) metallize;