CN102738176B - A kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and preparation method - Google Patents

Abstract

The invention discloses and a kind ofly prepare strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and preparation method, its process is: SOI substrate grows N-Si as bipolar device collector region, photoetching base, at base region growing P-SiGe, i-Si, i-Poly-Si, preparation deep trench isolation, form emitter, base stage and collector electrode, form SiGe HBT device; At Grown strain SiGe material, form NMOS and PMOS device active area, prepare pseudo-grid, autoregistration generates the source-drain area of NMOS and PMOS device, removes pseudo-grid, prepares grid, photoetching goes between, and forms the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit; The method takes full advantage of the feature of sige material hole mobility higher than common Si material, prepares SOI SiGe BiCMOS integrated circuit, existing simulation and hybrid digital-analog integrated circuit performance is obtained and significantly improves.

Description

A kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and preparation method.

Background technology

Semiconductor integrated circuit technology is the core technology of high-tech and information industry, become the important symbol of measurement national science technical merit, overall national strength and a defense force, the key of to take integrated circuit as the microelectric technique of representative be then semiconductor technology.Semiconductor industry is the infrastructural industries of country, and why it develops so fast, and except technology itself is to except the tremendous contribution of economic development, also application is relevant widely with it.

One of Intel (Intel) founder Gordon mole (a Gordon Moore) proposed " Moore's Law " in nineteen sixty-five, and this theorem is pointed out: the transistor size in integrated circuit (IC) chip, and within about every 18 months, increase by 1 times, performance also promotes 1 times.For many years, world semiconductor industry follows this law all the time and constantly advances, and especially Si base integrated circuit technique, is developed so far, and whole world number, with the equipment of trillion dollars and Technical investment, has made Si base technique define very powerful industry ability.The global information summit that on February 23rd, 2004, Intel CEO Ke Laigebeiruite held in Tokyo represents, Moore's Law will be still effective at following 15 to 20 years, but the technology dynamics that promotion Moore's Law moves on is: the characteristic size constantly reducing chip.At present, external 45nm technology has entered the large-scale production stage, and 32nm technical office is in the introduction period, and according to ITRS ITRS, next node is 22nm.

But, along with the continuation of integrated circuit technique develops, the characteristic size of chip constantly reduces, in the microminiaturized process of Si chip fabrication industry, be faced with Material Physics attribute, manufacturing process technology, the challenge of the aspect limit such as device architecture.Such as when characteristic size is less than below 100nm due to the problem such as tunneling leakage and reliability, traditional gate dielectric material SiO ₂the requirement of low-power consumption cannot be met; The short-channel effect of nano-device and narrow-channel effect are obvious all the more, have had a strong impact on device performance; Traditional photoetching technique cannot meet the lithographic accuracy day by day reduced.Therefore traditional Si base process devices is more and more difficult to the needs meeting design.

Further develop needs, a large amount of researchers conducting in-depth research in new construction, new material and new technology in order to what meet semiconductor technology, and have made great progress in the application in some field.These new constructions and new material are greatly improved to device performance, can meet integrated circuit technique and continue to meet the needs that " mole theorem " develop rapidly.

SOI(Silicon-On-Insulator, the silicon in dielectric substrate) technology be at the bottom of top layer silicon and backing between introduce one deck and bury oxide layer.By forming semiconductive thin film on insulator, SOI material is provided with the incomparable advantage of body silicon; Achieve the medium isolation of components and parts in integrated circuit, completely eliminate the parasitic latch-up in Bulk CMOS circuit; The integrated circuit adopting this material to make also has that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantages such as low voltage and low power circuits, therefore can say that SOI will likely become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.In addition, SOI material is also used to manufacture mems optical switch, as utilized body silicon Machining Technology.

Summary of the invention

The object of the invention is to utilize and prepare strain SiGe planar channeling PMOS device, strain SiGe planar channeling nmos device and bipolar transistor on a substrate slice, form plane BiCMOS integrated device, to realize the optimization of device and performance of integrated circuits.

The object of the present invention is to provide a kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate, nmos device and PMOS device are strain SiGe MOS device, and bipolar device is the two polycrystal SiGe HBT of SOI.

Further, PMOS device adopts quantum well structure.

Further, all device substrate are SOI material.

Further, the emitter of SiGe HBT device and base stage adopt polycrystalline silicon material.

Further, the base of SiGe HBT device is sige material.

Another object of the present invention is to the preparation method that a kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate is provided, comprise the steps:

The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100 ~ 150nm, and N-type doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3sOI substrate sheet;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, at Grown Si epitaxial loayer, thickness is 250 ~ 300nm, and N-type is adulterated, and doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3, as collector region;

3rd step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm, and at substrate surface growth trilaminate material: ground floor is SiGe layer, and Ge component is 15 ~ 25%, thickness is the doping of 20 ~ 60nm, P type, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, as base; The second layer is unadulterated intrinsic layer si layer, and thickness is 10 ~ 20nm; Third layer is unadulterated intrinsic Poly-Si layer, and thickness is 200 ~ 300nm, as base stage and emitter region;

4th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in deep trouth, fills SiO ₂;

5th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180 ~ 300nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

6th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215 ~ 325nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

7th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching base region, carries out p type impurity injection to this region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area;

8th step, photoetching emitting area, carry out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3, form emitter region;

9th step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area.And to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT device;

Tenth step, photoetching MOS active area, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, grow materials at two layers continuously in this active area: the N-type SiGe epitaxial loayer of ground floor to be thickness be 10 ~ 15nm, this layer of Ge component is 15 ~ 30%, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3; The intrinsic relaxation type Si cap layers of the second layer to be thickness be 3 ~ 5nm;

11 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in extension material surface deposit a layer thickness ₂layer; Photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 1 ~ 5 × 10 ¹⁷cm ^-3; Photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 1 ~ 5 × 10 ¹⁷cm ^-3;

12 step, utilize wet etching, etch away the SiO on surface ₂layer, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, the intrinsic Poly-Si layer of to be the SiN layer of 3 ~ 5nm in substrate surface deposit a layer thickness as gate medium and a layer thickness be 300 ~ 500nm, photoetching Poly-Si grid and gate medium, form the pseudo-grid that 22 ~ 350nm is long;

13 step, utilize ion implantation, carry out N-type and P type ion implantation respectively to nmos device active area and PMOS device active area, form N-type lightly-doped source drain structure (N-LDD) and P type lightly-doped source drain structure (P-LDD), doping content is 1 ~ 5 × 10 ¹⁸cm ^-3;

14 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 5 ~ 15nm in substrate surface deposit a layer thickness ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains the SiO of Poly-Si grid and gate medium side ₂, form side wall;

15 step, make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device; Make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device; By substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

16 step, use chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, thickness is 300 ~ 500nm, utilizes chemico-mechanical polishing (CMP) technology, by SiO ₂be planarized to gate surface;

17 step, utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking, grow at substrate surface the lanthana (La that a layer thickness is 2 ~ 5nm ₂o ₃); At substrate surface sputtering layer of metal tungsten (W), finally utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing;

18 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, superficial growth one deck SiO ₂layer, lithography fair lead;

19 step, metallization, photoetching nmos device and PMOS device lead-in wire, form drain electrode, source electrode and grid and SiGe HBT emitter, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that conducting channel is 22 ~ 350nm.

Determine to chemical vapor deposition (CVD) technological temperature in the 19 step according to the 3rd step based on maximum temperature involved in the strain SiGe planar S i base BiCMOS integrated device manufacture process of SOI substrate further, in this preparation method, maximum temperature is less than or equal to 800 DEG C.

Further, base thickness decides according to the epitaxy layer thickness of the 3rd step SiGe, gets 20 ~ 60nm.

Another object of the present invention is to the preparation method that a kind of strain SiGe planar S i base BiCMOS integrated circuit based on SOI substrate is provided, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 150nm, and upper layer of material is doping content is 1 × 10 ¹⁶cm ^-3n-type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 250nm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

(1c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(1d) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(1e) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1f) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, this layer of Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 10nm;

(1h) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm;

Step 2, implementation method prepared by device deep trench isolation is:

(2a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5um;

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation;

Step 3, implementation method prepared by collector electrode shallow-trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation;

Step 4, implementation method prepared by base stage shallow-trench isolation is:

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carries out impurity activation, forms SiGe HBT;

Step 6, the implementation method that MOS is prepared active area is:

(6a) photoetching MOS active area;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, be the N-type SiGe epitaxial loayer of 10nm at active region growth thickness, this layer of Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(6c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the intrinsic relaxation type Si cap layers of 3nm at active region growth thickness;

Step 7, the implementation method that nmos device and PMOS device are formed is:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at the SiO of Grown one deck 300nm ₂;

(7b) photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 1 × 10 ¹⁷cm ^-3;

(7c) photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 1 × 10 ¹⁷cm ^-3;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the SiN layer of 3nm in superficial growth a layer thickness;

(7e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, SiN layer grows the polysilicon of one deck 300nm;

(7f) photoetching Poly-Si grid and gate medium, forms the pseudo-grid that 22nm is long;

(7g) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and form N-type lightly-doped source drain structure (N-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7h) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and form P type lightly-doped source drain structure (P-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7i) at substrate surface, chemical vapor deposition (CVD) method is utilized, at 600 DEG C, growth one deck SiO ₂, thickness is 10nm, utilizes dry etch process photoetching to fall unnecessary SiO subsequently ₂, retain gate lateral wall SiO ₂, form side wall;

(7j) make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device;

(7k) make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device;

(7l) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation;

Step 8, implementation method prepared by grid is:

(8a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂layer, SiO ₂thickness is 300nm thickness;

(8b) utilize chemico-mechanical polishing (CMP) method, effects on surface carries out being planarized to gate level;

(8c) utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking;

(8d) grow at substrate surface the lanthana (La that a layer thickness is 2nm ₂o ₃);

(8e) at substrate surface sputtering layer of metal tungsten (W);

(8f) utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing;

Step 9, the implementation method forming BiCMOS integrated circuit is:

(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at superficial growth one deck SiO ₂layer;

(9b) lithography fair lead;

(9c) metallize;

(9d) photoetching lead-in wire, form nmos device and PMOS device drain electrode, source electrode and grid, SiGeHBT bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit that conducting channel is 22nm.

tool of the present invention has the following advantages:

1. what prepared by the present invention have employed light dope source and drain (LDD) structure based in the strain SiGe planar S i base BiCMOS integrated device structure of SOI substrate, restrained effectively the impact of hot carrier on device performance;

2. the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that prepared by the present invention all have employed quantum well structure in PMOS device structure, can effectively hole be limited in SiGe layer, decrease interface scattering, improve the electric properties such as the frequency of device, current driving ability;

3. the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that prepared by the present invention have employed high-K gate dielectric, improves the grid-control ability of MOS device, enhances the electric property of device;

4. the present invention's preparation is 800 DEG C based on the maximum temperature related in the strain SiGe planar S i base BiCMOS integrated device process of SOI substrate, lower than the technological temperature causing strain SiGe channel stress relaxation, therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

5. the present invention prepare based in the strain SiGe planar S i base BiCMOS integrated device of SOI substrate, metal gate mosaic technology (damascene process) is have employed when preparing nmos device and PMOS device gate electrode, tungsten (W) is employed as metal electrode in this technique, reduce the resistance of gate electrode, improve flexibility and the reliability of device layout;

6. the present invention prepare based in the strain SiGe planar S i base BiCMOS integrated device of SOI substrate, bipolar device adopts SOI substrate, collector region thickness is thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and can form two dimensional electric field in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.

Accompanying drawing explanation

Fig. 1 is provided by the invention based on the strain SiGe planar S i base BiCMOS integrated device of SOI substrate and the realization flow figure of circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of strain SiGe planar S i base BiCMOS integrated device based on SOI substrate, nmos device and PMOS device are strain SiGe MOS device, and bipolar device is the two polycrystal SiGe HBT of SOI.

As a prioritization scheme of the embodiment of the present invention, PMOS device adopts quantum well structure.

As a prioritization scheme of the embodiment of the present invention, all device substrate are SOI material.

As a prioritization scheme of the embodiment of the present invention, the emitter of SiGe HBT device and base stage adopt polycrystalline silicon material.

As a prioritization scheme of the embodiment of the present invention, the base of SiGe HBT device is sige material.

Referring to accompanying drawing 1, prepared by being described in further detail based on the strain SiGe planar S i base BiCMOS integrated device of SOI substrate and the technological process of circuit of 22 ~ 350nm channel length to the present invention.

Embodiment 1: preparation channel length is the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and the circuit of 22nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 150nm, and upper layer of material is doping content is 1 × 10 ¹⁶cm ^-3n-type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 250nm, as collector region, this layer of doping content is 1 × 10 ¹⁶cm ^-3;

(1c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(1d) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(1e) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1f) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, this layer of Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 10nm;

(1h) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm.

Step 2, prepared by device deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5um;

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carries out impurity activation, forms SiGe HBT.

Step 6, prepared by MOS active area.

(6a) photoetching MOS active area;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, be the N-type SiGe epitaxial loayer of 10nm at active region growth thickness, this layer of Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(6c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the intrinsic relaxation type Si cap layers of 3nm at active region growth thickness.

Step 7, nmos device and PMOS device are formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at the SiO of Grown one deck 300nm ₂;

(7b) photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 1 × 10 ¹⁷cm ^-3;

(7c) photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 1 × 10 ¹⁷cm ^-3;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the SiN layer of 3nm in superficial growth a layer thickness;

(7e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, SiN layer grows the polysilicon of one deck 300nm;

(7f) photoetching Poly-Si grid and gate medium, forms the pseudo-grid that 22nm is long;

(7g) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and form N-type lightly-doped source drain structure (N-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7h) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and form P type lightly-doped source drain structure (P-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7i) at substrate surface, chemical vapor deposition (CVD) method is utilized, at 600 DEG C, growth one deck SiO ₂, thickness is 10nm, utilizes dry etch process photoetching to fall unnecessary SiO subsequently ₂, retain gate lateral wall SiO ₂, form side wall;

(7j) make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device;

(7k) make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device;

(7l) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation.

Step 8, prepared by grid.

(8a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂layer, SiO ₂thickness is 300nm thickness;

(8b) utilize chemico-mechanical polishing (CMP) method, effects on surface carries out being planarized to gate level;

(8c) utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking;

(8d) grow at substrate surface the lanthana (La that a layer thickness is 2nm ₂o ₃);

(8e) at substrate surface sputtering layer of metal tungsten (W);

(8f) utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing.

Step 9, forms BiCMOS integrated circuit.

(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at superficial growth one deck SiO ₂layer;

(9b) lithography fair lead;

(9c) metallize;

(9d) photoetching lead-in wire, form nmos device and PMOS device drain electrode, source electrode and grid, SiGeHBT bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit that conducting channel is 22nm.

Embodiment 2: preparation channel length is the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and the circuit of 130nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 300nm, and upper layer of material is doping content is 5 × 10 ¹⁶cm ^-3n-type Si, thickness is 120nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 250nm, as collector region, this layer of doping content is 5 × 10 ¹⁶cm ^-3;

(1c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(1d) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(1e) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1f) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiGe layer of 40nm in Grown a layer thickness, and as base, this layer of Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3;

(1g) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 15nm;

(1h) method of chemical vapor deposition (CVD) is utilized, at 700 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 240nm.

Step 2, prepared by device deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 240nm;

(3e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 240nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiN layer of 150nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 260nm;

(4e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 700 DEG C, is the SiO of 400nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 5 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 3 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 1000 DEG C of temperature, annealing 60s, carries out impurity activation, forms SiGe HBT.

Step 6, prepared by MOS active area.

(6a) photoetching MOS active area;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, be the N-type SiGe epitaxial loayer of 12nm at active region growth thickness, this layer of Ge component is 20%, and doping content is 3 × 10 ¹⁶cm ^-3;

(6c) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the intrinsic relaxation type Si cap layers of 4nm at active region growth thickness.

Step 7, nmos device and PMOS device are formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at the SiO of Grown one deck 400nm ₂;

(7b) photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 3 × 10 ¹⁷cm ^-3;

(7c) photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 3 × 10 ¹⁷cm ^-3;

(7d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is the SiN layer of 4nm in superficial growth a layer thickness;

(7e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, SiN layer grows the polysilicon of one deck 400nm;

(7f) photoetching Poly-Si grid and gate medium, forms the pseudo-grid that 130nm is long;

(7g) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and form N-type lightly-doped source drain structure (N-LDD), doping content is 3 × 10 ¹⁸cm ^-3;

(7h) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and form P type lightly-doped source drain structure (P-LDD), doping content is 3 × 10 ¹⁸cm ^-3;

(7i) at substrate surface, chemical vapor deposition (CVD) method is utilized, at 700 DEG C, growth one deck SiO ₂, thickness is 15nm, utilizes dry etch process photoetching to fall unnecessary SiO subsequently ₂, retain gate lateral wall SiO ₂, form side wall;

(7j) make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device;

(7k) make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device;

(7l) by substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation.

Step 8, prepared by grid.

(8a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂layer, SiO ₂thickness is 400nm thickness;

(8b) utilize chemico-mechanical polishing (CMP) method, effects on surface carries out being planarized to gate level;

(8c) utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking;

(8d) grow at substrate surface the lanthana (La that a layer thickness is 4nm ₂o ₃);

(8e) at substrate surface sputtering layer of metal tungsten (W);

(8f) utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing.

Step 9, forms BiCMOS integrated circuit.

(9a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at superficial growth one deck SiO ₂layer;

(9b) lithography fair lead;

(9c) metallize;

(9d) photoetching lead-in wire, form nmos device and PMOS device drain electrode, source electrode and gate metal lead-in wire, SiGe HBT bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit that conducting channel is 130nm.

Embodiment 3: preparation channel length is the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and the circuit of 350nm, and concrete steps are as follows:

Step 1, epitaxial growth.

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 400nm, and upper layer of material is doping content is 1 × 10 ¹⁷cm ^-3n-type Si, thickness is 150nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 300nm, as collector region, this layer of doping content is 1 × 10 ¹⁷cm ^-3;

(1c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(1d) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(1e) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1f) utilizing the method for chemical vapor deposition (CVD), at 750 DEG C, is the SiGe layer of 60nm in Grown a layer thickness, and as base, this layer of Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3;

(1g) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 20nm;

(1h) method of chemical vapor deposition (CVD) is utilized, at 750 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 300nm.

Step 2, prepared by device deep trench isolation.

(2a) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5 μm;

(2d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation.

Step 3, prepared by collector electrode shallow-trench isolation.

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 300nm;

(3e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation.

Step 4, prepared by base stage shallow-trench isolation.

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiN layer of 200nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 325nm;

(4e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation.

Step 5, SiGe HBT is formed.

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 800 DEG C, is the SiO of 500nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to this region, makes contact zone doping content be 1 × 10 ²⁰cm ^-3, form base stage;

(5d); Photoetching emitter region, carries out N-type impurity injection to this region, makes doping content be 5 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to this region, makes collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector electrode;

(5f) to substrate at 1100 DEG C of temperature, annealing 15s, carries out impurity activation, forms SiGe HBT.

Step 6, prepared by MOS active area.

(6a) photoetching MOS active area;

(6b) utilize chemical vapor deposition (CVD) method, at 750 DEG C, be the N-type SiGe epitaxial loayer of 15nm at active region growth thickness, this layer of Ge component is 30%, and doping content is 5 × 10 ¹⁶cm ^-3;

(6c) utilizing chemical vapor deposition (CVD) method, at 750 DEG C, is the intrinsic relaxation type Si cap layers of 5nm at active region growth thickness.

Step 7, nmos device and PMOS device are formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at the SiO of Grown one deck 500nm ₂;

(7b) photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 5 × 10 ¹⁷cm ^-3;

(7c) photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 5 × 10 ¹⁷cm ^-3;

(7d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is the SiN layer of 5nm in superficial growth a layer thickness;

(7e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, SiN layer grows the polysilicon of one deck 500nm;

(7f) photoetching Poly-Si grid and gate medium, forms the pseudo-grid that 350nm is long;

(7g) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and form N-type lightly-doped source drain structure (N-LDD), doping content is 5 × 10 ¹⁸cm ^-3;

(7h) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and form P type lightly-doped source drain structure (P-LDD), doping content is 5 × 10 ¹⁸cm ^-3;

(7i) at substrate surface, chemical vapor deposition (CVD) method is utilized, at 800 DEG C, growth one deck SiO ₂, thickness is 5nm, utilizes dry etch process photoetching to fall unnecessary SiO subsequently ₂, retain gate lateral wall SiO ₂, form side wall;

(7j) make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device;

(7k) make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device;

(7l) by substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation.

Step 8, prepared by grid.

(8a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂layer, SiO ₂thickness is 500nm thickness;

(8b) utilize lanthana (CMP) method, effects on surface carries out being planarized to gate level;

(8c) utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking;

(8d) grow at substrate surface the lanthana (La that a layer thickness is 5nm ₂o ₃);

(8e) at substrate surface sputtering layer of metal tungsten (W);

(8f) utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing.

Step 9, forms BiCMOS integrated circuit.

(9a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at superficial growth one deck SiO ₂layer;

(9b) lithography fair lead;

(9c) metallize;

(9d) photoetching lead-in wire, form nmos device and PMOS device drain electrode, source electrode and gate metal lead-in wire, SiGe HBT bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit that conducting channel is 350nm.

The strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that the embodiment of the present invention provides and preparation method's tool have the following advantages:

1. what prepared by the present invention have employed light dope source and drain (LDD) structure based in the strain SiGe planar S i base BiCMOS integrated device structure of SOI substrate, restrained effectively the impact of hot carrier on device performance;

2. the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that prepared by the present invention all have employed quantum well structure in PMOS device structure, can effectively hole be limited in SiGe layer, decrease interface scattering, improve the electric properties such as the frequency of device, current driving ability;

3. the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that prepared by the present invention have employed high-K gate dielectric, improves the grid-control ability of MOS device, enhances the electric property of device;

4. the present invention's preparation is 800 DEG C based on the maximum temperature related in the strain SiGe planar S i base BiCMOS integrated device process of SOI substrate, lower than the technological temperature causing strain SiGe channel stress relaxation, therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

5. the present invention prepare based in the strain SiGe planar S i base BiCMOS integrated device of SOI substrate, metal gate mosaic technology (damascene process) is have employed when preparing nmos device and PMOS device gate electrode, tungsten (W) is employed as metal electrode in this technique, reduce the resistance of gate electrode, improve flexibility and the reliability of device layout;

6. the present invention prepare based in the strain SiGe planar S i base BiCMOS integrated device of SOI substrate, bipolar device adopts SOI substrate, collector region thickness is thin compared with traditional devices, therefore, there is collector region effect extending transversely in this device, and can form two dimensional electric field in collector region, thus improve reverse breakdown voltage and the Early voltage of this device, under identical breakdown characteristics, there is the characteristic frequency more excellent than traditional devices.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1., based on a preparation method for the strain SiGe planar S i base BiCMOS integrated device of SOI substrate, it is characterized in that, comprise the steps:

The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100 ~ 150nm, and N-type doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3sOI substrate sheet;

Second step, utilize the method for chemical vapor deposition (CVD), at 600 ~ 750 DEG C, at Grown Si epitaxial loayer, thickness is 250 ~ 300nm, and N-type is adulterated, and doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3, as collector region;

3rd step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm, and at substrate surface growth trilaminate material: ground floor is SiGe layer, and Ge component is 15 ~ 25%, thickness is the doping of 20 ~ 60nm, P type, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, as base; The second layer is unadulterated intrinsic layer si layer, and thickness is 10 ~ 20nm; Third layer is unadulterated intrinsic Poly-Si layer, and thickness is 200 ~ 300nm, as base stage and emitter region;

4th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the deep trouth that the degree of depth is 5 μm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in deep trouth, fills SiO ₂;

5th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180 ~ 300nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

6th step, with wet etching fall surface SiO ₂and SiN layer, the method for recycling chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 200 ~ 300nm in substrate surface deposit a layer thickness ₂layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215 ~ 325nm, utilizes chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, in shallow slot, fills SiO ₂;

7th step, with wet etching fall surface SiO ₂and SiN layer, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in substrate surface deposit a layer thickness ₂layer; Photoetching base region, carries out p type impurity injection to photoetching base region, makes base contact regions doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form base contact area;

8th step, photoetching emitting area, carry out N-type impurity injection to photoetching emitting area, makes doping content be 1 × 10 ¹⁷~ 5 × 10 ¹⁷cm ^-3, form emitter region;

9th step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to collector region, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, and to substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation, forms SiGe HBT device;

Tenth step, photoetching MOS active area, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, materials at two layers is grown continuously: the N-type SiGe epitaxial loayer of ground floor to be thickness be 10 ~ 15nm in this active area, N-type SiGe epitaxial loayer Ge component is 15 ~ 30%, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3; The intrinsic relaxation type Si cap layers of the second layer to be thickness be 3 ~ 5nm;

11 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 300 ~ 500nm in extension material surface deposit a layer thickness ₂layer; Photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 1 ~ 5 × 10 ¹⁷cm ^-3; Photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 1 ~ 5 × 10 ¹⁷cm ^-3;

12 step, utilize wet etching, etch away the SiO on surface ₂layer, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, the intrinsic Poly-Si layer of to be the SiN layer of 3 ~ 5nm in substrate surface deposit a layer thickness as gate medium and a layer thickness be 300 ~ 500nm, photoetching Poly-Si grid and gate medium, form the pseudo-grid that 22 ~ 350nm is long;

13 step, utilize ion implantation, respectively N-type and P type ion implantation are carried out to nmos device active area and PMOS device active area, form N-type lightly-doped source drain structure (N-LDD) and P type lightly-doped source drain structure (P-LDD), doping content is 1 ~ 5 × 10 ¹⁸cm ^-3;

14 step, utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is the SiO of 5 ~ 15nm in substrate surface deposit a layer thickness ₂layer, utilizes dry etch process, etches away the SiO on surface ₂layer, retains the SiO of Poly-Si grid and gate medium side ₂, form side wall;

15 step, make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device; Make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device; By substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

16 step, use chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, thickness is 300 ~ 500nm, utilizes chemico-mechanical polishing (CMP) technology, by SiO ₂be planarized to gate surface;

17 step, utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking, grow at substrate surface the lanthana (La that a layer thickness is 2 ~ 5nm ₂o ₃); At substrate surface sputtering layer of metal tungsten (W), finally utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing;

18 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, superficial growth one deck SiO ₂layer, lithography fair lead;

19 step, metallization, photoetching nmos device and PMOS device lead-in wire, form drain electrode, source electrode and grid and SiGeHBT emitter, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate that conducting channel is 22 ~ 350nm.

2. preparation method according to claim 1, it is characterized in that, determine to chemical vapor deposition (CVD) technological temperature in the 19 step according to the 3rd step based on maximum temperature involved in the strain SiGe planar S i base BiCMOS integrated device manufacture process of SOI substrate in this preparation method, maximum temperature is less than or equal to 800 DEG C.

3. preparation method according to claim 1, is characterized in that, base thickness decides according to the epitaxy layer thickness of the 3rd step SiGe, gets 20 ~ 60nm.

4., based on a preparation method for the strain SiGe planar S i base BiCMOS integrated circuit of SOI substrate, it is characterized in that, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1a) choose SOI substrate sheet, this substrate lower layer support material is Si, and intermediate layer is SiO ₂, thickness is 150nm, and upper layer of material is doping content is 1 × 10 ¹⁶cm ^-3n-type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, upper strata Si material grows the N-type epitaxial si layer that a layer thickness is 250nm, as collector region, N-type epitaxial si layer doping content is 1 × 10 ¹⁶cm ^-3;

(1c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(1d) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(1e) photoetching base, utilizes dry etching, etches the region, base that the degree of depth is 200nm;

(1f) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiGe layer of 20nm in Grown a layer thickness, and as base, SiGe layer Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3;

(1g) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, in the unadulterated intrinsic layer si layer of Grown a layer thickness 10nm;

(1h) method of chemical vapor deposition (CVD) is utilized, at 600 DEG C, at the unadulterated intrinsic Poly-Si layer of Grown a layer thickness 200nm;

Step 2, implementation method prepared by device deep trench isolation is:

(2a) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(2b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(2c) deep trench isolation region between lithographic device, goes out at deep trench isolation region dry etching the shallow slot that the degree of depth is 5um;

(2d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂, form device deep trench isolation;

Step 3, implementation method prepared by collector electrode shallow-trench isolation is:

(3a) SiO on surface is fallen with wet etching ₂and SiN layer;

(3b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(3c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(3d) photoetching collector electrode shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 180nm;

(3e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form collector electrode shallow-trench isolation;

Step 4, implementation method prepared by base stage shallow-trench isolation is:

(4a) SiO on surface is fallen with wet etching ₂and SiN layer;

(4b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 200nm in substrate surface deposit a layer thickness ₂layer;

(4c) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiN layer of 100nm in substrate surface deposit a layer thickness;

(4d) photoetching base stage shallow trench isolation areas, goes out at shallow trench isolation areas dry etching the shallow slot that the degree of depth is 215nm;

(4e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in shallow slot, fill SiO ₂, form base stage shallow-trench isolation;

Step 5, the implementation method that SiGe HBT is formed is:

(5a) SiO on surface is fallen with wet etching ₂and SiN layer;

(5b) utilizing the method for chemical vapor deposition (CVD), at 600 DEG C, is the SiO of 300nm in substrate surface deposit a layer thickness ₂layer;

(5c) photoetching base region, carries out p type impurity injection to photoetching base region, makes contact zone doping content be 1 × 10 ¹⁹cm ^-3, form base stage;

(5d) photoetching emitter region, carries out N-type impurity injection to photoetching emitter region, makes doping content be 1 × 10 ¹⁷cm ^-3, form emitter region;

(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic layer si layer and the intrinsic Poly-Si layer of collector region, N-type impurity injection is carried out to removal collector region, makes collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector electrode;

(5f) to substrate at 950 DEG C of temperature, annealing 120s, carries out impurity activation, forms SiGe HBT;

Step 6, the implementation method that MOS is prepared active area is:

(6a) photoetching MOS active area;

(6b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, be the N-type SiGe epitaxial loayer of 10nm at active region growth thickness, N-type SiGe epitaxial loayer Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(6c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the intrinsic relaxation type Si cap layers of 3nm at active region growth thickness;

Step 7, the implementation method that nmos device and PMOS device are formed is:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at the SiO of Grown one deck 300nm ₂;

(7b) photoetching PMOS device active area, carries out N-type ion implantation to PMOS device active area, makes its doping content reach 1 × 10 ¹⁷cm ^-3;

(7c) photoetching nmos device active area, utilizes ion implantation technology to carry out P type ion implantation to nmos device region, and form nmos device active area P trap, P trap doping content is 1 × 10 ¹⁷cm ^-3;

(7d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is the SiN layer of 3nm in superficial growth a layer thickness;

(7e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, SiN layer grows the polysilicon of one deck 300nm;

(7f) photoetching Poly-Si grid and gate medium, forms the pseudo-grid that 22nm is long;

(7g) photoetching nmos device active area, carries out N-type ion implantation to nmos device active area, and form N-type lightly-doped source drain structure (N-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7h) photoetching PMOS device active area, carries out P type ion implantation to PMOS device active area, and form P type lightly-doped source drain structure (P-LDD), doping content is 1 × 10 ¹⁸cm ^-3;

(7i) at substrate surface, chemical vapor deposition (CVD) method is utilized, at 600 DEG C, growth one deck SiO ₂, thickness is 10nm, utilizes dry etch process photoetching to fall unnecessary SiO subsequently ₂, retain gate lateral wall SiO ₂, form side wall;

(7j) make PMOS device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of PMOS device;

(7k) make nmos device active area by lithography, utilize ion implantation technique autoregistration to form the source-drain area of nmos device;

(7l) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation;

Step 8, implementation method prepared by grid is:

(8a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂layer, SiO ₂thickness is 300nm thickness;

(8b) utilize chemico-mechanical polishing (CMP) method, effects on surface carries out being planarized to gate level;

(8c) utilize wet etching to be removed completely by dummy grid, leave the autoregistration impression that grid in oxide layer are stacking;

(8d) grow at substrate surface the lanthana (La that a layer thickness is 2nm ₂o ₃);

(8e) at substrate surface sputtering layer of metal tungsten (W);

(8f) utilize chemico-mechanical polishing (CMP) technology by the tungsten (W) beyond area of grid and lanthana (La ₂o ₃) removing;

Step 9, the implementation method forming BiCMOS integrated circuit is:

(9a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at superficial growth one deck SiO ₂layer;

(9b) lithography fair lead;

(9c) metallize;

(9d) photoetching lead-in wire, form nmos device and PMOS device drain electrode, source electrode and grid, SiGeHBT bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, form the strain SiGe planar S i base BiCMOS integrated device based on SOI substrate and circuit that conducting channel is 22nm.