CN104241373B - Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof - Google Patents
Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof Download PDFInfo
- Publication number
- CN104241373B CN104241373B CN201410438228.9A CN201410438228A CN104241373B CN 104241373 B CN104241373 B CN 104241373B CN 201410438228 A CN201410438228 A CN 201410438228A CN 104241373 B CN104241373 B CN 104241373B
- Authority
- CN
- China
- Prior art keywords
- junctions
- stratotype
- anticlinal
- source region
- hetero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 230000005641 tunneling Effects 0.000 title abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000012190 activator Substances 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 208000032750 Device leakage Diseases 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 238000002353 field-effect transistor method Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses an anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and a preparation method thereof. The TFET comprises a tunneling source region, a channel region, a drain region and a control grid located above the channel region, wherein an electronic band structure of a heterogeneous tunneling junction of the tunneling source region and an electronic band structure of a heterogeneous tunneling junction of the channel region are respectively an anti-staggered-layer heterojunction. If the TFET is an N type device, the bottom of a conduction band of the tunneling source region is located below the valence band top of the channel region at the juncture surface of the heterogeneous tunneling junction of the tunneling source region and the heterogeneous tunneling junction of the channel region; if the TFET is a P type device, the valence band top of the tunneling source region is located above the bottom of a conduction band of the channel region. Thus, on-state currents of the TFET can be remarkably increased; meanwhile, off-state currents of the device are effectively suppressed, and a steep subthreshold slope is maintained. According to the preparation method of the TFET, a low-power dissipation integrated circuit formed by TFETs is prepared by effectively using a standard process, production cost is greatly reduced, and the process is simple.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), specifically relate to
And a kind of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor and preparation method thereof.
Background technology
Since integrated circuit is born, microelectronics integrated technology constantly develops according to " Moore's Law " always, semiconductor device
Part size constantly reduces.Enter deep sub-micron range with semiconductor device, existing MOSFET element is due to by self-propagating
The conduction mechanism drifting about is limited, sub-threshold slope limited by thermoelectrical potential kT/q and cannot with reducing of device size together
Step reduces.This results in MOSFET element leakage current and reduces the requirement being unable to reach device dimensions shrink, the energy of whole chip
Consumption constantly rises, and chip power-consumption density is increased dramatically, and seriously hinders the integrated development of chip system.In order to adapt to integrated circuit
Development trend, the R and D work of novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor
(TFET, Tunneling Field-Effect Transistor) adopts the new conduction mechanism of band-to-band-tunneling (BTBT), is a kind of non-
Often there is the Novel low power consumption device being suitable to system integration application development of development potentiality.TFET controls source and ditch by gate electrode
At road interface, the tunnelling width of tunnel junctions is so that source valence-band electrons are tunneling to channel conduction band (or raceway groove valence-band electrons tunnelling
To source conduction band) form tunnelling current.This new conduction mechanism breaks through heat in conventional MOS FET sub-threshold slope theoretical limit
The restriction of potential kT/q, it is possible to achieve less than the super steep sub-threshold slope of 60mV/dec, reduce device static leakage current and then
Reduce device quiescent dissipation.
But, because quasiconductor band-to-band-tunneling efficiency is low, the ON state current of TFET ratio compared with existing MOSFET is relatively low,
The requirement in system integration application can not be met.Therefore, while keeping more steep sub-threshold slope, improve TFET ON state
Electric current, is a very important problem needing in the application of TFET device to solve.
Content of the invention
For solving the problems, such as above-mentioned prior art, the present invention provides a kind of anticlinal stratotype hetero-junctions resonance tunnel-through field effect
Answer transistor and preparation method thereof.This tunneling field-effect transistor can significantly improve the ON state electricity of tunneling field-effect transistor
Stream, effective suppression device off-state current, keeps more steep sub-threshold slope simultaneously.
The technical scheme that the present invention provides is as follows：
A kind of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, including tunnelling source region, channel region, drain region be located at
Control gate above channel region, forms heterogeneous tunnel junctions at the interface with channel region for the tunnelling source region, this heterogeneous tunnel junctions
Band structure is anticlinal stratotype hetero-junctions.The band structure of anticlinal stratotype hetero-junctions is as shown in Fig. 1-1.
Above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor can be N-type device or P-type device.For N-type
For device,, at the heterogeneous tunnel junctions interface of tunnelling source region and channel region, the conduction band bottom of tunnelling source region is in raceway groove for it
Below the top of valence band in area, that is, the electron affinity of tunnelling area material is more than channel region material electron affinity and energy gap
Sum, tunnelling source region is p-type heavy doping, and drain region is N-type heavy doping, and channel region is lightly doped for p-type；And for P-type device,
At its heterogeneous tunnel junctions interface, the top of valence band of tunnelling source region is in more than the conduction band bottom of channel region, i.e. channel region material
Electron affinity is more than tunnelling area material electron affinity and energy gap sum, and tunnelling source region is N-type heavy doping, and drain region is
P-type heavy doping, channel region is lightly doped for N-type.
For above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, when it is N-type device, its tunnelling source region
For p-type heavy doping, its doping content is about 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, and its doping content is about
1E18cm-3-1E19cm-3, channel region is lightly doped for p-type, and its doping content is about 1E13cm-3-1E15cm-3；And working as it is p-type
During device, tunnelling source region is N-type heavy doping, and its doping content is about 1E18cm-3-1E20cm-3, drain region is p-type heavy doping, its
Doping content is about 1E18cm-3-1E19cm-3, channel region is lightly doped for N-type, and its doping content is about 1E13cm-3-1E15cm-3.
The present invention provide anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor can apply to Si, Ge it is also possible to
It is applied to other any II-VI that can form anticlinal stratotype heterostructure band structure, the binary of III-V or IV-IV race or three
First compound semiconductor materials.And, for N-type device, the electron affinity of tunnelling area material is more than channel region material
Material electron affinity and energy gap sum；And for P-type device, the electron affinity of channel region material is more than tunnelling source
Area's material electronicses affinity and energy gap sum.
A kind of preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, comprises the following steps：
1) one layer of oxide and one layer of nitride are deposited on a semiconductor substrate in order；
2) carry out shallow trench isolation (Shallow Trench Isolation, STI) after photoetching, and deposit isolated material filling out
Carry out chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) after filling deep hole；
3) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure；
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region；
5) growth selection tunnelling source region compound semiconductor, forms the heterogeneous tunnel junctions of anticlinal stratotype with channel region, simultaneously right
Tunnelling source region carries out adulterating in situ；
6) photoetching exposes drain region, with photoresist and grid as mask, carries out ion implanting and forms drain region；
7) quick high-temp annealing activator impurity；
8) finally enter the consistent later process of same CMOS, including depositing passivation layer, opening contact hole and metallization etc., that is,
Anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor can be obtained.
For the preparation method of above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, step 1) in quasiconductor
Substrate is to be lightly doped or unadulterated Semiconductor substrate, and one embodiment of the invention is in step 1) in using lightly doped quasiconductor lining
Bottom, its doping content is about 1E13cm-3-1E15cm-3.Wherein, the material of Semiconductor substrate can be II-VI, III-V or IV-
Silicon (SOI) in the binary of IV race or ternary semiconductor, insulator or one kind of the germanium (GOI) on insulator.
Preferably, step 3) in gate dielectric material be SiO2、Si3N4Or high-K gate dielectric material.Preferably, step 3) in
The method of deposit gate dielectric material is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
Preferably, step 3) in grid material be DOPOS doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or gold
Belong to the silicide of nickel.
In the preparation method of above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, the specific embodiment of the present invention
In step 5) pass through molecular beam epitaxy growth selection tunnelling source region compound semiconductor；The material of tunnelling source region compound semiconductor
Material is selected from can be with the semiconductor substrate materials in channel region material (i.e. step 1)) form anticlinal stratotype heterostructure band structure
Si, Ge, or II-VI, the binary of III-V and IV-IV race or ternary semiconductor material.Step 5) tunnelling source region is entered
Row adulterates in situ, and its doping content is about 1E18cm-3-1E20cm-3.Step 6) carry out ion implanting formation drain region, wherein, note
The concentration entering ion is about 1E18cm-3-1E19cm-3.
The anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor that the present invention provides can be N-type device or P-type device.
In above-mentioned preparation method, for N-type device, the electron affinity of tunnelling source region compound semiconductor materials is more than channel region
Material electronicses affinity and energy gap sum；And for P-type device, the electron affinity of channel region material is more than tunnelling
Area material electron affinity and energy gap sum.
The method have the benefit that：
Compared with existing TFET, the anticlinal stratotype hetero-junctions tunneling field-effect transistor that the present invention provides passes through device junction
Structure designs, and significantly increases device ON state current, effectively inhibits device off-state current simultaneously, maintain steep subthreshold value oblique
Rate.Taking N-type device as a example：
1st, tunnelling source region and channel region are different materials, form the heterogeneous tunnel junctions of anticlinal stratotype at interface, and heterogeneous
At junction interface, the conduction band bottom of tunnelling source region is located at below the top of valence band of channel region, as Fig. 1-1a) as shown in.
2nd, device is in although the top of valence band of the conduction band bottom of tunnelling source region and channel region forms energy window during OFF state, but
Be p-type heavy doping tunnelling source region conduction band be empty state it is impossible to produce source region conduction band to channel region valence band band-to-band-tunneling；Ditch simultaneously
Road area valence-band electrons need to cross larger potential barrier and get to source region, and device off-state current very little, thus avoid normal mistake
TFET device leakage current very big problem during stratotype orientation, such as Fig. 1-2 a) as shown in.
3rd, gate electrode adds positive voltage, and raceway groove can carry drop-down, and channel region forms a triangular quantum well at tunnel junctions, works as source
When overlapping at area's valence band, channel region valence band and channel region conduction band three, there is resonance tunnel-through at tunnel junctions, device is opened,
More steep subthreshold swing, such as Fig. 1-2 b can be obtained) as shown in.
4th, increase with grid voltage, between source region valence band, channel region valence band and channel region conduction band, tunnelling width reduces, when both sides tunnel
Wear efficiency close when, resonance tunnel-through efficiency is increased dramatically, and tunnelling probability levels off to 1, obtains the ON state of larger tunneling transistor
Electric current.
The anticlinal stratotype hetero-junctions tunneling field-effect transistor preparation process is simple of the present invention, can be effectively integrated in CMOS
Integrated TFET device in circuit, the low power consumption integrated circuit can also being made up of TFET using standard technology preparation, is greatly dropped
Low production cost, simplifies technological process.
Brief description
Fig. 1 is the structural representation of the present invention anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor；
Fig. 1-1 is the anticlinal stratotype band structure schematic diagram of N/P type anticlinal stratotype hetero-junctions resonant tunneling thin film tunnel junctions；
Wherein：A) for the band structure of the anticlinal stratotype of N-type anticlinal stratotype hetero-junctions resonant tunneling thin film tunnel junctions；B) it is
The band structure of the anticlinal stratotype of p-type anticlinal stratotype hetero-junctions resonant tunneling thin film tunnel junctions；
Fig. 1-2 is N-type anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor fundamental diagram；
Wherein：A) for the band structure at tunnel junctions during device OFF state；B) be device ON state when tunnel junctions at can carry knot
Structure；
Fig. 2 is the device profile map being formed on a semiconductor substrate after removing nitride after STI isolates；
Fig. 3 is photoetching and etches the device profile map after forming grid；
Fig. 4 exposes the source region of TFET device for photoetching and etches device profile map after source region；
After Fig. 5 is the heterogeneous source region of extension growth selection, and tunnelling source region is carried out with the device profile map after adulterating in situ；
Fig. 6 exposes the drain region of TFET device for photoetching and ion implanting forms the device profile map behind drain region；
In Fig. 1～Fig. 6：
1- Semiconductor substrate (channel region)；2-STI isolates；
3- dielectric layer；4- grid；
5- photoresist；6- heterogeneous tunnelling source region；
7- drain region；The passivation layer of 8- later process；
The metal of 9- later process.
Specific embodiment
Below in conjunction with accompanying drawing, by specific embodiment, the present invention is described further.
The anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor that the present invention provides, its structure is as shown in figure 1, include tunnel
The control gate 4 worn source region 6, channel region 1, drain region 7 and be located at channel region 1 top, wherein, tunnelling source region 6 is heterogeneous with channel region 1
The band structure of tunnel junctions is anticlinal stratotype hetero-junctions, as shown in Fig. 1-1, wherein：A) it is that N-type anticlinal stratotype hetero-junctions resonates
The band structure of the anticlinal stratotype of tunneling transistor tunnel junctions；B) it is p-type anticlinal stratotype hetero-junctions resonant tunneling thin film tunnel junctions
The band structure of anticlinal stratotype；.
Above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor can be N-type device or P-type device.For N-type
For device, at its heterogeneous tunnel junctions interface, the conduction band bottom of tunnelling source region 6 is in below the top of valence band of channel region 1, that is,
The electron affinity of tunnelling source region 6 material is more than channel region 1 material electronicses affinity and energy gap sum, and tunnelling source region 6 is P
Type heavy doping, drain region 7 is N-type heavy doping, and channel region 1 is lightly doped for p-type；And for P-type device, its heterogeneous tunnelling is made friends with
The top of valence band of interface tunnelling source region 6 is in more than the conduction band bottom of channel region 1, i.e. the electron affinity of channel region 1 material
More than tunnelling source region 6 material electronicses affinity and energy gap sum, tunnelling source region 6 is N-type heavy doping, and drain region 7 is that p-type is heavily doped
Miscellaneous, channel region 1 is lightly doped for N-type.
Fig. 1-2 is N-type anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor fundamental diagram.When device is in OFF state
When although the top of valence band of the conduction band bottom of tunnelling source region and channel region forms energy window, but the leading of p-type heavy doping tunnelling source region
Carry as empty state it is impossible to produce source region conduction band to the band-to-band-tunneling of channel region valence band；Channel region valence-band electrons need to cross relatively simultaneously
Big potential barrier gets to source region, device off-state current very little, thus TFET device leakage when avoiding normal staggered floor type orientation
The very big problem of electric current, such as Fig. 1-2 a) as shown in.When gate electrode plus positive voltage, raceway groove can carry drop-down, and channel region is at tunnel junctions
Form a triangular quantum well, when overlapping at source region valence band, channel region valence band and channel region conduction band three, at tunnel junctions
There is resonance tunnel-through, device is opened, it is possible to obtain more steep subthreshold swing, such as Fig. 1-2 b) as shown in.
For above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, when it is N-type device, its tunnelling source region
6 is p-type heavy doping, and its doping content is about 1E18cm-3-1E20cm-3, drain region 7 is N-type heavy doping, and its doping content is about
1E18cm-3-1E19cm-3, channel region 1 is lightly doped for p-type, and its doping content is about 1E13cm-3-1E15cm-3；And working as it is p-type
During device, tunnelling source region 6 is N-type heavy doping, and its doping content is about 1E18cm-3-1E20cm-3, drain region 7 is p-type heavy doping,
Its doping content is about 1E18cm-3-1E19cm-3, channel region 1 is lightly doped for N-type, and its doping content is about 1E13cm-3-
1E15cm-3.
The anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor that the present invention provides can apply to InAs/GaSb and partly leads
Body material it is also possible to be applied to the II-VI that other can form anticlinal stratotype heterostructure band structure, III-V and IV-IV race
Binary or ternary semiconductor material.And, it is desirable to the electron affinity of tunnelling area material for N-type device
More than channel region material electron affinity and energy gap sum；And it is desirable to the electronics of channel region material for P-type device
Affinity is more than tunnelling area material electron affinity and energy gap sum.
The preparation side of above-mentioned anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, below, is described taking N-type device as a example
Method, the preparation of p-type anticlinal stratotype hetero-junctions resonance tunnel-through FET device is similar to therewith., above-mentioned taking N-type device as a example
The implementation steps of the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as shown in Fig. 2～Fig. 6, including：
1st, in substrate doping for (about 1E13cm is lightly doped-3-1E15cm-3), crystal orientation is<001>GaSb substrate 1
Upper deposit layer of silicon dioxide, thickness about 10nm, and deposit one layer of silicon nitride (Si3N4), thickness about 100nm, afterwards
Isolate 2 using shallow-trench isolation fabrication techniques active area STI, then carry out CMP, as shown in Figure 2.
2nd, the silicon dioxide on surface is removed in drift, then deposits one layer of gate dielectric layer 3, and gate dielectric layer is Al2O3, thickness be 1～
5nm；Grid material 4 is deposited using LPCVD, grid material is doped polysilicon layer, thickness is 50～200nm.Make gate figure by lithography, carve
Erosion grid material 4 until gate dielectric layer 3, as shown in Figure 3.
3rd, photoetching exposes source region, goes out hetero-junctions tunnelling source region using high selectivity dry etching, junction depth about 50nm, such as
Shown in figure -4.
4th, heterogeneous source region 6 is formed using molecular beam epitaxy growth selection InAs quasiconductor, source region is carried out in situ simultaneously
Doping (about 1E20cm-3), as shown in figure -5.
5th, photoetching exposes drain region, and with photoresist 5 and grid 4 as mask, (As, dosage is to carry out drain region 7 ion implanting
1E14/cm-2, energy is 20keV, and injection ion concentration is about 1E18/cm-3), as shown in Figure 6.Carry out a quick high-temp to move back
Fire, and implanted dopant is entered with line activating (temperature is 1050 DEG C, and the time is 10s)
6th, finally enter conventional later process, including deposit passivation layer 8, opening contact hole and metallization 9 etc., shown in Fig. 1
The anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor structure schematic diagram of the described N-type for being obtained.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.Any it is familiar with ability
The technical staff in domain, without departing under technical solution of the present invention ambit, can be utilized in the methods and techniques of the disclosure above
Hold and technical solution of the present invention is made with many possible variations and modification, or the Equivalent embodiments being revised as equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention is to made for any of the above embodiments any simple
Modification, equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (8)
1. a kind of preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, this anticlinal stratotype hetero-junctions resonance tunnel
Wear field-effect transistor and include tunnelling source region, channel region, drain region and the control gate above channel region, in described tunnelling source region
With form heterogeneous tunnel junctions at the interface of channel region, the band structure of described heterogeneous tunnel junctions is anticlinal stratotype hetero-junctions, its
Preparation method comprises the following steps：
1) one layer of oxide and one layer of nitride are deposited on a semiconductor substrate in order；
2) carry out shallow trench isolation after photoetching, and deposit isolated material filling deep hole after carry out chemical-mechanical planarization；
3) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure；
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region；
5) growth selection tunnelling source region compound semiconductor, forms the heterogeneous tunnel junctions of anticlinal stratotype with channel region, simultaneously to tunnelling
Source region carries out adulterating in situ；
6) photoetching exposes drain region, with photoresist and grid as mask, carries out ion implanting and forms drain region；
7) quick high-temp annealing activator impurity；
8) pass through later process, including deposit passivation layer, opening contact hole and metallization, anticlinal stratotype hetero-junctions resonance tunnel-through is obtained
Field-effect transistor.
2. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, institute
Stating anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor is N-type device, and described tunnelling source region is p-type heavy doping, described leakage
Area is N-type heavy doping, and described channel region is lightly doped for p-type；At the heterogeneous tunnel junctions interface of described tunnelling source region and channel region,
The conduction band bottom of tunnelling source region is located at below the top of valence band of channel region.
3. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, institute
Stating anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor is P-type device, and described tunnelling source region is N-type heavy doping, and drain region is P
Type heavy doping, channel region is lightly doped for N-type；Described anticlinal stratotype hetero-junctions is located at leading of channel region by the top of valence band of tunnelling source region
More than band bottom.
4. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step
The described Semiconductor substrate in rapid 1) is to be lightly doped or unadulterated Semiconductor substrate, and the material of Semiconductor substrate is II-VI, III-V
Or the silicon SOI on the binary of IV-IV race or ternary semiconductor, the insulator or germanium GOI on insulator.
5. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step
The described Semiconductor substrate in rapid 1) is lightly doped Semiconductor substrate, and doping content is 1E13cm-3～1E15cm-3.
6. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step
The described gate dielectric material in rapid 3) is SiO2、Si3N4Or high-K gate dielectric material；Step 3) described deposit gate dielectric material method be
Thermal oxide, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition；Step 3) described grid material be DOPOS doped polycrystalline silicon, gold
Belong to cobalt, the silicide of metallic nickel, the silicide of metallic cobalt or metallic nickel.
7. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step
Rapid 5) are by molecular beam epitaxy growth selection tunnelling source region compound semiconductor, the material of tunnelling source region compound semiconductor
Selected from Si, Ge, or II-VI, the binary of III-V and IV-IV race or ternary semiconductor material；The leading of described tunnelling source region
Form the heterogeneous tunnel junctions of described anticlinal stratotype with bottom is located at below the top of valence band of described channel region.
8. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step
The doping content of rapid 5) described original position doping is 1E18cm-3～1E20cm-3；Step 6) concentration of described ion implanting is
1E18cm-3～1E19cm-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438228.9A CN104241373B (en) | 2014-08-29 | 2014-08-29 | Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438228.9A CN104241373B (en) | 2014-08-29 | 2014-08-29 | Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241373A CN104241373A (en) | 2014-12-24 |
| CN104241373B true CN104241373B (en) | 2017-02-15 |
Family
ID=52229126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410438228.9A Active CN104241373B (en) | 2014-08-29 | 2014-08-29 | Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241373B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612353A (en) * | 2003-10-31 | 2005-05-04 | 国际商业机器公司 | High mobility heterojunction complementary field effect transistor and method thereof |
| CN1812123A (en) * | 2004-10-29 | 2006-08-02 | 英特尔公司 | Resonant tunneling device using metal oxide semiconductor processing |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9209288B2 (en) * | 2012-12-21 | 2015-12-08 | Intel Corporation | Reduced scale resonant tunneling field effect transistor |
-
2014
- 2014-08-29 CN CN201410438228.9A patent/CN104241373B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612353A (en) * | 2003-10-31 | 2005-05-04 | 国际商业机器公司 | High mobility heterojunction complementary field effect transistor and method thereof |
| CN1812123A (en) * | 2004-10-29 | 2006-08-02 | 英特尔公司 | Resonant tunneling device using metal oxide semiconductor processing |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104241373A (en) | 2014-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104269439B (en) | Embedding layer heterojunction tunneling field effect transistor and manufacturing method thereof | |
| CN103985745B (en) | The tunneling field-effect transistor of suppression output nonlinear unlatching and preparation method | |
| CN103151391B (en) | The short grid tunneling field-effect transistor of vertical non-uniform doped channel and preparation method | |
| CN102184955B (en) | Complementary tunneling field effect transistor and forming method thereof | |
| CN103579324B (en) | A kind of three source tunneling field-effect transistors and preparation method thereof | |
| CN103594376B (en) | A kind of knot modulation type tunneling field-effect transistor and preparation method thereof | |
| CN104465657A (en) | Complementary tfet and manufacturing method thereof | |
| CN103560144B (en) | Suppress the method for tunneling transistor leakage current and corresponding device and preparation method | |
| CN104362095B (en) | A kind of preparation method of tunneling field-effect transistor | |
| CN104347692B (en) | Suppress tunneling field-effect transistor that output nonlinear is opened and preparation method thereof | |
| CN104241374B (en) | Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof | |
| CN108538911A (en) | L-type tunneling field-effect transistor of optimization and preparation method thereof | |
| CN104810405B (en) | A kind of tunneling field-effect transistor and preparation method | |
| CN108321197A (en) | A kind of tunnel field-effect transistor and its manufacturing method | |
| CN104576721B (en) | A kind of tunneling field-effect transistor with electric field localization effects enhancing ON state current | |
| CN105118858A (en) | A vertical tunneling field effect transistor | |
| CN102324434B (en) | Schottky barrier metal oxide semiconductor (MOS) transistor and preparation method thereof | |
| CN104332409B (en) | Isolate the preparation method of tunneling field-effect transistor based on deep N-well technique | |
| CN104241373B (en) | Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof | |
| CN105244375B (en) | PNIN/NPIP type SSOI TFET and preparation method with mutation tunnel junctions | |
| CN105390531B (en) | A kind of preparation method of tunneling field-effect transistor | |
| CN106898642B (en) | Super steep averagely subthreshold swing fin tunneling field-effect transistor and preparation method thereof | |
| CN109478562A (en) | Tunneling field-effect transistor and its manufacturing method | |
| CN104241375B (en) | Straddling type heterojunction resonance tunneling field-effect transistor and preparing method thereof | |
| CN103996713A (en) | Vertical-channel double-mechanism conduction nano-wire tunneling transistor and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |