CN104241373B - Anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and preparation method thereof - Google Patents

Abstract

The invention discloses an anti-staggered layer type heterojunction resonant tunneling field effect transistor and a preparation method thereof. The device includes a tunneling source region, a channel region, a drain region and a control gate located above the channel region, wherein the energy band structure of the heterogeneous tunneling junction between the tunneling source region and the channel region is an anti-staggered layer type texture. If it is an N-type device, at the heterogeneous tunnel junction interface between the tunneling source region and the channel region, the bottom of the conduction band of the tunneling source region is below the top of the valence band of the channel region; if it is a P-type device, the tunneling The top of the valence band in the source region is above the bottom of the conduction band in the channel region. The invention can significantly increase the on-state current of the tunneling field effect transistor, effectively suppress the off-state current of the device, and maintain a relatively steep sub-threshold slope. The preparation method effectively utilizes a standard process to prepare a low-power integrated circuit composed of TFETs, greatly reduces the production cost, and has a simple process.

Description

An anti-staggered layer heterojunction resonant tunneling field effect transistor and its preparation method

technical field

The invention belongs to the field of CMOS ultra large scale integrated circuit (ULSI) field effect transistor logic devices, and specifically relates to an anti-staggered layer type heterojunction resonant tunneling field effect transistor and a preparation method thereof.

Background technique

Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, existing MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT/q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip continues to rise, and the power consumption density of the chip increases sharply, which seriously hinders the development of chip system integration. In order to adapt to the development trend of integrated circuits, the development and research work of new ultra-low power consumption devices is particularly important. Tunneling Field-Effect Transistor (TFET, Tunneling Field-Effect Transistor) adopts a new conduction mechanism of band-band tunneling (BTBT), and is a new type of low-power device with great development potential suitable for the development of system integration applications. The TFET controls the tunneling width of the tunneling junction at the interface between the source and the channel through the gate electrode, so that the source valence band electrons tunnel to the channel conduction band (or the channel valence band electrons tunnel to the source conduction band) to form tunneling current. This new conduction mechanism breaks through the limitation of thermoelectric potential kT/q in the theoretical limit of the traditional MOSFET subthreshold slope, and can achieve an ultra-steep subthreshold slope lower than 60mV/dec, reducing the static leakage current of the device and thereby reducing the static power consumption of the device.

However, due to the low tunneling efficiency of the semiconductor band, the on-state current of the TFET is lower than that of the existing MOSFET, which cannot meet the requirements of system integration applications. Therefore, it is a very important problem to be solved in the application of TFET devices to improve the on-state current of TFET while maintaining a relatively steep sub-threshold slope.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides an anti-staggered layer heterojunction resonant tunneling field effect transistor and a preparation method thereof. The tunneling field effect transistor can significantly increase the on-state current of the tunneling field effect transistor, effectively suppress the off-state current of the device, and maintain a relatively steep sub-threshold slope.

The technical scheme provided by the invention is as follows:

An anti-staggered layer type heterojunction resonant tunneling field effect transistor, comprising a tunneling source region, a channel region, a drain region and a control gate located above the channel region, at the interface between the tunneling source region and the channel region A heterogeneous tunneling junction is formed at the position, and the energy band structure of the heterogeneous tunneling junction is an anti-staggered layer heterojunction. The energy band structure of the anti-staggered layer heterojunction is shown in Figure 1-1.

The aforementioned anti-staggered layer heterojunction resonant tunneling field effect transistor may be an N-type device or a P-type device. For an N-type device, at the heterogeneous tunnel junction interface between the tunneling source region and the channel region, the bottom of the conduction band of the tunneling source region is below the top of the valence band of the channel region, that is, the tunneling source The electron affinity of the material in the channel region is greater than the sum of the electron affinity of the material in the channel region and the forbidden band width. The tunneling source region is heavily doped with P type, the drain region is heavily doped with N type, and the channel region is lightly doped with P type. For P-type devices, the top of the valence band of the tunneling source region at the heterogeneous tunneling junction interface is located above the bottom of the conduction band of the channel region, that is, the electron affinity of the channel region material is greater than The sum of electron affinity and forbidden band width of the material of the tunneling source region, the tunneling source region is N-type heavily doped, the drain region is P-type heavily doped, and the channel region is N-type lightly doped.

For the above-mentioned anti-staggered layer type heterojunction resonant tunneling field effect transistor, when it is an N-type device, its tunneling source region is heavily doped with P-type, and its doping concentration is about 1E18cm ^-3 -1E20cm ^-3 , The drain region is N-type heavily doped, its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region is P-type lightly doped, its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 ; When it is a P-type device, the tunnel source region is heavily doped with N type, and its doping concentration is about 1E18cm ^-3 -1E20cm ^-3 , and the drain region is heavily doped with P type, and its doping concentration is about 1E18cm ^-3 - 1E19cm ^-3 , the channel region is N-type lightly doped, and its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 .

The anti-staggered layer heterojunction resonant tunneling field-effect transistor provided by the present invention can be applied to Si and Ge, and can also be applied to any other II-VI, III-V that can form an anti-staggered layer heterojunction energy band structure Or binary or ternary compound semiconductor materials of Group IV-IV. Moreover, for N-type devices, the electron affinity of the material in the tunneling source region is greater than the sum of the electron affinity of the channel region material and the forbidden band width; while for the P-type device, the electron affinity of the channel region material The sum potential is greater than the sum of the electron affinity of the material in the tunneling source region and the forbidden band width.

A method for preparing an anti-staggered layer heterojunction resonant tunneling field effect transistor, comprising the following steps:

1) sequentially depositing a layer of oxide and a layer of nitride on the semiconductor substrate;

2) Perform shallow trench isolation (Shallow Trench Isolation, STI) after photolithography, and deposit isolation material to fill the deep hole, then perform chemical mechanical polishing (CMP);

3) Deposit gate dielectric material and gate material, perform photolithography and etching, and form a gate pattern;

4) Photolithography exposes the tunneling source region and selectively etches the tunneling source region;

5) Selectively grow the compound semiconductor in the tunneling source region to form an anti-staggered layer type heterogeneous tunneling junction with the channel region, and perform in-situ doping on the tunneling source region at the same time;

6) The drain region is exposed by photolithography, and the photoresist and the gate are used as a mask to perform ion implantation to form the drain region;

7) Rapid high-temperature annealing to activate impurities;

8) Finally, it enters the subsequent process consistent with CMOS, including deposition of passivation layer, opening of contact holes and metallization, that is,

An anti-staggered layer type heterojunction resonant tunneling field effect transistor can be produced.

For the preparation method of the above-mentioned anti-staggered layer type heterojunction resonant tunneling field effect transistor, the semiconductor substrate in step 1) is a lightly doped or undoped semiconductor substrate, an embodiment of the present invention is in step 1) A lightly doped semiconductor substrate is used, and its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 . Wherein, the material of the semiconductor substrate may be one of II-VI, III-V or IV-IV group binary or ternary compound semiconductor, silicon on insulator (SOI) or germanium on insulator (GOI).

Preferably, the gate dielectric material in step 3) is SiO ₂ , Si ₃ N ₄ or high-K gate dielectric material. Preferably, the method for depositing the gate dielectric material in step 3) is conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition or physical vapor deposition.

Preferably, the gate material in step 3) is doped polysilicon, metal cobalt, metal nickel, metal cobalt silicide or metal nickel silicide.

In the preparation method of the above anti-staggered layer type heterojunction resonant tunneling field effect transistor, in the specific embodiment of the present invention, in step 5) the compound semiconductor in the tunneling source region is selectively grown by molecular beam epitaxy; the compound semiconductor in the tunneling source region is The material is selected from Si, Ge, or II-VI, III-V and IV-IV groups that can form an anti-staggered layered heterojunction energy band structure with the channel region material (ie, the semiconductor substrate material in step 1) Binary or ternary compound semiconductor materials. Step 5) Perform in-situ doping on the tunneling source region, and its doping concentration is about 1E18cm ⁻³ -1E20cm ⁻³ . Step 6) performing ion implantation to form a drain region, wherein the concentration of implanted ions is about 1E18cm ^-3 -1E19cm ^-3 .

The anti-staggered layer heterojunction resonant tunneling field effect transistor provided by the present invention can be an N-type device or a P-type device. In the above preparation method, for N-type devices, the electron affinity of the compound semiconductor material in the tunneling source region is greater than the sum of the electron affinity of the channel region material and the forbidden band width; and for P-type devices, the channel The electron affinity of the material in the tunneling source region is greater than the sum of the electron affinity of the material in the tunneling source region and the forbidden band width.

The beneficial technical effect of the present invention is:

Compared with the existing TFET, the anti-staggered layer type heterojunction tunneling field effect transistor provided by the present invention significantly increases the on-state current of the device through the design of the device structure, and effectively suppresses the off-state current of the device at the same time, maintaining a steep Straight subthreshold slope. Take N-type devices as an example:

1. The tunneling source region and the channel region are made of different materials, and an anti-staggered layer type heterogeneous tunneling junction is formed at the interface, and the conduction band bottom of the tunneling source region at the heterojunction interface is located at the valence band of the channel region Below the top, as shown in Figure 1-1a).

2. When the device is in the off state, although the conduction band bottom of the tunneling source region and the valence band top of the channel region form an energy window, the conduction band of the P-type heavily doped tunneling source region is empty, and the source region cannot be generated. Band tunneling from the conduction band to the valence band in the channel region; at the same time, the valence band electrons in the channel region need to cross a large potential barrier to reach the source region, and the off-state current of the device is very small, thus avoiding the TFET in the normal cross-layer orientation. The problem of large device leakage current, as shown in Figure 1-2a).

3. A positive voltage is applied to the gate electrode, the energy band of the channel is pulled down, and the channel region forms a triangular potential well at the tunnel junction. When the valence band of the source region, the valence band of the channel region and the conduction band of the channel region overlap , resonant tunneling occurs at the tunneling junction, the device is turned on, and a steeper subthreshold swing can be obtained, as shown in Figure 1-2b).

4. As the gate voltage increases, the tunneling width between the valence band in the source region, the valence band in the channel region, and the conduction band in the channel region decreases. When the tunneling efficiency on both sides is close, the resonant tunneling efficiency increases sharply, and the tunneling The probability is close to 1, and a larger on-state current of the tunneling transistor is obtained.

The anti-staggered layer type heterojunction tunneling field effect transistor of the present invention has a simple preparation process, can effectively integrate TFET devices in CMOS integrated circuits, and can also use standard processes to prepare low-power integrated circuits composed of TFETs, greatly reducing The production cost is reduced and the process flow is simplified.

Description of drawings

Fig. 1 is a structural schematic diagram of an anti-staggered layer heterojunction resonant tunneling field effect transistor of the present invention;

Figure 1-1 is a schematic diagram of the energy band structure of the N/P type anti-staggered layer heterojunction resonant tunneling transistor at the tunneling junction;

Among them: a) is the energy band structure of the N-type anti-staggered layer type heterojunction resonant tunneling transistor tunneling junction anti-staggered layer type; Split-layer energy band structure;

Figure 1-2 is a working principle diagram of an N-type anti-staggered layer heterojunction resonant tunneling field effect transistor;

Where: a) is the energy band structure at the tunnel junction when the device is off; b) is the energy band structure at the tunnel junction when the device is on;

2 is a cross-sectional view of the device after the nitride is removed after the STI isolation is formed on the semiconductor substrate;

3 is a cross-sectional view of the device after photolithography and etching to form the gate;

4 is a cross-sectional view of the device after photolithography exposes the source region of the TFET device and etches the source region;

Fig. 5 is a cross-sectional view of the device after the epitaxial selective growth of the heterogeneous source region and the in-situ doping of the tunneling source region;

6 is a cross-sectional view of the device after photolithography exposes the drain region of the TFET device and ion implants the drain region;

In Figures 1 to 6:

1-semiconductor substrate (channel region); 2-STI isolation;

3-dielectric layer; 4-gate;

5-photoresist; 6-heterogeneous tunneling source region;

7-drain area; 8-passivation layer of subsequent process;

9-Metals in subsequent processes.

detailed description

The present invention will be further described through specific embodiments below in conjunction with the accompanying drawings.

The anti-staggered layer type heterojunction resonant tunneling field effect transistor provided by the present invention has a structure as shown in FIG. Gate 4, wherein the energy band structure of the heterogeneous tunneling junction between the tunneling source region 6 and the channel region 1 is an anti-staggered layer heterojunction, as shown in Figure 1-1, wherein: a) is N-type The energy band structure of the tunneling junction anti-staggered layer type of the anti-staggered layer type heterojunction resonant tunneling transistor; b) the energy band structure of the tunneling junction anti-staggered layer type of the P-type anti-staggered layer type heterojunction resonant tunneling transistor ;.

The aforementioned anti-staggered layer heterojunction resonant tunneling field effect transistor may be an N-type device or a P-type device. For an N-type device, the bottom of the conduction band of the tunneling source region 6 at the heterogeneous tunneling interface is below the top of the valence band of the channel region 1, that is, the electron affinity of the material of the tunneling source region 6 is greater than The sum of the electron affinity and the forbidden band width of the material of the channel region 1, the tunneling source region 6 is heavily doped with P type, the drain region 7 is heavily doped with N type, and the channel region 1 is lightly doped with P type; For a P-type device, the top of the valence band of the tunneling source region 6 at the heterogeneous tunneling interface is located above the bottom of the conduction band of the channel region 1, that is, the electron affinity of the material in the channel region 1 is greater than that of the tunneling region 1. The sum of the material electron affinity and forbidden band width of the tunneling source region 6, the tunneling source region 6 is N-type heavily doped, the drain region 7 is P-type heavily doped, and the channel region 1 is N-type lightly doped.

Figure 1-2 is a working principle diagram of an N-type anti-staggered layer heterojunction resonant tunneling field effect transistor. When the device is in the off state, although the conduction band bottom of the tunneling source region and the valence band top of the channel region form an energy window, the conduction band of the P-type heavily doped tunneling source region is empty, and the source conduction band cannot be generated. The band-band tunneling brought to the valence band of the channel region; at the same time, the valence band electrons in the channel region need to cross a large potential barrier to reach the source region, and the off-state current of the device is very small, thus avoiding the TFET device in the normal cross-layer orientation. The problem of large leakage current, as shown in Figure 1-2a). When a positive voltage is applied to the gate electrode, the energy band of the channel is pulled down, and the channel region forms a triangular potential well at the tunnel junction. When the valence band of the source region, the valence band of the channel region and the conduction band of the channel region overlap, Resonant tunneling occurs at the tunneling junction, the device is turned on, and a steeper subthreshold swing can be obtained, as shown in Figure 1-2b).

For the above-mentioned anti-staggered layer type heterojunction resonant tunneling field effect transistor, when it is an N-type device, its tunneling source region 6 is heavily doped with P-type, and its doping concentration is about 1E18cm ^-3 -1E20cm ^-3 , the drain region 7 is N-type heavily doped, its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region 1 is P-type lightly doped, its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 ; And when it is a P-type device, the tunneling source region 6 is heavily doped with N type, and its doping concentration is about 1E18cm ^-3 -1E20cm ^-3 , and the drain region 7 is heavily doped with P type, and its doping concentration is about 1E18cm ^-3 -1E19cm ^-3 , the channel region 1 is N-type lightly doped, and its doping concentration is about 1E13cm ^-3 -1E15cm ^-3 .

The anti-staggered layer heterojunction resonant tunneling field effect transistor provided by the present invention can be applied to InAs/GaSb semiconductor materials, and can also be applied to other II-VI, III- Binary or ternary compound semiconductor materials of V and IV-IV groups. Moreover, for N-type devices, it is required that the electron affinity of the material in the tunneling source region is greater than the sum of the electron affinity of the channel region material and the forbidden band width; while for the P-type device, it is required that the channel region material has an The electron affinity is greater than the sum of the electron affinity of the material in the tunneling source region and the forbidden band width.

Taking the N-type device as an example, the preparation method of the above-mentioned inverted-staggered-layer heterojunction resonant tunneling field-effect transistor is described below, and the preparation of the P-type inverted-staggered-layer heterojunction resonant tunneling field-effect transistor is similar. Taking an N-type device as an example, the implementation steps of the above-mentioned method for manufacturing an anti-staggered layer heterojunction resonant tunneling field effect transistor are shown in Figures 2 to 6, including:

1. The doping concentration of the substrate is lightly doped (about 1E13cm ^-3 -1E15cm ^-3 ), and the crystal orientation is <001> GaSb substrate 1

Deposit a layer of silicon dioxide on it with a thickness of about 10nm, and deposit a layer of silicon nitride (Si ₃ N ₄ ) with a thickness of about 100nm, and then use shallow trench isolation technology to make STI isolation 2 in the active area, and then perform CMP. as shown in picture 2.

2. Float away the silicon dioxide on the surface, and then deposit a gate dielectric layer 3, the gate dielectric layer is Al ₂ O ₃ , with a thickness of 1-5nm; use LPCVD to deposit the gate material 4, and the gate material is a doped polysilicon layer , the thickness is 50-200nm. The gate pattern is photolithographically etched, and the gate material 4 is etched until the gate dielectric layer 3 , as shown in FIG. 3 .

3. The source region is exposed by photolithography, and the heterojunction tunneling source region is etched by a high selective dry method, with a junction depth of about 50nm, as shown in Figure-4.

4. The InAs semiconductor is selectively grown by molecular beam epitaxy to form the heterogeneous source region 6, and the source region is doped in situ (about 1E20cm ^-3 ), as shown in Figure-5.

5. The drain region is exposed by photolithography, and the drain region 7 is implanted with ions (As, the dose is 1E14/cm ^-2 , the energy is 20keV, and the implanted ion concentration is about 1E18/cm2 using the photoresist 5 and the gate 4 as a mask. ^-3 ), as shown in Figure 6. Perform a rapid high-temperature annealing and activate the implanted impurities (temperature is 1050°C, time is 10s)

6. Finally, enter the conventional subsequent process, including depositing passivation layer 8, opening contact holes, and metallization 9, etc. Figure 1 shows the obtained N-type anti-staggered layer type heterojunction resonant tunneling Schematic diagram of the structure of a field effect transistor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. a kind of preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor, this anticlinal stratotype hetero-junctions resonance tunnel Wear field-effect transistor and include tunnelling source region, channel region, drain region and the control gate above channel region, in described tunnelling source region With form heterogeneous tunnel junctions at the interface of channel region, the band structure of described heterogeneous tunnel junctions is anticlinal stratotype hetero-junctions, its Preparation method comprises the following steps：

1) one layer of oxide and one layer of nitride are deposited on a semiconductor substrate in order；

2) carry out shallow trench isolation after photoetching, and deposit isolated material filling deep hole after carry out chemical-mechanical planarization；

3) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure；

4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region；

5) growth selection tunnelling source region compound semiconductor, forms the heterogeneous tunnel junctions of anticlinal stratotype with channel region, simultaneously to tunnelling Source region carries out adulterating in situ；

6) photoetching exposes drain region, with photoresist and grid as mask, carries out ion implanting and forms drain region；

7) quick high-temp annealing activator impurity；

8) pass through later process, including deposit passivation layer, opening contact hole and metallization, anticlinal stratotype hetero-junctions resonance tunnel-through is obtained Field-effect transistor.

2. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, institute Stating anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor is N-type device, and described tunnelling source region is p-type heavy doping, described leakage Area is N-type heavy doping, and described channel region is lightly doped for p-type；At the heterogeneous tunnel junctions interface of described tunnelling source region and channel region, The conduction band bottom of tunnelling source region is located at below the top of valence band of channel region.

3. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, institute Stating anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor is P-type device, and described tunnelling source region is N-type heavy doping, and drain region is P Type heavy doping, channel region is lightly doped for N-type；Described anticlinal stratotype hetero-junctions is located at leading of channel region by the top of valence band of tunnelling source region More than band bottom.

4. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step The described Semiconductor substrate in rapid 1) is to be lightly doped or unadulterated Semiconductor substrate, and the material of Semiconductor substrate is II-VI, III-V Or the silicon SOI on the binary of IV-IV race or ternary semiconductor, the insulator or germanium GOI on insulator.

5. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step The described Semiconductor substrate in rapid 1) is lightly doped Semiconductor substrate, and doping content is 1E13cm^-3～1E15cm^-3.

6. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step The described gate dielectric material in rapid 3) is SiO₂、Si₃N₄Or high-K gate dielectric material；Step 3) described deposit gate dielectric material method be Thermal oxide, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition；Step 3) described grid material be DOPOS doped polycrystalline silicon, gold Belong to cobalt, the silicide of metallic nickel, the silicide of metallic cobalt or metallic nickel.

7. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step Rapid 5) are by molecular beam epitaxy growth selection tunnelling source region compound semiconductor, the material of tunnelling source region compound semiconductor Selected from Si, Ge, or II-VI, the binary of III-V and IV-IV race or ternary semiconductor material；The leading of described tunnelling source region Form the heterogeneous tunnel junctions of described anticlinal stratotype with bottom is located at below the top of valence band of described channel region.

8. the preparation method of anticlinal stratotype hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, step The doping content of rapid 5) described original position doping is 1E18cm^-3～1E20cm^-3；Step 6) concentration of described ion implanting is 1E18cm^-3～1E19cm^-3.