CN104835840B - Super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and preparation method - Google Patents
Super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and preparation method Download PDFInfo
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Abstract
The invention provides one kind super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and preparation method, belong to field-effect transistor logical device field in cmos vlsi (ULSI).The tunneling field-effect transistor uses the material energy gap of many shell sections in the nano thread structure with core multilayered shell, the structure continuously to increase along nano wire radial direction.The present invention can subthreshold slope degradation phenomena effectively in suppression device transfer characteristic, while significantly reducing the average subthreshold slope of tunneling field-effect transistor, and maintain more steep minimum subthreshold slope.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), specifically relate to
And a kind of super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and preparation method thereof.
Background technology
Since being born from integrated circuit, microelectronics integrated technology is continued to develop according to " Moore's Law " always, semiconductor device
Part size constantly reduces.As semiconductor devices enters deep sub-micron range, conventional MOSFET device is due to by self-propagating
The conduction mechanism of drift is limited, and sub-threshold slope is limited by thermoelectrical potential kT/q and can not be same with the diminution of device size
Step reduces.This results in MOSFET element leakage current and reduces the requirement for being unable to reach device dimensions shrink, the energy of whole chip
Consumption constantly rises, and chip power-consumption density increased dramatically, and seriously hinder the integrated development of chip system.In order to adapt to integrated circuit
Development trend, novel super-low power consuming devices R and D work just seems especially important.Tunneling field-effect transistor
(TFET, Tunneling Field-Effect Transistor), using the new conduction mechanism of band-to-band-tunneling (BTBT), is a kind of non-
Often there is the Novel low power consumption device suitable for system integration application development of development potentiality.TFET controls source and ditch by gate electrode
The tunnelling width of tunnel junctions at road interface so that source valence-band electrons are tunneling to channel conduction band (or raceway groove valence-band electrons tunnelling
To source conduction band) form tunnelling current.This new conduction mechanism breaks through heat in conventional MOS FET sub-threshold slope theoretical limits
Potential kT/q limitation, it is possible to achieve there is super steep sub-threshold slope less than 60mV/dec, device static leakage current is reduced
And then reduce device quiescent dissipation.
But, and unlike conventional MOS FET, subthreshold slope is change in the subthreshold region of TFET transfer curves, and with
Gate voltage increase and gradually increase, this is resulted in TFET transfer characteristics, the subthreshold slope correspondence scope less than 60mV/dec
Smaller, the average subthreshold slope of device is higher, is unfavorable for application of the TFET devices in super low-power consumption field.Therefore, keep steeper
While straight minimum sub-threshold slope, suppress subthreshold slope and degenerate, realize that the super steep subthreshold slope that is averaged is TFET device applications
The problem of one of middle needs solution is extremely important.
The content of the invention
It is an object of the invention to provide super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor and the preparation of one kind
Method.The tunneling field-effect transistor can subthreshold slope degradation phenomena effectively in suppression device transfer characteristic, while significantly drop
The average subthreshold slope of low tunneling field-effect transistor, and maintain more steep minimum subthreshold slope.
The technical scheme that the present invention is provided is as follows：
A kind of super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor, as shown in figure 1, using core-multilayered shell
Nano thread structure, the nano thread structure center section is as the channel region 9 of transistor, and the two ends of nano thread structure are respectively as source
Area 7 and drain region 8, are provided with gate dielectric layer 4 and control gate 5 above nanowire channel area, and the nano thread structure includes sandwich layer
Part 2 and multilayer shell parts 3 (3-1,3-2 ..., 3-n), wherein the material energy gap of many shell sections 3 is along nano wire radius
Direction continuously increases, and innermost layer 3-1 energy gaps are minimum, and outermost layer 3-n energy gaps are maximum, and middle each layer energy gap is continuous
Change.Tunneling transistor channel region 9 is that, undoped with intrinsic region, for N-type device, tunnelling source region is p-type heavy doping, and it is mixed
Miscellaneous concentration is about 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, and its doping concentration is about 1E18cm-3-1E19cm-3；And it is right
For P-type device, tunnelling source region is N-type heavy doping, and its doping concentration is about 1E18cm-3-1E20cm-3, drain region is p-type weight
Doping, its doping concentration is about 1E18cm-3-1E19cm-3。
The energy gap of nano wire multilayered shell in the nanowire tunneling field-effect transistor (being more than three layers) is along nano wire
The variable gradient of radial direction is the important parameter of device design.Energy gap variable gradient is too small, causes outermost material to be prohibited
Bandwidth is narrow, and device off-state current will be caused to increase, minimum sub-threshold slope increase.And energy gap variable gradient is excessive,
Cause outermost material energy gap excessive, cause gate voltage needed for opening band-to-band-tunneling excessive.General warranty most surface layer material
Expect energy gap 0.3eV-0.7eV big compared with core material energy gap.And have in nano wire multilayered shell compared with broad stopband width portion
Divide (part for being more than sandwich layer energy gap about more than 0.3eV) thickness optimization between 5nm-20nm.And nanowire core layer segment
Diameter is general between 5-10nm.
Described tunneling field-effect transistor can apply to SiGe semi-conducting materials, can also be applied to other II-VI,
The binary or ternary semiconductor material of III-V and IV-IV races.
Present invention simultaneously provides the preparation method of described super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor,
Comprise the following steps：
1) substrate prepares：(about 1E13cm is lightly doped on insulating barrier-3-1E15cm-3) or undoped with Semiconductor substrate；
2) etched on substrate and anneal to form nanowire core, and the selective etching insulating barrier below nano wire, etching
Go out groove；
3) extension successively grows atomicity than the source region compound semiconductor along nano wire radial direction consecutive variations, is formed
The nano wire multilayer shell material that energy gap successively increases；
4) gate dielectric material is deposited, grid material is deposited, photoetching and etching is carried out, gate figure is formed；
5) photoetching exposes source region, using photoresist and grid as mask, carries out ion implanting formation source region, and concentration is about
1E18cm-3-1E20cm-3；
6) photoetching exposes drain region, using photoresist and grid as mask, carries out ion implanting formation drain region, and concentration is about
1E18cm-3-1E19cm-3；
7) quick high-temp annealing activator impurity；
8) later process, including deposit passivation layer, opening contact hole and metallization etc. are finally entered, you can be made super steep flat
Equal subthreshold amplitude of oscillation nanowire tunneling field-effect transistor.
Described preparation method, it is characterized in that, step 1) described in semiconductor substrate materials be selected from Si, Ge or other
The binary or ternary semiconductor of II-VI, III-V and IV-IV race；Described insulating layer material is selected from SiO2、Si3N4Or
Hafnium.
Described preparation method, it is characterized in that, step 2) described in nanowire core layer material be selected from have compared with low energy gap
The Ge of width or the binary or ternary semiconductor of other II-VI, III-V and IV-IV race.
Described preparation method, it is characterized in that, step 3) described in nano wire Shell Materials be selected from atomicity than different
SiGe or other II-VI, III-V and IV-IV race binary or ternary semiconductor.
Described preparation method, it is characterized in that, step 4) described in gate dielectric layer material be selected from SiO2、Si3N4Or high K
Gate dielectric material.
Described preparation method, it is characterized in that, step 4) described in growth gate dielectric material method be selected from following side
One of method：Conventional thermal oxidation, nitriding thermal oxidation, atomic layer deposition or chemical vapor deposition.
Described preparation method, it is characterized in that, step 4) described in grid material be selected from DOPOS doped polycrystalline silicon, metallic cobalt, nickel
And other metals or metal silicide.
The technique effect of the present invention (by taking N-type device as an example)：
1st, nano wire is core-multilayer shell structure, and material energy gap successively increases along nano wire radial direction in different layers
Greatly, and at nano wire outermost layer with compared with broad stopband width, have at nanowire core compared with low energy gap width.
2nd, gate electrode adds positive voltage, and raceway groove can band drop-down, the generation band-to-band-tunneling at tunnel junctions, device unlatching.In grid voltage
When smaller, mainly there are the fractional source regions compared with broad stopband width band-to-band-tunneling to occur first at nano wire shell outer layer,
It is hereby achieved that more steep minimum subthreshold swing.
3rd, as grid voltage increases, at nanowire core there is the region portions band-to-band-tunneling compared with low energy gap width to open
Open.For band-to-band-tunneling, small gap material has bigger tunnelling probability relative to wide-band gap material, in identical gate voltage
Bigger band-to-band-tunneling current increment can be obtained under the conditions of increment, it is hereby achieved that more steep average subthreshold slope, has
Imitate the phenomenon that suppression device subthreshold slope increases and degenerated with gate voltage.
4th, simultaneously as having the shell sections compared with broad stopband width to play a leading role in the case of device is just opened, have
Beneficial to the minimum subthreshold slope of reduction, and it effectively prevent off-state current increase, minimum subthreshold caused by low energy gap area material
The phenomenon of slope increase.
Compared with existing TFET, super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor is set by device architecture
Meter, significantly improves device transfer characteristic, effectively reduces the average subthreshold slope of device, and the minimum for maintaining steep is sub-
Threshold slope.
The super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor preparation technology of the present invention is simple, can effectively exist
Integrated TFET devices in CMOS integrated circuits, can also prepare the low power consumption integrated circuit being made up of TFET using standard technology,
Production cost is significantly reduced, technological process is simplified.
Brief description of the drawings
Fig. 1 is the structural representation of the super steep averagely subthreshold amplitude of oscillation nanowire tunneling field-effect transistor of the present invention.
Fig. 2 is the schematic diagram of the Semiconductor substrate on insulating barrier；
Fig. 3 is etching and the device schematic diagram to be formed after nanowire core of annealing；
Fig. 4 is photoetching and selective etching insulating barrier, in the device schematic diagram of nano wire groove formed below；
Fig. 5 (a) is the device schematic diagram formed after the nano wire shell that material energy gap successively increases；Fig. 5 (b) is outer
Prolong nano wire multilayered shell partial schematic diagram of the growth selection atomicity than gradual change；
Fig. 6 (a) is deposit and etches the device schematic diagram to be formed after gate figure；Fig. 6 (b) is cuing open along device channel direction
Face figure；
Fig. 7 be photoetching expose after the source region and ion implanting formation source region of TFET devices along device channel directional profile
Figure；
Fig. 8 photoetching expose behind the drain region of TFET devices and ion implanting formation drain region along device channel directional profile
Figure.
In figure,
1- insulating barriers；2- nanowire core layer materials；3- nano wire multilayers shell material (including innermost layer 3-1, outermost layer 3-n,
And middle each layer)；4- gate mediums；5- grid；6- photoresists；7- source regions；8- drain regions；9- channel regions；The passivation of 10- later process
Layer；The metal of 11- later process.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment to super steep averagely subthreshold amplitude of oscillation nanowire tunneling of the present invention
The implementation of field-effect transistor is described further.
Specific implementation step is as shown in Fig. 2-Fig. 8：(by taking N-type device as an example, P-type device can be by that analogy for this example)
1st, preparing substrate material, is insulator (SiO2) on 1 undoped with, crystal orientation is<001>Ge, as shown in Figure 2.
2nd, photoetching and etch form nanowire core 2, the and (H that annealed2, 900 DEG C, 5min), nanowire core diameter
About 5nm-10nm, as shown in Figure 3.
3rd, using hydrofluoric acid, selective etching forms groove below nanowire core, and depth is about 100nm, as shown in Figure 4.
4th, Si of the extension growth selection atomicity than consecutive variations on nanowire core 21-xGexCompound semiconductor, shape
Into nano wire multilayered shell 3, (x=1 in wherein 3-1 layers, atomicity compares 0 in 3-n layers<x<0.5, middle each layer is closer to device surface
Atomicity is more smaller than x values), shell thickness is about 5nm-20nm, as shown in Figure 5.
5th, using one layer of gate dielectric layer 4 of atomic layer deposition, gate dielectric layer is SiO2, thickness is 1~5nm；Formed sediment using LPCVD
Product grid material 5, grid material is doped polysilicon layer, and thickness is 50~200nm.Make gate figure by lithography, as shown in Figure 6.
6th, photoetching exposes source region, is mask with photoresist 6 and grid 5, and carrying out the ion implanting of source region 7, (impurity concentration is about
1E20cm-3), as shown in Figure 7.
7th, photoetching exposes drain region, is mask with photoresist 6 and grid 5, and carrying out the ion implanting of drain region 8, (impurity concentration is about
1E18cm-3), as shown in Figure 8.
8th, a quick high-temp annealing is carried out, and enters line activating (1050 DEG C, 10s) to implanted dopant.Finally enter routine
Later process, including deposit passivation layer 10, opening contact hole and metallization 11 etc..
Fig. 1 show the super steep averagely subthreshold amplitude of oscillation nanometer threaded list of the obtained N-type prepared based on CMOS IC techniques
Wear field-effect transistor structure schematic diagram.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible variations and modification to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (10)
1. a kind of tunneling field-effect transistor, the tunneling field-effect transistor uses nano thread structure, nano thread structure pars intermedia
The channel region for transistor is allocated as, the two ends of nano thread structure are respectively as source region and drain region, above nanowire channel area
Provided with gate dielectric layer and control gate, it is characterised in that the nano thread structure includes sandwich layer part and many shell sections, wherein many
The material energy gap of shell sections continuously increases along nano wire radial direction, and the energy gap of innermost layer material is minimum, outermost
The energy gap of layer material is maximum, the energy gap consecutive variations of middle layers of material.
2. tunneling field-effect transistor as claimed in claim 1, it is characterised in that tunneling transistor channel region is undoped with this
Area is levied, for N-type device, tunnelling source region is p-type heavy doping, and its doping concentration is 1E18cm-3-1E20cm-3, drain region is N
Type heavy doping, its doping concentration is 1E18cm-3-1E19cm-3；And for P-type device, tunnelling source region is N-type heavy doping,
Its doping concentration is 1E18cm-3-1E20cm-3, drain region is p-type heavy doping, and its doping concentration is 1E18cm-3-1E19cm-3。
3. tunneling field-effect transistor as claimed in claim 1, it is characterised in that the outermost material of many shell sections
Energy gap 0.3eV-0.7eV big compared with core material energy gap.
4. tunneling field-effect transistor as claimed in claim 1, it is characterised in that the sandwich layer section diameter 5-10nm it
Between, the thickness of many shells is between 5nm-20nm.
5. the tunneling field-effect transistor described in claim 1 is applied to SiGe semiconductor material devices, or applied to other II-
The binary or ternary semiconductor material devices of VI, III-V and IV-IV race.
6. the preparation method of tunneling field-effect transistor as claimed in claim 1, comprises the following steps：
1) substrate prepares：Being lightly doped on insulating barrier or undoped with Semiconductor substrate；
2) etched on substrate and anneal to form nanowire core, and the selective etching insulating barrier below nano wire, etch recessed
Groove；
3) extension successively grows atomicity than the compound semiconductor along nano wire radial direction consecutive variations, forms energy gap
The many Shell Materials of nano wire successively increased；
4) gate dielectric material is deposited, grid material is deposited, photoetching and etching is carried out, gate figure is formed；
5) photoetching exposes source region, using photoresist and grid as mask, carries out ion implanting formation source region, concentration is 1E18cm-3-
1E20cm-3；
6) photoetching exposes drain region, using photoresist and grid as mask, carries out ion implanting formation drain region, concentration is 1E18cm-3-
1E19cm-3；
7) high-temperature annealing activation impurity；
8) later process, including deposit passivation layer, opening contact hole and metallization are finally entered, you can super steep averagely subthreshold is made
Amplitude of oscillation nanowire tunneling field-effect transistor.
7. the preparation method described in claim 6, it is characterised in that step 1) described in semiconductor substrate materials be selected from Si, Ge
Or the binary or ternary semiconductor of other II-VI, III-V and IV-IV race；The insulating layer material is selected from SiO2、
Si3N4Or hafnium.
8. the preparation method described in claim 6, it is characterised in that step 2) described in nanowire core layer material be selected from have compared with
The Ge of low energy gap width or the binary or ternary semiconductor of other II-VI, III-V and IV-IV races.
9. the preparation method described in claim 6, it is characterised in that step 3) described in many Shell Materials of nano wire be selected from atom
Number is than different SiGe or the binary or ternary semiconductor of other II-VI, III-V and IV-IV races.
10. the preparation method described in claim 6, it is characterised in that step 4) described in gate dielectric material be selected from SiO2、Si3N4
Or high-K gate dielectric material, the method for the deposit gate dielectric material is selected from one of following method：The hot oxygen of conventional thermal oxidation, nitrating
Change, atomic layer deposition or chemical vapor deposition, the grid material is selected from DOPOS doped polycrystalline silicon, metallic cobalt, nickel and other metals or
Metal silicide.
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| CN106898642B (en) * | 2017-03-13 | 2019-06-07 | 北京大学 | Super steep averagely subthreshold swing fin tunneling field-effect transistor and preparation method thereof |
| CN107248530B (en) * | 2017-06-15 | 2019-09-13 | 北京大学 | A kind of two-dimensional material/heterojunction semiconductor vertical tunneling transistors and preparation method |
| CN107104140B (en) * | 2017-06-15 | 2019-09-13 | 北京大学 | A kind of two-dimensional material/heterojunction semiconductor tunneling transistor and preparation method |
| CN111435682A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Multi-channel gate-all-around transistor |
| CN111435642B (en) * | 2019-01-11 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked semiconductor nanowire structure and preparation method thereof |
| CN111435644B (en) * | 2019-01-11 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | Gate-all-around transistor and preparation method thereof |
| CN111435641B (en) * | 2019-01-11 | 2022-06-24 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked gate-all-around transistor and preparation method thereof |
| CN111435649B (en) * | 2019-01-11 | 2023-12-01 | 中国科学院上海微系统与信息技术研究所 | Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof |
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| CN103985745A (en) * | 2014-04-24 | 2014-08-13 | 北京大学 | Tunneling field-effect transistor capable of restraining nolinear opening of output and preparation method thereof |
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