CN104752497B - A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method - Google Patents
A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The present invention provides a kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation methods, belong to field-effect transistor logical device field in cmos vlsi (ULSI).The tunnelling source region of the tunneling field-effect transistor is multilayered structure, different layers are the semiconductor of energy gap consecutive variations, and energy gap gradually increases along vertical devices surface direction, and wherein lowest level energy gap is minimum, top layer's energy gap is maximum, intermediate each layer energy gap consecutive variations.The present invention can subthreshold slope degradation phenomena effectively in suppression device transfer characteristic, while significantly reducing the average subthreshold slope of tunneling field-effect transistor, and maintain more steep minimum subthreshold slope.
Description
Technical field
The invention belongs to field-effect transistor logical device fields in cmos vlsi (ULSI), specifically relate to
And a kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method thereof of multilayer source structure.
Background technology
Since integrated circuit is born, microelectronics integrated technology is continued to develop according to " Moore's Law " always, semiconductor device
Part size constantly reduces.As semiconductor devices enters deep sub-micron range, conventional MOSFET device is due to by self-propagating
The conduction mechanism of drift is limited, and sub-threshold slope is limited by thermoelectrical potential kT/q and can not be same with the diminution of device size
Step reduces.This results in MOSFET element leakage current to reduce the requirement for being unable to reach device dimensions shrink, the energy of entire chip
Consumption constantly rises, and chip power-consumption density increased dramatically, and seriously hinders the integrated development of chip system.In order to adapt to integrated circuit
Development trend, novel super-low power consuming devices R and D work just seem especially important.Tunneling field-effect transistor
(TFET, Tunneling Field-Effect Transistor) uses band-to-band-tunneling (BTBT) new conduction mechanism, is a kind of non-
Often there is the Novel low power consumption device suitable for system integration application development of development potentiality.TFET controls source and ditch by gate electrode
The tunnelling width of tunnel junctions at road interface so that source valence-band electrons are tunneling to channel conduction band (or raceway groove valence-band electrons tunnelling
To source conduction band) form tunnelling current.This novel conduction mechanism breaks through heat in conventional MOS FET sub-threshold slope theoretical limits
The limitation of potential kT/q may be implemented have super steep sub-threshold slope less than 60mV/dec, reduce device static leakage current
And then reduce device quiescent dissipation.
But unlike conventional MOS FET, subthreshold slope is variation in the subthreshold region of TFET transfer curves, and with
It gate voltage to increase and gradually increase, this is resulted in TFET transfer characteristics, and the subthreshold slope less than 60mV/dec corresponds to range
Smaller, the average subthreshold slope of device is higher, is unfavorable for application of the TFET devices in super low-power consumption field.Therefore, keep steeper
While straight minimum sub-threshold slope, subthreshold slope is inhibited to degenerate, realizes that the super steep subthreshold slope that is averaged is TFET device applications
A middle extremely important problem for needing to solve.
Invention content
The purpose of the present invention is to provide a kind of multilayer source structure it is super it is steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and
Preparation method.The tunneling field-effect transistor can subthreshold slope degradation phenomena effectively in suppression device transfer characteristic, show simultaneously
Writing reduces the average subthreshold slope of tunneling field-effect transistor, and maintains more steep minimum subthreshold slope.
Technical solution provided by the invention is as follows：
A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of multilayer source structure, as shown in Figure 1, including tunnelling source region
6, channel region 1, drain region 7 and the control gate 4 above raceway groove, characterized in that the tunnelling source region is multilayered structure (6-
1,6-2 ... 6-n), different layers are the semiconductor of energy gap consecutive variations, and along vertical devices, (device refers to energy gap
The tunneling field-effect transistor) surface direction gradually increases, and wherein lowest level 6-1 energy gaps are minimum, and top layer 6-2 prohibits
Bandwidth is maximum, intermediate each layer energy gap consecutive variations.For N-type device, tunnelling source region is p-type heavy doping, drain region
For N-type heavy doping, channel region is lightly doped for p-type；And for P-type device, tunnelling source region is N-type heavy doping, and drain region is p-type
Heavy doping, channel region are lightly doped for N-type.
The tunneling field-effect transistor, characterized in that for N-type device, tunnelling source region is p-type heavy doping,
Its doping concentration is about 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, and doping concentration is about 1E18cm-3-1E19cm-3,
Channel region is lightly doped for p-type, and doping concentration is about 1E13cm-3-1E15cm-3；And for P-type device, tunnelling source region is
N-type heavy doping, doping concentration are about 1E18cm-3-1E20cm-3, drain region is p-type heavy doping, and doping concentration is about 1E18cm-3-1E19cm-3, channel region is lightly doped for N-type, and doping concentration is about 1E13cm-3-1E15cm-3。
Variation of the energy gap of multilayer tunnelling source region along vertical devices surface direction in the tunneling field-effect transistor
Gradient is the important parameter of device design.Energy gap variable gradient is too small, causes most surface layer material energy gap narrow, will
Device off-state current is caused to increase, minimum sub-threshold slope increases.And energy gap variable gradient is excessive, leads to most surface material
Energy gap is excessive, causes gate voltage needed for unlatching band-to-band-tunneling excessive.General warranty most surface layer material energy gap is more most
The big 0.3eV-0.7eV of subsurface material energy gap.And tunnelling source region is with (wide more than lowest level forbidden band compared with broad stopband width segments
Spend about 0.3eV or more region portions) junction depth optimize between 5nm-20nm.
The tunneling field-effect transistor can be applied to SiGe semi-conducting materials, can also be applied to other II-VI,
The binary or ternary compound semiconductor materials of III-V and IV-IV races.
Present invention simultaneously provides the preparations of the super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of the multilayer source structure
Method includes the following steps：
1) substrate prepares：(about 1E13cm is lightly doped-3-1E15cm-3) or undoped semiconductor substrate；
2) on substrate initial thermal oxide and deposit one layer of nitride, STI etching, and deposit isolated material filling deep hole after
CMP；
3) regrow gate dielectric material, deposits grid material, carries out lithography and etching, forms gate figure；
4) one layer of barrier oxide layers are deposited, photoetching exposes source region and selective etching goes out source region；
5) it is partly led than the source region compound of vertically consecutive variations using molecular beam epitaxy growth selection atomicity
Body obtains the multilayer tunnelling source structure of energy gap vertically consecutive variations, while carrying out doping in situ to source region, dense
Degree is about 1E18cm-3-1E20cm-3, dispel barrier oxide layers；
6) photoetching exposes drain region, using photoresist and grid as mask, carries out ion implanting and forms drain region, concentration is about
1E18cm-3-1E19cm-3；
7) quick high-temp annealing activator impurity；
8) the consistent later process of same CMOS, including deposit passivation layer, opening contact hole and metallization etc. are finally entered, i.e.,
The super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of multilayer source structure can be made.
The preparation method, characterized in that being lightly doped described in step 1), doping concentration are about 1E13cm-3-
1E15cm-3。
The preparation method, characterized in that semiconductor substrate materials described in step 1) be selected from Si, Ge or other
Germanium on the binary or ternary compound semiconductor of II-VI, III-V and IV-IV race, the silicon (SOI) or insulator on insulator
(GOI)。
The preparation method, characterized in that the gate dielectric layer material described in step 3) is selected from SiO2、Si3N4Or high K
Gate dielectric material.
The preparation method, characterized in that the method for the growth gate dielectric material described in step 3) is selected from following side
One of method：Conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
The preparation method, characterized in that the grid material described in step 3) is selected from DOPOS doped polycrystalline silicon, metallic cobalt, nickel
And other metals or metal silicide.
The preparation method, characterized in that the multilayer area material described in step 5) can be selected from atomicity than different
SiGe or other II-VI, the binary or ternary compound semiconductor of III-V and IV-IV races.
The technique effect of the present invention (by taking N-type device as an example)：
1, tunnelling source region is multilayered structure, and different layers are the semiconductor of energy gap consecutive variations, and at channel surface
With compared with broad stopband width, there is relatively narrow energy gap at a certain distance from apart from channel surface.
2, gate electrode adds positive voltage, the drop-down of raceway groove energy band that band-to-band-tunneling occurs at tunnel junctions, and device is opened.In grid voltage
There are the region portions compared with broad stopband width band-to-band-tunneling occurs when smaller, mainly at channel surface, it is hereby achieved that compared with
Steep minimum subthreshold swing.
3, as grid voltage increases, the region portions with relatively narrow energy gap at a certain distance from channel surface occur
Band-to-band-tunneling.And for band-to-band-tunneling, small gap material has the tunnelling probability of bigger relative to wide-band gap material, in phase
With the band-to-band-tunneling current increment that can obtain bigger under the conditions of gate voltage increment, it is hereby achieved that more steep average subthreshold
Slope, effectively inhibit device subthreshold slope with gate voltage increase and the phenomenon that degenerate.
4, it plays a leading role, has with the region portions compared with broad stopband width simultaneously as just having been opened in device
Conducive to the minimum subthreshold slope of reduction, and it is oblique to effectively prevent off-state current increase, minimum subthreshold caused by small gap material meeting
The phenomenon that rate increases.
Compared with existing TFET, the super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of multilayer source structure passes through device junction
Structure design, significantly improve device transfer characteristic, effectively reduce the average subthreshold slope of device, maintain it is steep most
Small subthreshold slope.
The super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor preparation process of multilayer source structure of the present invention is simple, preparation side
Method can effectively integrate TFET devices based entirely on the CMOS IC techniques of standard in CMOS integrated circuits, can also utilize mark
Quasi- technique prepares the low power consumption integrated circuit being made of TFET, significantly reduces production cost, simplifies technological process.
Description of the drawings
Fig. 1 is the structural schematic diagram of the super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of multilayer source structure of the present invention.
Fig. 2 removes the device profile map after nitride after forming STI isolation on a semiconductor substrate；
Fig. 3 is photoetching and etching forms the device profile map after grid；
Fig. 4 is that photoetching exposes the source region of TFET devices and etches device profile map after source region；
Fig. 5 is multilayer tunnelling source region of the extension growth selection atomicity than gradual change, and carries out doping in situ to tunnelling source region
Device profile map afterwards；
Fig. 6 photoetching exposes the drain region of TFET devices and ion implanting forms the device profile map behind drain region.
In figure, 1- semiconductor substrates (channel region)；2-STI is isolated；3- dielectric layers；4- grid；5- photoresists；6- multilayer tunnellings
Source region (including-lowest level 6-1, top layer 6-n and intermediate each layer)；The drain regions 7-；The passivation layer of 8- later process；9- later process
Metal.
Specific implementation mode
Below in conjunction with attached drawing, pass through the specific embodiment steep averagely subthreshold amplitude of oscillation super to multilayer source structure of the present invention
The implementation of tunneling field-effect transistor is described further.
Specific implementation step is as shown in Fig. 2-Fig. 7：(this example by taking N-type device as an example, P-type device can with and so on)
1, it is that (about 1E13cm is lightly doped in substrate doping-3-1E15cm-3), crystal orientation is<001>Si substrates 1 on
Initial thermal oxide layer of silicon dioxide, thickness about 10nm, and deposit one layer of silicon nitride (Si3N4), thickness about 100nm is used later
Shallow-trench isolation technology, deposit isolated material filling deep hole make active area STI isolation 2, then carry out CMP, as shown in Figure 2.
2, the silica of surface initial growth is removed in drift, then thermally grown one layer of gate dielectric layer 3, gate dielectric layer SiO2,
Thickness is 1~5nm；Grid material 4 is deposited using LPCVD, grid material is doped polysilicon layer, and thickness is 50~200nm.It makes by lithography
Gate figure, etching grid material 4 is until gate dielectric layer 3, as shown in Figure 3.
3, one layer of SiO is deposited2Barrier layer, thickness about 10nm, photoetching are exposed source region, are gone out using high selectivity dry etching
Tunnelling source region, junction depth about 50nm, as shown in figure -4.
4, the Si using molecular beam epitaxy growth selection along vertical devices surface direction atomicity than consecutive variations1-xGex
Compound semiconductor forms multilayer source region 6, and (x=1 in wherein 6-1 layers, atomicity is than 0 in 6-n layers<x<0.5, intermediate each layer more connects
Nearly device surface atomicity ratio x values are smaller), while doping (impurity concentration about 1E20cm in situ is carried out to source region-3), such as Fig. 5 institutes
Show.
5, barrier oxide layers are dispelled, photoetching exposes drain region, is mask with photoresist 5 and grid 4, carries out 7 ion of drain region
Inject (impurity concentration about 1E18cm-3), as shown in Figure 6.
6, the annealing of quick high-temp is carried out, and to implanted dopant into line activating (1050 DEG C, 10s).Finally enter routine
Later process, including deposit passivation layer 8, opening contact hole and metallization 9 etc..
Fig. 1 show the super steep average Asia of multilayer source structure of the N-type prepared based on standard CMOS IC techniques obtained
Threshold amplitude of oscillation tunneling field-effect transistor structural schematic diagram.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (9)
1. a kind of tunneling field-effect transistor, including tunnelling source region, channel region, drain region and the control above channel region
Grid, characterized in that the tunnelling source region is multilayered structure, and the layer structure of the tunnelling source region uses energy gap consecutive variations
Semiconductor, wherein the energy gap along vertical tunneling field-effect transistor surface direction layer structure gradually increases, wherein most
Lower layer's energy gap is minimum, and top layer's energy gap is maximum, and top layer's material energy gap is big compared with lowest level material energy gap
0.3eV-0.7eV。
2. tunneling field-effect transistor as described in claim 1, characterized in that for N-type device, tunnelling source region is P
Type heavy doping, doping concentration 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, doping concentration 1E18cm-3-
1E19cm-3, channel region is lightly doped for p-type, doping concentration 1E13cm-3-1E15cm-3；And for P-type device, tunnelling
Source region is N-type heavy doping, doping concentration 1E18cm-3-1E20cm-3, drain region is p-type heavy doping, and doping concentration is
1E18cm-3-1E19cm-3, channel region is lightly doped for N-type, doping concentration 1E13cm-3-1E15cm-3。
3. tunneling field-effect transistor as described in claim 1, characterized in that it is wide to be more than lowest level forbidden band in tunnelling source region
The depth of the part of 0.3eV or more is spent between 5nm-20nm.
4. tunneling field-effect transistor described in claim 1 is applied to SiGe semiconductor material devices, or is applied to other II-
The binary or ternary compound semiconductor materials device of VI, III-V and IV-IV race.
5. the preparation method of tunneling field-effect transistor as described in claim 1, includes the following steps：
1) substrate prepares：It is lightly doped or undoped semiconductor substrate；
2) on substrate initial thermal oxide and deposit one layer of nitride；STI is etched, and deposits CMP after isolated material filling deep hole；
3) regrow gate dielectric material, deposits grid material, carries out lithography and etching, forms gate figure；
4) one layer of barrier oxide layers are deposited, photoetching exposes source region and selective etching goes out source region；
5) it uses molecular beam epitaxy growth selection atomicity than the source region compound semiconductor of vertically consecutive variations, obtains
Doping in situ is carried out to the multilayer tunnelling source structure of energy gap vertically consecutive variations, while to source region, it is a concentration of
1E18cm-3-1E20cm-3, dispel barrier oxide layers；
6) photoetching exposes drain region, using photoresist and grid as mask, carries out ion implanting and forms drain region, a concentration of 1E18cm-3-
1E19cm-3；
7) quick high-temp annealing activator impurity；
8) the consistent later process of same CMOS, including deposit passivation layer, opening contact hole and metallization are finally entered, you can be made
The super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor of multilayer source structure.
6. preparation method as claimed in claim 5, characterized in that semiconductor substrate materials described in step 1) be selected from Si,
Ge or other II-VI, binary or ternary compound semiconductor, the silicon (SOI) on insulator or the insulation of III-V and IV-IV races
Germanium (GOI) on body, described is lightly doped, doping concentration 1E13cm-3-1E15cm-3。
7. preparation method as claimed in claim 5, characterized in that the gate dielectric layer material described in step 3) is selected from SiO2、
Si3N4Or high-K gate dielectric material, the method for growing gate dielectric material are selected from one of following method：The hot oxygen of conventional thermal oxidation, nitrating
Change, chemical vapor deposition or physical vapor deposition.
8. preparation method as claimed in claim 5, characterized in that grid material described in step 3) be selected from DOPOS doped polycrystalline silicon,
Metallic cobalt or nickel.
9. preparation method as claimed in claim 5, characterized in that the multilayer area material described in step 5) is selected from atomicity
Than different SiGe or other II-VI, the binary or ternary compound semiconductor of III-V and IV-IV races.
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| CN201510136845.8A CN104752497B (en) | 2015-03-26 | 2015-03-26 | A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method |
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| CN201510136845.8A CN104752497B (en) | 2015-03-26 | 2015-03-26 | A kind of super steep averagely subthreshold amplitude of oscillation tunneling field-effect transistor and preparation method |
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| CN104752497A CN104752497A (en) | 2015-07-01 |
| CN104752497B true CN104752497B (en) | 2018-08-28 |
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