CN111435642B - Three-dimensional stacked semiconductor nanowire structure and preparation method thereof - Google Patents

Three-dimensional stacked semiconductor nanowire structure and preparation method thereof Download PDF

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CN111435642B
CN111435642B CN201910026963.1A CN201910026963A CN111435642B CN 111435642 B CN111435642 B CN 111435642B CN 201910026963 A CN201910026963 A CN 201910026963A CN 111435642 B CN111435642 B CN 111435642B
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layer
semiconductor
periodic
nanowire structure
fabricating
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CN111435642A (en
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刘强
俞文杰
任青华
陈治西
刘晨鹤
赵兰天
陈玲丽
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Abstract

The invention provides a three-dimensional stacked semiconductor nanowire structure and a preparation method thereof, wherein the three-dimensional stacked semiconductor nanowire structure comprises the following steps: forming a periodic structure on a second semiconductor substrate and performing ion implantation to form a stripping interface; forming a groove in the insulating layer on the first semiconductor substrate, wherein the groove does not penetrate through the insulating layer; bonding the periodic structure and the insulating layer to form a cavity; annealing to strengthen the bonding strength and to strip the periodic structure from the stripping interface to form a top semiconductor layer; and patterning the top semiconductor layer and selectively removing the sacrificial layer to form a semiconductor nanowire structure suspended in the air and crossing the groove. According to the invention, the SOI substrate with the graphical structure is firstly manufactured, the hollowed-out and upwards-stacked semiconductor nanowires can be directly prepared by the SOI substrate through dry etching, and when the semiconductor nanowires are etched, isotropic wet etching is not required, so that the generation of an inwards concave cavity can be effectively avoided.

Description

Three-dimensional stacked semiconductor nanowire structure and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a three-dimensional stacked semiconductor nanowire structure and a preparation method thereof.
Background
With the continuous scaling of microelectronic devices, it is expected that the existing FinFET technology will face a larger technical bottleneck at the 5nm and 3nm nodes, and the device performance is no longer greatly improved with the continuous reduction of the device size. There is a need for new device technologies, such as new device materials (e.g., strained silicon, silicon germanium, iii-v semiconductors, etc.), and new device structures (e.g., nanowire ring-gate transistors, etc.).
The nanowire gate-all-around transistor can limit a conducting channel to the center of the nanowire instead of the interface of the nanowire and the gate oxide layer, so that scattering of current carriers is greatly reduced, and the nanowire gate-all-around transistor is expected to be an important future development direction and further continues the development of the Mole's law.
The nanowire ring gate transistor has various preparation schemes, and one simple preparation method is to etch a hollow nanowire structure based on an SOI substrate and prepare a corresponding ring gate transistor. Fig. 1 to 12 show a method for manufacturing a representative nanowire gate-all-around transistor, in which fig. 2 shows a schematic cross-sectional structure at a-a 'of fig. 1, fig. 3 shows a schematic cross-sectional structure at B-B' of fig. 1, and fig. 4 to 12 have the same correspondence. The method mainly comprises the following steps:
as shown in fig. 1 to fig. 3, step 1) is performed to provide an SOI substrate, where the SOI substrate includes a silicon substrate 101, an oxide layer 102, and a top silicon layer 103, and silicon nanowires 104 are etched in the top silicon layer 103 and the oxide layer 102 through a photolithography process and an etching process;
as shown in fig. 4 to 6, step 2) is performed, and the oxide layer 102 under the silicon nanowire is removed by wet etching to form a hollow hole 105;
as shown in fig. 7 to 9, step 3) is performed to thin the silicon nanowire;
as shown in fig. 10 to 12, step 4) is performed to sequentially deposit a gate dielectric layer 106 and a gate electrode 107 to form a gate-all-around transistor.
The above solution has the following disadvantages:
firstly, when the nanowire structure is etched in step 1), the top silicon of the adjacent region of the nanowire and a part of the silicon oxide under the top silicon need to be etched away. As shown in fig. 2, during the etching process, it is necessary to keep the oxide layer 102 from being etched through, and the remaining silicon oxide layer can still keep a certain thickness to prevent a large parasitic capacitance or breakdown between the gate electrode and the substrate electrode (as shown by 108 in fig. 11) as shown in fig. 11, which brings a certain requirement to the accuracy of the etching process.
Secondly, in order to prepare the silicon nanowire with the suspended structure, the oxide layer under the nanowire needs to be etched, and a wet etching is usually adopted, but since the wet etching is an isotropic etching, a part of the silicon oxide in the exposed region except under the silicon nanowire is also etched, and an unnecessary concave cavity 109 is formed, as shown in fig. 8.
This concave cavity can have the following adverse effects:
as shown in fig. 13 and 14, wherein fig. 13 is a top view of the cross section C-C' of fig. 11, and fig. 14 is an enlarged structural view of the dashed box of fig. 13, the concave cavity is finally filled with the gate dielectric layer 106 and the gate electrode 107. In order to ensure good step coverage, an ALD process is generally used to prepare the gate dielectric layer 106 and the gate electrode 107. Even with ALD processes, however, when filling a semi-enclosed structure with dishing, premature contact interconnection of the film to the film occurs easily during filling of the plated film, and eventually an enclosed cavity within the gate metal is formed in the reentrant structure, rather than being completely filled.
As shown in fig. 8, 13 and 14, the corresponding concave cavity 109 in fig. 8 is also filled with the gate dielectric layer 106 and the gate electrode 107, so that the gate electrode under the nanowire is longer than the gate electrode above the nanowire. This results in: an unnecessary overlapping area is arranged between the bottom layer gate and the source drain, a silicon channel in the area is influenced by asymmetric gate potential, and current carriers in the silicon channel are scattered to a certain extent; the resistance between the gate electrode and the source-drain electrode becomes large; the source-drain parasitic capacitance becomes large, and the high-frequency characteristic of the device becomes poor; when the silicon channel of the overlapping region is heavily doped, hot electrons are easily generated between the bottom gate and the silicon channel of the overlapping region, the gate leakage current is increased, and the gate oxide is broken down.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a three-dimensionally stacked semiconductor nanowire structure and a method for manufacturing the same, which are used to solve the problems that a conventional semiconductor nanowire structure in the prior art requires a wet etching process, which is prone to generate a concave cavity, and the process stability is low.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensionally stacked semiconductor nanowire structure, the method comprising: step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming an insulating layer on the surface of the first semiconductor substrate; step 2), forming a periodic structure of alternately stacked sacrificial layers and semiconductor layers on the surface of the second semiconductor substrate, carrying out stripping ion implantation on the sacrificial layer at the bottommost layer, and defining a stripping interface in the sacrificial layer at the bottommost layer; step 3), the insulating layer is etched in a patterning mode, so that a groove is formed in the insulating layer, and the groove does not penetrate through the insulating layer; step 4), bonding the periodic structure and the insulating layer, wherein the periodic structure seals the groove to form a cavity; step 5), carrying out an annealing process to strengthen the bonding strength between the insulating layer and the periodic structure, and stripping the sacrificial layer at the bottommost layer from a stripping interface, wherein the part of the periodic structure, which is combined with the insulating layer, is used as a top semiconductor layer of the SOI substrate; 6) the top semiconductor layer is etched in a patterned mode to form a periodic nanowire structure which is suspended and stretches across the groove, the periodic nanowire structure comprises periodic bosses located on two sides of the groove and a plurality of periodic nanowires connected to the periodic bosses; 7) selectively removing the sacrificial layer in the periodic nanowires to form suspended and upwards stacked semiconductor nanowires; 8) and rounding and thinning the semiconductor nanowire structure.
Optionally, the insulating layer has a thickness of no greater than 150 nm, the top semiconductor layer has a thickness of no greater than 50nm, and the recess has a depth of no greater than 50 nm.
Optionally, the bonding atmosphere in step 4) includes hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen, or vacuum, and during the annealing process in step 5), the mixture in the cavity is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer to reduce the pressure in the cavity.
Optionally, the annealing process includes annealing at a first temperature to peel the sacrificial layer of the bottommost layer from the peeling interface, and annealing at a second temperature to enhance the bonding strength between the insulating layer and the periodic structure, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃. .
Optionally, step 5) further comprises a step of performing CMP polishing on the top semiconductor surface to remove the remaining sacrificial layer of the bottommost layer.
Optionally, the thickness of the lowermost sacrificial layer is not less than 40 nm.
Optionally, the topmost layer of the periodic structure is a semiconductor layer, and step 2) further includes a step of performing planarization treatment on the topmost semiconductor layer, so that the surface roughness of the topmost semiconductor layer is less than 0.2 nm, and the thickness of the topmost semiconductor layer is equal to that of the semiconductor layer in the periodic structure.
Optionally, the planarization process includes one or a combination of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
Optionally, the sacrificial layer comprises a SixGe1-x layer and the semiconductor layer comprises a Si layer, wherein 0 < x ≦ 1.
Optionally, the sacrificial layer includes a 111 crystal plane Si layer, and the semiconductor layer includes a GaN layer.
Optionally, the sacrificial layer comprises a single crystal Al2O3 layer and the semiconductor layer comprises a GaN layer.
Optionally, step 8) is to oxidize the semiconductor nanowire structure to form an oxide layer on the surface thereof, and then to remove the oxide layer, so as to reduce the diameter of the semiconductor nanowire and round the semiconductor nanowire.
Optionally, the oxidizing is to perform rapid annealing in an oxygen atmosphere and control the semiconductor nanowire to perform slight oxidation so as to improve the control accuracy of the size and the shape of the nanowire, and the method for removing the oxide layer includes one of wet etching or atomic layer etching.
The present invention also provides a three-dimensionally stacked semiconductor nanowire structure comprising: a semiconductor substrate; the insulating layer is provided with a groove, and the groove does not penetrate through the insulating layer; the semiconductor nanowire structure comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses, and any two adjacent semiconductor bosses are separated by a sacrificial layer boss.
Optionally, the thickness of the insulating layer is not greater than 150 nm, and the depth of the groove is not greater than 50 nm.
Optionally, the material of the semiconductor nanowire comprises one of Si and GaN.
As described above, the three-dimensionally stacked semiconductor nanowire structure and the method for manufacturing the same according to the present invention have the following advantageous effects:
1) according to the invention, the SOI substrate with the graphical structure is firstly manufactured, the hollowed-out and three-dimensionally stacked semiconductor nanowires can be directly prepared by the SOI substrate through dry etching, and when the semiconductor nanowires are etched, isotropic wet etching is not required, so that the generation of an inwards concave cavity can be effectively avoided.
2) In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or oxygen/nitrogen mixed gas, so that in the subsequent processes of intelligent stripping and high-temperature reinforced bonding, the gas in the cavity of the insulating layer can be diffused out of the semiconductor or absorbed by the semiconductor, and the air pressure in the cavity is reduced, so that the cavity structure has internal pressure close to the external atmospheric pressure in the high-temperature environment, the pressure on the cavity structure is small, and the structure is not easily damaged by the difference between the internal air pressure and the external air pressure, thereby obtaining the SOI substrate with the graphical structure of the thin-layer top semiconductor layer, and reducing the preparation difficulty and the preparation time of the semiconductor nanowire.
Drawings
Fig. 1 to 14 are schematic structural diagrams showing steps of a method for manufacturing a nanowire wrap-around transistor in the prior art.
Fig. 15-33 are schematic structural views showing steps of a method for fabricating a three-dimensional stacked semiconductor nanowire structure according to the present invention.
Description of the element reference numerals
201 first silicon substrate
202 insulating layer
203 groove
204 cavity
301 second silicon substrate
302 second insulating layer
40 period structure
401 sacrificial layer
402 semiconductor layer
501 semiconductor nanowires
503 semiconductor boss
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 15 to 33. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 15 to 33, the present embodiment provides a method for preparing a three-dimensionally stacked semiconductor nanowire structure, the method comprising:
as shown in fig. 15, step 1) is performed to provide a first silicon substrate 201 and a second silicon substrate 301, and an insulating layer 202 is formed on a surface of the first silicon substrate 201. In other embodiments, the first silicon substrate and the second silicon substrate may be made of other semiconductor materials, for example, the material of the first semiconductor substrate and the second semiconductor substrate may be one of germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide, and is not limited to the examples listed here.
For example, a thermal oxidation process is adopted to form a silicon dioxide layer on the surface of the first silicon substrate 201 as the insulating layer 202, in this embodiment, the thermal oxidation process is a dry thermal oxidation process, and the temperature range of the oxidation is 900 to 1200 ℃, and may be specifically 1000 ℃.
As shown in fig. 17 to 19, step 2) is performed to form the periodic structure 40 of the alternately stacked sacrificial layers 401 and semiconductor layers 402 on the surface of the second semiconductor substrate 301, and then the stripping ion implantation is performed to the sacrificial layer 401 at the bottom layer, so as to define the stripping interface in the sacrificial layer 401 at the bottom layer.
For example, a periodic structure 40 of alternately stacked sacrificial layers 401 and semiconductor layers 402 may be formed on the surface of the second semiconductor substrate 301 by a Chemical Vapor Deposition (CVD) process or Molecular Beam Epitaxy (MBE). For example, in the present embodiment, the sacrificial layer 401 may be a SixGe1-x layer, and the semiconductor layer 402 may be a Si layer, where 0 < x ≦ 1. Of course, according to different etching processes, the sacrificial layer may be silicon, the semiconductor layer may be SixGe1-x layer, and the sacrificial layer and the semiconductor layer may be interchangeable if both are made of semiconductor materials. The sacrificial layer 401 and the semiconductor layer 402 have similar lattice parameters in principle, and have a higher etching selectivity ratio in the same etching process, for example, the etching selectivity ratio of the sacrificial layer 401 to the semiconductor layer 402 is not less than 10 to 1. For example, when the sacrificial layer 401 is a SixGe1-x layer, H may be used2O2Solutions or H2O2+NH3·H2O solution or H2O2+HF+COOCH3A solution or the like selectively removes the sacrificial layer 401.
For another example, in another embodiment, the sacrificial layer 401 may be a 111 crystal plane Si layer, and the semiconductor layer 402 may be a GaN layer, in which case NH may be used3·H2O solution or H2O2The + HF solution selectively removes the sacrificial layer 401.
For another example, in another embodiment, the sacrificial layer 401 may be a single crystal Al2O3 layer, and the semiconductor layer 402 may be a GaN layer, and in this case, the sacrificial layer 401 may be selectively removed using a H3PO4 solution, an HF solution, an NH3 · H2O solution, a BOE solution, or the like.
The bottom layer of the periodic structure 40 is a sacrificial layer 401, the top layer of the periodic structure 40 is a semiconductor layer 402, and after the deposition of the top layer of the semiconductor layer 402, the method further comprises a step of performing planarization treatment on the top layer of the semiconductor layer 402, so that the surface roughness of the top layer of the semiconductor layer 402 is smaller than 0.2 nanometer, and the thickness of the top layer of the semiconductor layer 402 is equal to the thickness of the semiconductor layer 402 in the periodic structure 40. For example, the planarization process may include one or a combination of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
In this embodiment, the thickness of the lowermost sacrificial layer 401 is not less than 40 nm. For example, the thickness of the sacrificial layer 401 at the bottom layer can be 40-60 nanometers, and the sacrificial layer 401 at the bottom layer with the thickness can effectively ensure the process stability of the subsequent ion implantation stripping and ensure that fewer residual layers exist after the stripping, so that the removal cost of the subsequent residual layers is saved.
As an example, the stripping ions may be H ions, and the ion implantation parameters depend on the desired implantation depth. Of course, in other embodiments, He ions may be used as the stripping ions for implantation, and the examples are not limited to the examples listed here.
As shown in fig. 16, step 3) is performed to pattern etch the insulating layer 202, so as to form a groove 203 in the insulating layer 202, where the groove 203 does not penetrate through the insulating layer 202.
In this embodiment, the patterned etching is anisotropic dry etching to improve the control accuracy of the groove 203.
For example, in the present embodiment, the thickness of the insulating layer 202 is not greater than 150 nm, and the depth of the groove 203 is not greater than 50 nm. The above parameter settings may ensure that a sufficient thickness of the insulating layer is maintained below the recess 203, for example, the thickness of the insulating layer below the recess 203 is above 50 nm.
As shown in fig. 20, step 4) is then performed to bond the periodic structure 40 and the insulating layer 202, and the periodic structure 40 closes the groove 203 to form a cavity 204.
As shown in fig. 21, step 5) is performed, an annealing process is performed to enhance the bonding strength between the insulating layer 202 and the periodic structure 40, and the periodic structure 40 is peeled from the peeling interface, wherein the portion of the periodic structure 40 bonded to the insulating layer 202 serves as a top semiconductor layer of the SOI substrate; wherein the bonding atmosphere of step 4) includes hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen, or vacuum, and during the annealing process of step 5), the mixture in the cavity 204 is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer to reduce the pressure in the cavity 204.
In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or oxygen/nitrogen mixed gas, so that in the subsequent processes of intelligent stripping and high-temperature reinforced bonding, the gas in the insulating layer cavity 204 can be diffused out of silicon or absorbed by silicon, for example, the hydrogen can be diffused out of a semiconductor layer, the oxygen can be absorbed by the semiconductor layer, and the air pressure in the cavity 204 is reduced, so that the cavity 204 structure has internal pressure close to the external atmospheric pressure in the high-temperature environment, the pressure on the cavity 204 structure is smaller, and the structure is not easily damaged by the difference of the internal and external air pressures, thereby obtaining the SOI substrate with the thin-layer top semiconductor layer and the graphical structure. For example, in this embodiment, the thickness of the top semiconductor layer is not greater than 50nm, and a thinner top semiconductor layer is prepared, so that the application range of the SOI substrate with the patterned structure of the present invention can be effectively expanded, for example, the present invention can be used for etching and forming a hollowed three-dimensional stacked semiconductor nanowire, thereby reducing the etching difficulty of the semiconductor nanowire and improving the quality of the semiconductor nanowire.
Specifically, the annealing process includes annealing at a first temperature to peel the sacrificial layer 401 of the bottom layer from the peeling interface, and annealing at a second temperature to enhance the bonding strength between the insulating layer 202 and the periodic structure 40, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃.
Finally, as shown in fig. 22, CMP polishing is performed on the surface of the top semiconductor layer to remove the remaining sacrificial layer 401 of the bottom layer, so as to obtain a top semiconductor layer with a smooth surface.
The above-described manufacturing method is applicable to wafer-level manufacturing, and the structure of the SOI substrate of the wafer-level patterned structure of the present invention is shown in fig. 23.
Fig. 24 to 32 are enlarged schematic structural views of a dotted-line frame region in fig. 22, fig. 25 is a schematic structural view of a cross section at a-a 'in fig. 24, fig. 26 is a schematic structural view of a cross section at B-B' in fig. 24, and fig. 27 to 32 have the same view relationship.
As shown in fig. 24 to 26, step 6) is performed to pattern-etch the top semiconductor layer to form a periodic nanowire structure suspended in the air and crossing the groove, where the periodic nanowire structure includes periodic mesas located at two sides of the groove and a plurality of periodic nanowires connected to the periodic mesas.
Specifically, the patterned etching is anisotropic dry etching.
As shown in fig. 27 to 29, step 7) is followed to selectively remove the sacrificial layer in the periodic nanowire to form a semiconductor nanowire 501 which is suspended and stacked upwards, and since the sacrificial layer in the periodic nanowire is much thinner than the sacrificial layer in the periodic mesa, when the sacrificial layer in the periodic nanowire is completely removed, the sacrificial layer mesa remains in the periodic mesa, and the sacrificial layer mesa separates two adjacent semiconductor mesas 502.
As shown in fig. 30-33, step 8) is finally performed to round and thin the semiconductor nanowire structure.
For example, the semiconductor nanowire structure may be oxidized to form an oxide layer on the surface thereof, and then the oxide layer may be removed to make the diameter of the semiconductor nanowire small and round the semiconductor nanowire. Optionally, the oxidizing is to perform rapid annealing in an oxygen atmosphere and control the semiconductor nanowire to perform slight oxidation so as to improve the control accuracy of the size and the shape of the nanowire, and the method for removing the oxide layer includes one of wet etching or atomic layer etching.
It should be noted that the above-mentioned manufacturing method is suitable for wafer-level manufacturing, as shown in fig. 33.
As shown in fig. 30 to 33, the present embodiment also provides a three-dimensionally stacked semiconductor nanowire structure, including: a semiconductor substrate 201; an insulating layer 202 located on the semiconductor substrate 201, wherein the insulating layer 202 has a groove 203 therein, and the groove 203 does not penetrate through the insulating layer 202; the semiconductor nanowire structure comprises semiconductor bosses 502 positioned on two sides of the groove and a plurality of semiconductor nanowires 501 connected to the semiconductor bosses 502, wherein any two adjacent semiconductor bosses 502 are separated by a sacrificial layer boss.
For example, the thickness of the insulating layer 202 is not greater than 150 nm, and the depth of the groove 203 is not greater than 50 nm.
For example, the material of the semiconductor nanowire 501 includes one of Si and GaN.
As described above, the three-dimensionally stacked semiconductor nanowire structure and the method for manufacturing the same according to the present invention have the following advantageous effects:
1) the invention provides a preparation method of an SOI substrate with good process stability, the SOI substrate can directly prepare hollow three-dimensional stacked semiconductor nanowires through dry etching, when the semiconductor nanowires are etched, isotropic wet etching is not needed, and the generation of concave cavities can be effectively avoided.
2) In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or oxygen/nitrogen mixed gas, so that in the subsequent processes of intelligent stripping and high-temperature reinforced bonding, the gas in the cavity of the insulating layer can be diffused out of the top semiconductor layer or absorbed by the top semiconductor layer, and the gas pressure in the cavity is reduced, so that the cavity structure has internal pressure close to the external atmospheric pressure in the high-temperature environment, the pressure on the cavity structure is smaller, and the structure is not easily damaged by the difference between the internal pressure and the external pressure, thereby obtaining the SOI substrate with the thin-layer top semiconductor layer and the graphical structure.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (13)

1. A method of fabricating a three-dimensionally stacked semiconductor nanowire structure, the method comprising:
step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming an insulating layer on the surface of the first semiconductor substrate;
step 2), forming a periodic structure of alternately stacked sacrificial layers and semiconductor layers on the surface of the second semiconductor substrate, carrying out stripping ion implantation on the sacrificial layer at the bottommost layer, and defining a stripping interface in the sacrificial layer at the bottommost layer;
step 3), the insulating layer is etched in a patterning mode, so that a groove is formed in the insulating layer, and the groove does not penetrate through the insulating layer;
step 4), bonding the periodic structure and the insulating layer, wherein the groove is sealed by the periodic structure to form a cavity;
step 5), carrying out an annealing process to strengthen the bonding strength between the insulating layer and the periodic structure, and stripping the sacrificial layer at the bottommost layer from a stripping interface, wherein the part of the periodic structure, which is combined with the insulating layer, is used as a top semiconductor layer of the SOI substrate;
step 6), the top semiconductor layer is etched in a graphical mode to form a periodic nanowire structure which is suspended and stretches across the groove, the periodic nanowire structure comprises periodic bosses located on two sides of the groove and a plurality of periodic nanowires connected to the periodic bosses, and the width of the groove is smaller than the length of the periodic nanowires;
step 7), selectively removing the sacrificial layer in the periodic nanowires to form suspended and upwards stacked semiconductor nanowires;
and 8) rounding and thinning the semiconductor nanowire structure.
2. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the thickness of the insulating layer is not more than 150 nanometers, the thickness of the top semiconductor layer is not more than 50 nanometers, and the depth of the groove is not more than 50 nanometers.
3. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the bonding atmosphere of step 4) includes hydrogen, a mixture of hydrogen and nitrogen, a mixture of oxygen and nitrogen, oxygen, or vacuum, and during the annealing process of step 5), the mixture in the cavity is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer to reduce the pressure in the cavity.
4. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the annealing process comprises annealing at a first temperature to enable the sacrificial layer at the bottommost layer to be stripped from a stripping interface, and annealing at a second temperature to enhance the bonding strength of the insulating layer and the periodic structure, wherein the first temperature ranges from 200 ℃ to 900 ℃, and the second temperature ranges from 400 ℃ to 1200 ℃.
5. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: step 5) further comprises the step of carrying out CMP polishing on the surface of the top semiconductor layer so as to remove the residual sacrificial layer of the bottommost layer.
6. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the thickness of the bottom sacrificial layer is not less than 40 nanometers.
7. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the topmost layer of the periodic structure is a semiconductor layer, and the step 2) further comprises the step of carrying out planarization treatment on the topmost semiconductor layer, so that the surface roughness of the topmost semiconductor layer is smaller than 0.2 nanometer, and the thickness of the topmost semiconductor layer is equal to that of the semiconductor layer in the periodic structure.
8. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 7, wherein: the planarization treatment comprises one or two combinations of chemical mechanical polishing or thermal oxidation followed by removal of the oxide layer.
9. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the sacrificial layer comprises SixGe1-xThe semiconductor layer comprises a Si layer, wherein x is more than 0 and less than or equal to 1.
10. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the sacrificial layer comprises a 111 crystal plane Si layer, and the semiconductor layer comprises a GaN layer.
11. The method of fabricating the three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: the sacrificial layer comprises single crystal Al2O3A layer, the semiconductor layer comprising a GaN layer.
12. The method of fabricating a three-dimensionally stacked semiconductor nanowire structure of claim 1, wherein: and 8) oxidizing the semiconductor nanowire structure to form an oxide layer on the surface of the semiconductor nanowire structure, and then removing the oxide layer to reduce the diameter of the semiconductor nanowire and round the semiconductor nanowire.
13. The method of fabricating the three-dimensionally stacked semiconductor nanowire structure of claim 12, wherein: the oxidation is to carry out rapid annealing in an oxygen atmosphere and control the semiconductor nanowires to carry out slight oxidation so as to improve the control precision of the size and the shape of the nanowires, and the method for removing the oxide layer comprises one of wet etching or atomic layer etching.
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