CN105633001A - Silicon-on-insulator substrate material and preparation method thereof - Google Patents
Silicon-on-insulator substrate material and preparation method thereof Download PDFInfo
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- CN105633001A CN105633001A CN201511017224.4A CN201511017224A CN105633001A CN 105633001 A CN105633001 A CN 105633001A CN 201511017224 A CN201511017224 A CN 201511017224A CN 105633001 A CN105633001 A CN 105633001A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
Abstract
The invention provides silicon-on-insulator substrate material and a preparation method thereof. The silicon-on-insulator substrate material comprises bottom silicon; an insulating layer which is combined on the surface of the bottom silicon, wherein the positions corresponding to preparation of transistor channels of the insulating layer are provided with grooves which penetrate through the bottom silicon or the bottom part with reserving of a part of insulating layer; and top silicon which is combined on the surface of the insulating layer. The grooves are manufactured in the insulating layer corresponding to preparation of the transistor channels, and the grooves can completely penetrate between the top silicon and the bottom silicon and can also reserve a part of insulating layer in the grooves so that a hollow area is enabled to be formed below the subsequently prepared transistor channels. The structure and the method are simple and reliability of a device can be effectively enhanced so that the silicon-on-insulator substrate material has wide application prospect in the field of semiconductor manufacturing.
Description
Technical field
The present invention relates to a kind of semiconductor device substrates and its preparation method, particularly relate to silicon substrate material and its preparation method in a kind of insulator islands.
Background technology
SOI (Silicon-On-Insulator, the silicon in insulating substrate) technology be at the bottom of top layer silicon and backing between introduce one layer and bury zone of oxidation. By forming semiconductor film on insulator, SOI material is provided with the incomparable advantage of body silicon: the media isolated that can realize components and parts in unicircuit, completely eliminates the parasitic latch-up in Bulk CMOS circuit; The unicircuit adopting this kind of material to make also has that stray capacitance is little, integration density height, speed are fast, technique is simple, short-channel effect is little and are specially adapted to the advantages such as low voltage and low power circuits, therefore, SOI becomes the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit gradually.
When starting to adopt SOI material to make substrate, chip manufacturer still can continue to use traditional manufacturing process and equipment in process of production. Fact proved, SOI can meet the performance demand of main flow MOSFET (metal oxide semiconductor field effect transistor (MOSFET)) completely. The improved performance of CMOS (complementary metal oxide semiconductor) device, leakage current reduced and power consumption minimizing etc. all can produce great promoter action, is particularly suitable for voltage devices structure etc.
Except cmos device, SOI also can be used to the leading microelectromechanical systems of manufacturing technology (MEMS), and MEMS can be used for sensor and low-light power technology circuit etc. , it is also possible to utilize SOI to strengthen the performance of BiCMOS, power device and high tension apparatus, in addition can also improve in addition in the performance of hot environment or the unicircuit under being exposed on ionizing radiation environment.
The chip of SOI wafer manufacture is made up of millions of insulation layer containing transistor, and each insulation layer isolates mutually with the bulk substrate silicon substrate under other insulation layer and its. This feature greatly simplifies the design of circuit: owing between transistor being isolation mutually, and Designers is without the need in order to realize the electric insulation of reverse-biased node and design complicated circuit arrangement. Insulation layer also can protect movable silicon layer parasitic on top layer and body silicon substrate substrate simultaneously. These two advantages of SOI so that Designerss can develop compacter super large-scale integration (VLSI) chip.
Meanwhile, IC manufacturing business utilizes SOI can also produce at the standby cmos circuit lower with power consumption under operator scheme. Owing to insulation layer in this structure separates movable silicon film and bulk substrate silicon substrate, therefore the p-n junction of big area will be replaced by dielectric isolation (dielectricisolation). Source electrode and drain electrode (drainregions) extend downward buried oxide (buriedoxideBOX), effectively reduce leakage current and junction capacitance. Its result has necessarily increased substantially the travelling speed of chip, has widened the temperature range of devices function. SOI device also has minimum junction area, therefore has good anti-soft inefficacy, instantaneous irradiation and single-particle (alpha-particle) and overturns ability.
Relative to body silicon materials device, the correlated performance such as the stray capacitance of SOI, source and drain coupling, Flouride-resistani acid phesphatase all increases significantly, but contacts with insulation layer due to the active area top layer silicon of general SOI device, and device causes following impact:
The first, there is certain stray capacitance between source and drain and substrate, affect device speed;
2nd, it is coupled by bottom BOX between source and drain, the device of reduced size easily produces short-channel effect;
3rd, channel carrier can be caused scattering by the defect in raceway groove underlying insulating layer, affects the mobility of current carrier;
4th, after high energy particle incidence, will in BOX insulation layer excitation electron-hole pair, affect the anti-radiation performance of device.
Based on the above, it is provided that a kind of SOI substrate material that can effectively improve SOI device reliability is necessary.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide silicon substrate material and its preparation method in a kind of insulator islands, for improving the reliability of traditional SOI substrate making devices further.
For achieving the above object and other relevant objects, the present invention provides the preparation method of silicon substrate material in a kind of insulator islands, and described preparation method comprises step: step 1), it is provided that the first silicon substrate, forms the first insulation layer in described first surface of silicon; Step 2), carry out peeling off ion implantation to described first silicon substrate based on described first insulation layer, in described silicon substrate, interface is peeled off in definition, then removes described first insulation layer; Step 3), it is provided that the 2nd silicon substrate, forms the 2nd insulation layer in described 2nd surface of silicon; Step 4), form mask layer in described 2nd surface of insulating layer, and in forming etching window corresponding to the position preparing transistor channel; Step 5), etch described 2nd insulation layer based on etching window, formed and be through to described 2nd silicon substrate or bottom remains with the groove of part the 2nd insulation layer; Step 6), it is bonded described first silicon substrate and described 2nd insulation layer; Step 7), carry out annealing process and described first silicon substrate is peeled off from stripping interface, the part being bonded with described 2nd insulation layer is as the silicon top layer of silicon substrate material in insulator islands; And step 8), carry out high temperature annealing, to strengthen described 2nd silicon substrate and the bond strength of described 2nd insulation layer.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 1) in, adopt thermal oxidation technology to form silicon dioxide layer in described first surface of silicon, as the first insulation layer; Step 3) in, adopt thermal oxidation technology to form silicon dioxide layer in described 2nd surface of silicon, as the 2nd insulation layer.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, the thickness of described 2nd insulation layer is for being not less than 5nm.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 2) in, described stripping ion is H ion or He ion.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 2) in, described stripping ion in the injection degree of depth of described first silicon substrate be 20��2000nm.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 6) also comprise before bonding the step that described first silicon substrate and the 2nd silicon substrate clean.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 7) in, the atmosphere of annealing process is N2 atmosphere.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 7) in, the temperature range of annealing process is 400��500 DEG C, so that described first silicon substrate is peeled off from stripping interface.
As a kind of preferred version of the preparation method of silicon substrate material in the insulator islands of the present invention, step 7) in, also comprise the step that described top layer silicon surface is carried out CMP planarization.
The present invention also provides silicon substrate material in a kind of insulator islands, comprising: bottom silicon; Insulation layer, is incorporated into described bottom silicon face, and in having corresponding to the position preparing transistor channel until described bottom silicon or bottom remain with the groove of partial insulative layer; And top layer silicon, it is incorporated into described surface of insulating layer.
As a kind of preferred version of silicon substrate material in the insulator islands of the present invention, described insulation layer is silicon dioxide layer.
As a kind of preferred version of silicon substrate material in the insulator islands of the present invention, the thickness of described insulation layer is for being not less than 5nm.
As a kind of preferred version of silicon substrate material in the insulator islands of the present invention, the thickness range of described top layer silicon is 20��2000nm.
As mentioned above, silicon substrate material and its preparation method in the insulator islands of the present invention, there is following useful effect: the present invention is by making groove corresponding to preparing in the insulation layer of transistor channel, this groove can completely through between top layer silicon and bottom silicon, can also in groove the insulation layer of retained part so that below the transistor channel of follow-up preparation, there is area of knockout. Present configuration and method are simple, can effectively improve the reliability of device, be with a wide range of applications in field of semiconductor manufacture.
Accompanying drawing explanation
The structural representation that Fig. 1��Figure 10 is shown as in the insulator islands of the present invention each step of the preparation method of silicon substrate material respectively and presents.
Figure 11 is shown as the structural representation of silicon substrate material in insulator islands of the present invention.
Element numbers explanation
101 first silicon substrates
102 first insulation layers
201 the 2nd silicon substrates
202 the 2nd insulation layers
203 grooves
301 bottom silicon
302 insulation layers
303 grooves
304 top layer silicon
Embodiment
Below by way of specific specific examples, embodiments of the present invention being described, those skilled in the art the content disclosed by this specification sheets can understand other advantages and effect of the present invention easily. The present invention can also be implemented by embodiments different in addition or be applied, and the every details in this specification sheets based on different viewpoints and application, can also carry out various modification or change under the spirit not deviating from the present invention.
Refer to Fig. 1��Figure 11. It should be noted that, the diagram provided in the present embodiment only illustrates the basic conception of the present invention with illustration, then the only component count of display with relevant assembly in the present invention but not when implementing according to reality, shape and size drafting in diagram, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Fig. 1��Figure 10, the present embodiment provides the preparation method of silicon substrate material in a kind of insulator islands, and described preparation method comprises step:
As shown in Fig. 1��Fig. 2, first carry out step 1), it is provided that the first silicon substrate 101, forms the first insulation layer 102 in described first silicon substrate 101 surface.
Exemplarily, thermal oxidation technology is adopted to form silicon dioxide layer in described first silicon substrate 101 surface, as the first insulation layer 102, in the present embodiment, described thermal oxidation technology is selected as dry method thermal oxidation technology, and the temperature range of oxidation is 900��1200 DEG C, and specifically selecting is 1000 DEG C.
Exemplarily, the thickness of described first insulation layer 102 is for being not less than 5nm, and the thickness of described first insulation layer 102 can be determined according to the temperature and time of thermal oxidation technology. In the present embodiment, the thickness of described first insulation layer 102 is 20nm. Described first insulation layer 102 can in the process of follow-up H or He ion implantation, and the surface of protection silicon is not damaged.
As shown in Fig. 3��Fig. 4, then carry out step 2), carry out peeling off ion implantation to described first silicon substrate 101 based on described first insulation layer 102, in described silicon substrate, interface is peeled off in definition, then removes described first insulation layer 102.
Exemplarily, described stripping ion is H ion, and ion implantation parameter is depending on the required injection degree of depth. Certainly, in other embodiments, it is also possible to select He ion to inject as stripping ion, be not limited to cited example herein.
Exemplarily, described stripping ion in the injection degree of depth of described first silicon substrate 101 be 20��2000nm.
In the present embodiment, after described stripping ion implantation, described first insulation layer 102 is removed completely. The method removed is: adopt the first insulation layer 102 described in HF wet etching, it all to be removed, finally can obtain the first smooth silicon substrate 101 surface.
As shown in figures 5 and 6, step 3 is then carried out), it is provided that the 2nd silicon substrate 201, forms the 2nd insulation layer 202 in described 2nd silicon substrate 201 surface.
Exemplarily, thermal oxidation technology is adopted to form silicon dioxide layer in described 2nd silicon substrate 201 surface, as the 2nd insulation layer 202, in the present embodiment, described thermal oxidation technology is selected as dry method thermal oxidation technology, and the temperature range of oxidation is 900��1200 DEG C, and specifically selecting is 1000 DEG C.
Exemplarily, the thickness of described 2nd insulation layer 202 is for being not less than 5nm, and the thickness of described 2nd insulation layer 202 can be determined according to the temperature and time of thermal oxidation technology. In the present embodiment, the thickness of described 2nd insulation layer 202 is 20nm.
Then step 4 is carried out), form mask layer in described 2nd insulation layer 202 surface, and in forming etching window corresponding to the position preparing transistor channel.
Exemplarily, described mask layer can be photoresist material, silicon nitride or its combination.
As shown in Figure 7, then carry out step 5), etch described 2nd insulation layer 202 based on etching window, formed and be through to described 2nd silicon substrate 201 or bottom remains with part the 2nd insulation layer 202 or bottom remains with 202 grooves 203 of part the 2nd insulation layer.
Exemplarily, in the present embodiment, described groove 203 is through to described 2nd silicon substrate 201, specifically, RIE or ICP dry etching method described 2nd insulation layer 202 of etching can be selected, until when the thickness of described 2nd insulation layer 202 also remains several nanometers, it may also be useful to HF wet etching is removed further, to be formed until the groove 203 of described 2nd silicon substrate 201, and the 2nd silicon substrate 201 in groove 203 is made to obtain smooth surface.
Certainly, it is also possible to removed ground two insulation layer 202 of part by etching, making the 2nd insulation layer 202 remaining with part bottom described groove 203, the thickness of the insulation layer of reservation can be determined according to demand, does not limit herein.
As shown in Fig. 8��Fig. 9, then carry out step 6), it is bonded described first silicon substrate 101 and described 2nd insulation layer 202.
Exemplarily, before bonding, also comprise the step stating the first silicon substrate 101 and described 2nd silicon substrate 201 cleans.
Exemplarily, before bonding, also comprise the step that described first silicon substrate 101 and described 2nd insulation layer 202 surface are carried out plasma hydrophilic treatment.
As shown in Figure 10, finally carry out step 7), carry out annealing process and described first silicon substrate 101 is peeled off from stripping interface, the part being bonded with described 2nd insulation layer 202 is as the silicon top layer of silicon substrate material in insulator islands.
Exemplarily, the atmosphere of annealing process is N2Atmosphere.
Exemplarily, the temperature range of annealing process is 400��500 DEG C, so that described first silicon substrate 101 is peeled off from stripping interface, in the present embodiment, it is 450 DEG C that the temperature of described annealing process is selected.
In addition, also comprise step 8), carry out high temperature (1000��1200 DEG C) annealing, to strengthen described first silicon substrate 101 and the bond strength of described 2nd insulation layer 202.
Finally, adopt CMP that described top layer silicon surface is carried out polishing, obtain the top layer silicon of smooth finish surface.
As shown in figure 11, the present embodiment also provides silicon substrate material in a kind of insulator islands, comprising: bottom silicon 301; Insulation layer 302, is incorporated into described bottom silicon face, and in having corresponding to the position preparing transistor channel until described bottom silicon 301 or bottom remain with the groove 303 of partial insulative layer; Top layer silicon 304, is incorporated into described surface of insulating layer.
Exemplarily, described groove 303 is through to described bottom silicon 301. Certainly, it is possible to so that remaining with the 2nd insulation layer 202 of part bottom described groove 203, the thickness of the insulation layer of reservation can be determined according to demand, does not limit herein.
Exemplarily, described insulation layer 302 is silicon dioxide layer.
Exemplarily, the thickness of described insulation layer 302 is for being not less than 5nm.
Exemplarily, the thickness range of described top layer silicon 304 is 20��2000nm
As mentioned above, silicon substrate material and its preparation method in the insulator islands of the present invention, there is following useful effect: the present invention is by making groove corresponding to preparing in the insulation layer of transistor channel, this groove can completely through between top layer silicon and bottom silicon, can also in groove the insulation layer of retained part so that below the transistor channel of follow-up preparation, there is area of knockout. Present configuration and method are simple, can effectively improve the reliability of device, be with a wide range of applications in field of semiconductor manufacture. So, the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is the principle of illustrative the present invention and effect thereof only, but not for limiting the present invention. Above-described embodiment all under the spirit not running counter to the present invention and category, can be modified or change by any person skilled in the art scholar. Therefore, in art, tool usually intellectual, not departing under disclosed spirit and technological thought all the equivalence modifications completed or change, must be contained by the claim of the present invention such as.
Claims (13)
1. the preparation method of silicon substrate material in an insulator islands, it is characterised in that, described preparation method comprises step:
Step 1), it is provided that the first silicon substrate, forms the first insulation layer in described first surface of silicon;
Step 2), carry out peeling off ion implantation to described first silicon substrate based on described first insulation layer, in described silicon substrate, interface is peeled off in definition, then removes described first insulation layer;
Step 3), it is provided that the 2nd silicon substrate, forms the 2nd insulation layer in described 2nd surface of silicon;
Step 4), form mask layer in described 2nd surface of insulating layer, and in forming etching window corresponding to the position preparing transistor channel;
Step 5), etch described 2nd insulation layer based on etching window, formed and be through to described 2nd silicon substrate or bottom remains with the groove of part the 2nd insulation layer;
Step 6), it is bonded described first silicon substrate and described 2nd insulation layer;
Step 7), carry out annealing process and described first silicon substrate is peeled off from stripping interface, the part being bonded with described 2nd insulation layer is as the silicon top layer of silicon substrate material in insulator islands;
Step 8), carry out high temperature annealing, to strengthen described 2nd silicon substrate and the bond strength of described 2nd insulation layer.
2. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 1) in, adopt thermal oxidation technology to form silicon dioxide layer in described first surface of silicon, as the first insulation layer; Step 3) in, adopt thermal oxidation technology to form silicon dioxide layer in described 2nd surface of silicon, as the 2nd insulation layer.
3. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: the thickness of described 2nd insulation layer is for being not less than 5nm.
4. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 2) in, described stripping ion is H ion or He ion.
5. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 2) in, described stripping ion in the injection degree of depth of described first silicon substrate be 20��2000nm.
6. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 6) also comprise before bonding the step that described first silicon substrate and the 2nd silicon substrate clean.
7. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 7) in, the atmosphere of annealing process is N2Atmosphere.
8. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 7) in, the temperature range of annealing process is 400��500 DEG C, so that described first silicon substrate is peeled off from stripping interface.
9. the preparation method of silicon substrate material in insulator islands according to claim 1, it is characterised in that: step 7) in, also comprise the step that described top layer silicon surface is carried out CMP planarization.
10. silicon substrate material in an insulator islands, it is characterised in that, comprising:
Bottom silicon;
Insulation layer, is incorporated into described bottom silicon face, and in having corresponding to the position preparing transistor channel until described bottom silicon or bottom remain with the groove of partial insulative layer;
Top layer silicon, is incorporated into described surface of insulating layer.
Silicon substrate material in 11. insulator islands according to claim 10, it is characterised in that: described insulation layer is silicon dioxide layer.
Silicon substrate material in 12. insulator islands according to claim 10, it is characterised in that: the thickness of described insulation layer is for being not less than 5nm.
Silicon substrate material in 13. insulator islands according to claim 10, it is characterised in that: the thickness range of described top layer silicon is 20��2000nm.
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Cited By (12)
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| CN109962106A (en) * | 2017-12-14 | 2019-07-02 | 上海新微技术研发中心有限公司 | MOSFET device and method of manufacturing the same |
| CN111076851A (en) * | 2019-12-09 | 2020-04-28 | 中国科学院上海微系统与信息技术研究所 | Pressure sensor and manufacturing method thereof |
| CN111435642A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked semiconductor nanowire structure and preparation method thereof |
| CN111435637A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of SOI substrate with graphical structure |
| CN111435644A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Gate-all-around transistor and preparation method thereof |
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| CN109962106A (en) * | 2017-12-14 | 2019-07-02 | 上海新微技术研发中心有限公司 | MOSFET device and method of manufacturing the same |
| CN111435666A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | SOI substrate with graphical structure and preparation method thereof |
| CN111435649A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof |
| CN111435637A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of SOI substrate with graphical structure |
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| CN111435649B (en) * | 2019-01-11 | 2023-12-01 | 中国科学院上海微系统与信息技术研究所 | Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof |
| CN111435648A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of SOI substrate with graphical structure |
| CN111435642A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked semiconductor nanowire structure and preparation method thereof |
| CN111435641A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked gate-all-around transistor and preparation method thereof |
| CN111435678A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of gate-all-around transistor |
| CN111435678B (en) * | 2019-01-11 | 2021-08-20 | 中国科学院上海微系统与信息技术研究所 | Preparation method of gate-all-around transistor |
| CN111076851B (en) * | 2019-12-09 | 2022-03-29 | 中国科学院上海微系统与信息技术研究所 | Pressure sensor and manufacturing method thereof |
| CN111076851A (en) * | 2019-12-09 | 2020-04-28 | 中国科学院上海微系统与信息技术研究所 | Pressure sensor and manufacturing method thereof |
| CN115881618A (en) * | 2021-09-28 | 2023-03-31 | 苏州华太电子技术股份有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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