CN111435649B - Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof - Google Patents

Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof Download PDF

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CN111435649B
CN111435649B CN201910027054.XA CN201910027054A CN111435649B CN 111435649 B CN111435649 B CN 111435649B CN 201910027054 A CN201910027054 A CN 201910027054A CN 111435649 B CN111435649 B CN 111435649B
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semiconductor
insulating layer
groove
substrate
layer
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CN111435649A (en
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刘强
俞文杰
任青华
陈治西
刘晨鹤
赵兰天
陈玲丽
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

The invention provides a semiconductor nanowire structure based on a graphical SOI substrate and a preparation method thereof, comprising the following steps: ion implantation is carried out in the second semiconductor substrate to form a stripping interface; forming a groove in the first insulating layer, wherein the groove does not penetrate through the first insulating layer; bonding the second semiconductor substrate and the first insulating layer to form a cavity; performing an annealing process to strengthen bonding strength, and stripping the second semiconductor substrate from the stripping interface to form a top semiconductor layer; and patterning and etching the top semiconductor layer to form a semiconductor nanowire structure which is suspended and spans the groove. The SOI substrate with the patterned structure is manufactured firstly, the hollowed-out semiconductor nanowire can be directly manufactured through dry etching, and isotropic wet etching is not needed when the semiconductor nanowire is manufactured, so that the generation of concave cavities can be effectively avoided.

Description

Semiconductor nanowire structure based on graphical SOI substrate and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a semiconductor nanowire structure based on a graphical SOI substrate and a preparation method thereof.
Background
As microelectronic devices continue to shrink, existing FinFET technology is expected to face a larger technology bottleneck at the 5 nm and 3 nm nodes, and device performance is no longer greatly improved as device size continues to decrease. There is a need for new device technologies, such as new device materials (e.g., strained silicon, silicon germanium, group iii-v semiconductors, etc.), and new device structures (e.g., nanowire ring gate transistors, etc.).
The nanowire ring gate transistor can limit the conducting channel to the center of the nanowire instead of the interface between the nanowire and the gate oxide layer, which greatly reduces the scattering of carriers, and is expected to be an important development direction in the future, and further continues the development of moore's law.
The nanowire ring gate transistor has various preparation schemes, one of the simpler preparation methods is to etch out a hollowed nanowire structure based on the SOI substrate and prepare the corresponding ring gate transistor. A representative preparation method of the nanowire ring gate transistor is shown in fig. 1-12, wherein fig. 2 shows a schematic cross-sectional structure of fig. 1 at A-A ', fig. 3 shows a schematic cross-sectional structure of fig. 1 at B-B', and fig. 4-12 have the same correspondence. The method mainly comprises the following steps:
as shown in fig. 1 to 3, step 1) is performed to provide an SOI substrate including a silicon substrate 101, an oxide layer 102 and a top silicon layer 103, and silicon nanowires 104 are etched in the top silicon layer 103 and the oxide layer 102 by a photolithography process and an etching process;
as shown in fig. 4 to 6, step 2) is performed to remove the oxide layer 102 under the silicon nanowire by wet etching to form a hollowed-out hole 105;
as shown in fig. 7 to 9, step 3) is performed to thin the silicon nanowire;
as shown in fig. 10 to 12, step 4) is performed to sequentially deposit a gate dielectric layer 106 and a gate electrode 107 to form a gate-all-around transistor.
The above solution has the following drawbacks:
first, in the step 1), the top silicon layer in the adjacent area of the nanowire and the part of the silicon oxide under the top silicon layer need to be etched away. As shown in fig. 2, during the etching process, the oxide layer 102 needs to be kept from being etched through, and the remaining silicon oxide layer can still keep a certain thickness, so as to prevent the gate electrode and the substrate electrode shown in fig. 11 (as shown by 108 in fig. 11) from having a larger parasitic capacitance or breakdown, which brings a certain requirement to the accuracy of the etching process.
Second, in order to produce a silicon nanowire having a suspended structure, the oxide layer under the nanowire needs to be etched away, and wet etching is usually required, but since wet etching is isotropic etching, the silicon oxide in the remaining exposed area except under the silicon nanowire is also etched away to form an unnecessary concave cavity 109, as shown in fig. 8.
The concave cavity can have the following adverse effects:
fig. 13 and 14 show a top view of the cross section C-C' in fig. 11, and fig. 14 shows an enlarged schematic view of the dashed line box in fig. 13, wherein the concave cavity is finally filled with the gate dielectric layer 106 and the gate electrode 107. In order to ensure good step coverage, an ALD process is generally used to prepare the gate dielectric layer 106 and the gate electrode 107. However, even in the ALD process, when filling a semi-closed structure having a concave shape, early contact interconnection of the film to the film occurs easily during filling of the plating film, and eventually a closed cavity in the gate metal is formed in the concave structure, instead of being completely filled.
As shown in fig. 8, 13 and 14, the corresponding concave cavity 109 in fig. 8 is also filled with the gate dielectric layer 106 and the gate electrode 107, so that the gate electrode under the nanowire is longer than the gate electrode above the nanowire. This can result in: an unnecessary overlapping region is arranged between the bottom layer gate and the source drain, a silicon channel of the region is affected by asymmetrical gate potential, and carriers in the silicon channel are scattered to a certain extent; the resistance between the gate electrode and the source-drain electrode becomes large; the source drain parasitic capacitance becomes large, and the high-frequency characteristic of the device becomes poor; when the silicon channel of the overlapped region is heavily doped, hot electrons are easily generated between the bottom layer gate and the silicon channel of the overlapped region, so that the gate leakage current is increased, and gate oxide is broken down.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor nanowire structure based on a patterned SOI substrate and a method for preparing the same, which are used for solving the problems that a semiconductor nanowire structure prepared by a conventional process in the prior art needs to use a wet etching process to easily generate a concave cavity, and the process stability is low.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor nanowire structure based on a patterned SOI substrate, the method comprising: step 1), providing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating layer on the surface of the first semiconductor substrate, and forming a second insulating layer on the surface of the second semiconductor substrate; step 2), carrying out stripping ion implantation on the first semiconductor substrate based on the first insulating layer, and defining a stripping interface in the first semiconductor substrate; step 3), the first insulating layer is etched in a patterning mode, and grooves penetrating to the first semiconductor substrate are formed; step 4), bonding the first insulating layer and the second insulating layer, wherein the second insulating layer seals the groove to form a cavity; step 5), carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second insulating layer, and stripping the first semiconductor substrate from the stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate; and 6) patterning and etching the top semiconductor layer to form a semiconductor nanowire structure which is suspended and spans the groove.
Optionally, the thickness of the top semiconductor layer is not greater than 50 nm, the total thickness of the first insulating layer and the second insulating layer is not greater than 150 nm, and the depth of the groove is not greater than 50 nm.
Optionally, the bonding atmosphere in step 4) includes hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and during the annealing process in step 5), the mixed gas in the cavity is absorbed by the top semiconductor layer or diffuses out of the top semiconductor layer to reduce the air pressure in the cavity.
Optionally, the annealing process includes annealing at a first temperature to strip the first semiconductor substrate from the peeling interface, and annealing at a second temperature to strengthen the bonding strength of the first insulating layer and the second insulating layer, the first temperature ranging from 200 to 900 ℃ and the second temperature ranging from 400 to 1200 ℃.
Optionally, in step 6), the nanowire structure includes a semiconductor bump located at two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bump.
The invention also provides a preparation method of the semiconductor nanowire structure based on the patterned SOI substrate, which comprises the following steps: step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming a first insulating layer on the surface of the first semiconductor substrate; step 2), carrying out stripping ion implantation on the second semiconductor substrate, and defining a stripping interface in the second semiconductor substrate; step 3), etching the first insulating layer in a patterning way to form a groove in the first insulating layer, wherein the groove does not penetrate through the first insulating layer; step 4), bonding the second semiconductor substrate and the first insulating layer, wherein the second semiconductor substrate seals the groove to form a cavity; step 5), carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second semiconductor substrate, and stripping the second semiconductor substrate from a stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate; and 6) patterning and etching the top semiconductor layer to form a semiconductor nanowire structure which is suspended and spans the groove.
Optionally, the thickness of the top semiconductor layer is not greater than 50 nm, the thickness of the first insulating layer is not greater than 150 nm, and the depth of the recess is not greater than 50 nm.
Optionally, the bonding atmosphere in step 4) includes hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and during the annealing process in step 5), the mixed gas in the cavity is absorbed by the top semiconductor layer or diffuses out of the top semiconductor layer to reduce the air pressure in the cavity.
Optionally, the annealing process includes annealing at a first temperature to strip the second semiconductor substrate from the peeling interface, and annealing at a second temperature to strengthen the bonding strength of the first insulating layer to the second semiconductor substrate, the first temperature ranging from 200 to 900 ℃ and the second temperature ranging from 400 to 1200 ℃.
Optionally, in step 6), the nanowire structure includes a semiconductor bump located at two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bump.
The invention also provides a semiconductor nanowire structure based on the patterned SOI substrate, which comprises the following steps: a semiconductor substrate; the insulation layer is provided with a groove, and the groove does not penetrate through the insulation layer; the semiconductor nanowire structure is suspended and spans the groove; wherein the thickness of the insulating layer is not more than 150 nanometers, and the depth of the groove is not more than 50 nanometers.
Optionally, the nanowire structure comprises a semiconductor boss located at two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor boss.
As described above, the method for fabricating a semiconductor nanowire structure based on a patterned SOI substrate of the present invention has the following advantageous effects:
1) The SOI substrate with the patterned structure is manufactured firstly, the hollowed-out semiconductor nanowire can be directly manufactured through dry etching, and isotropic wet etching is not needed when the semiconductor nanowire is manufactured, so that the generation of concave cavities can be effectively avoided.
2) In the preparation process of the invention, the atmosphere adopted in bonding is selected as hydrogen/nitrogen or mixed gas of oxygen/nitrogen, so that the gas in the cavity of the insulating layer can be diffused from the semiconductor or absorbed by the semiconductor in the following intelligent stripping and high Wen Jiagu bonding processes, and the air pressure in the cavity is reduced, so that the cavity structure has the internal pressure similar to the external atmospheric pressure in the high-temperature environment, the pressure born by the cavity structure is smaller, and the structure is not easily damaged by the internal and external air pressure difference, thereby obtaining the SOI substrate with the patterned structure of the thin-layer top semiconductor layer.
Drawings
Fig. 1 to 14 are schematic structural diagrams showing steps of a method for manufacturing a nanowire ring gate transistor in the prior art.
Fig. 15 to 21 and fig. 29 to 32 show schematic structural views of steps of a method for fabricating a patterned SOI substrate-based semiconductor nanowire structure according to embodiment 1 of the present invention.
Fig. 22 to 28 are schematic structural views showing steps of a method for fabricating a semiconductor nanowire structure based on a patterned SOI substrate according to embodiment 2 of the present invention.
Description of element reference numerals
201. First silicon substrate
202. A first insulating layer
203. Groove
204. Cavity cavity
301. Second silicon substrate
302. Second insulating layer
401. Top silicon layer
501. Silicon nanowire
502. Silicon boss
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 15-32. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 15 to 21 and fig. 29 to 32, the present embodiment provides a method for preparing a silicon nanowire structure based on a patterned SOI substrate, the method comprising:
as shown in fig. 15, step 1) is first performed to provide a first silicon substrate 201 and a second silicon substrate 301, a first insulating layer 202 is formed on the surface of the first silicon substrate 201, and a second insulating layer 302 is formed on the surface of the second silicon substrate 301. Of course, in other embodiments, the first silicon substrate and the second silicon substrate may be made of other semiconductor materials, for example, the first semiconductor substrate and the second semiconductor substrate may be made of one of germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide, and are not limited to the examples listed herein.
For example, a thermal oxidation process is used to form a silicon dioxide layer on the surfaces of the first silicon substrate 201 and the second silicon substrate 301, and the thermal oxidation process is a dry thermal oxidation process, in this embodiment, the oxidation temperature is 900-1200 ℃, and specifically, may be 1000 ℃.
The thickness of the first insulating layer 202 and the second insulating layer 302 may be between 10 nm and 100 nm, respectively, and the thickness of the first insulating layer 202 and the second insulating layer 302 may be determined according to the temperature and time of the thermal oxidation process. For example, in the present embodiment, the thickness of the first insulating layer 202 is not greater than 50 nm, so that the depth of the groove 203 is not greater than 50 nm, and the total thickness of the first insulating layer 202 and the second insulating layer 302 is not greater than 150 nm. The above parameter settings may ensure that a sufficient insulating layer thickness is maintained below the recess 203, e.g. a thickness of 50 nm or more below the recess 203.
In addition, the first insulating layer 202 may protect the surface of silicon from damage during the subsequent implantation of H or He ions.
As shown in fig. 16, step 2) is then performed, in which a lift-off interface is defined in the first silicon substrate 201 by performing lift-off ion implantation on the first silicon substrate 201 based on the first insulating layer 202.
As an example, the stripping ions may be H ions, with ion implantation parameters being dependent on the desired implantation depth. Of course, in other embodiments, he ions may be selected as the stripping ions for implantation, and are not limited to the examples listed herein. The thickness of the subsequent top silicon layer 401 is defined by the depth of the lift-off interface.
As shown in fig. 17, step 3) is then performed to pattern etch the first insulating layer 202, forming a recess 203 extending through to the first silicon substrate 201.
In this embodiment, the patterned etching is anisotropic dry etching, so as to improve the control accuracy of the groove 203.
As shown in fig. 18 to 20, step 4), bonding the first insulating layer 202 and the second insulating layer 302, wherein the second insulating layer 302 closes the groove 203 to form the cavity 204.
As shown in fig. 21, step 5) is then performed, in which an annealing process is performed to strengthen the bonding strength between the first insulating layer 202 and the second insulating layer 302, and the first silicon substrate 201 is peeled from the peeling interface, and the portion bonded to the first insulating layer 202 serves as the top silicon layer 401 of the SOI substrate; wherein, the bonding atmosphere in the step 4) includes hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and during the annealing process in the step 5), the mixed gas in the cavity 204 is absorbed by the top silicon layer 401 or diffused out of the top silicon layer 401, so as to reduce the air pressure in the cavity 204. In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or mixed gas of oxygen/nitrogen, so that the gas in the insulating layer cavity 204 can be diffused from silicon or absorbed by silicon in the following intelligent stripping and high Wen Jiagu bonding processes, and the air pressure in the cavity 204 is reduced, so that the cavity 204 structure has internal pressure similar to the external atmospheric pressure in the high-temperature environment, the pressure born by the cavity 204 structure is smaller, and the structure is not easily damaged by the internal and external air pressure difference, thereby obtaining the SOI substrate with the patterned structure of the thin-layer top silicon layer 401. For example, in this embodiment, the thickness of the top silicon layer 401 is not greater than 50 nm, so that a thinner top silicon layer 401 is prepared, which can effectively expand the application range of the SOI substrate with the patterned structure of the present invention, for example, the method can be used for etching to form hollowed-out silicon nanowires, reduce the etching difficulty of the silicon nanowires, and improve the quality of the silicon nanowires.
Specifically, the annealing process includes annealing at a first temperature to peel the first silicon substrate 201 from the peeling interface, and annealing at a second temperature to strengthen the bonding strength of the first insulating layer 202 and the second insulating layer 302, the first temperature ranging from 200 to 900 ℃ and the second temperature ranging from 400 to 1200 ℃.
For the first and second semiconductor substrates, which are different, the parameters of the above process are as follows:
the top silicon surface is then CMP polished to obtain a top silicon layer 401 with a smooth surface.
As shown in fig. 29 to 32, fig. 29 to 31 correspond to the schematic structural diagram of the dashed box area in fig. 21, fig. 30 is a schematic structural diagram of the cross-section at C-C 'in fig. 29, fig. 31 is a schematic structural diagram of the cross-section at D-D' in fig. 29, and finally step 6) is performed, and the top silicon layer is patterned to form a silicon nanowire 501 structure suspended and crossing the recess.
Specifically, the patterning etching is anisotropic dry etching, and the nanowire structure includes silicon bosses 502 located at two sides of the groove and a plurality of silicon nanowires 501 connected to the silicon bosses 502.
Example 2
As shown in fig. 22 to 32, the present embodiment provides a method for preparing a silicon nanowire structure based on a patterned SOI substrate, the method comprising:
as shown in fig. 22, step 1) is first performed, a first silicon substrate 201 and a second silicon substrate 301 are provided, and a first insulating layer 202 is formed on the surface of the first silicon substrate 201. Of course, in other embodiments, the first silicon substrate and the second silicon substrate may be made of other semiconductor materials, for example, the first semiconductor substrate and the second semiconductor substrate may be made of one of germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide, and are not limited to the examples listed herein.
For example, a thermal oxidation process is used to form a silicon dioxide layer on the surface of the first silicon substrate 201, and as the first insulating layer 202, in this embodiment, a dry thermal oxidation process is selected as the thermal oxidation process, and the oxidation temperature is 900-1200 ℃, specifically, may be 1000 ℃.
As shown in fig. 24, step 2) is then performed to perform a lift-off ion implantation on the second silicon substrate 301, and a lift-off interface is defined in the second silicon substrate 301.
As an example, the stripping ions may be H ions, with ion implantation parameters being dependent on the desired implantation depth. Of course, in other embodiments, he ions may be selected as the stripping ions for implantation, and are not limited to the examples listed herein. The thickness of the subsequent top silicon layer 401 is defined by the depth of the lift-off interface.
As shown in fig. 23, step 3) is performed, and the first insulating layer 202 is patterned to form a groove 203 in the first insulating layer 202, wherein the groove 203 does not penetrate the first insulating layer 202.
In this embodiment, the patterned etching is anisotropic dry etching, so as to improve the control accuracy of the groove 203.
For example, in the present embodiment, the thickness of the first insulating layer 202 is not greater than 150 nm, and the depth of the groove 203 is not greater than 50 nm. The above parameter settings may ensure that a sufficient insulating layer thickness is maintained below the recess 203, e.g. a thickness of 50 nm or more below the recess 203.
As shown in fig. 25 to 26, step 4) is then performed to bond the second silicon substrate 301 and the first insulating layer 202, and the second silicon substrate 301 closes the groove 203 to form the cavity 204.
As shown in fig. 27, step 5) is then performed, in which an annealing process is performed to strengthen the bonding strength between the first insulating layer 202 and the second silicon substrate 301, and the second silicon substrate 301 is peeled from the peeling interface, and the portion bonded to the first insulating layer 202 serves as the top silicon layer 401 of the SOI substrate; wherein, the bonding atmosphere in the step 4) includes hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and in the annealing process in the step 5), the mixed gas in the cavity 204 is absorbed by the top silicon layer 401 or diffused out of the top silicon layer 401, so as to reduce the air pressure in the cavity 204.
In the preparation process of the invention, the atmosphere adopted in bonding is selected to be hydrogen/nitrogen or mixed gas of oxygen/nitrogen, so that the gas in the insulating layer cavity 204 can be diffused from silicon or absorbed by silicon in the following intelligent stripping and high Wen Jiagu bonding processes, and the air pressure in the cavity 204 is reduced, so that the cavity 204 structure has internal pressure similar to the external atmospheric pressure in the high-temperature environment, the pressure born by the cavity 204 structure is smaller, and the structure is not easily damaged by the internal and external air pressure difference, thereby obtaining the SOI substrate with the patterned structure of the thin-layer top silicon layer 401. For example, in this embodiment, the thickness of the top silicon layer 401 is not greater than 50 nm, so that a thinner top silicon layer 401 is prepared, which can effectively expand the application range of the SOI substrate with the patterned structure of the present invention, for example, the method can be used for etching to form hollowed-out silicon nanowires, reduce the etching difficulty of the silicon nanowires, and improve the quality of the silicon nanowires.
Specifically, the annealing process includes annealing at a first temperature to peel the second silicon substrate 301 from the peeling interface, and annealing at a second temperature to strengthen the bonding strength of the first insulating layer 202 and the second silicon substrate 301, the first temperature ranging from 200 to 900 ℃, the second temperature ranging from 400 to 1200 ℃.
For the first and second semiconductor substrates, which are different, the parameters of the above process are as follows:
the top silicon surface is then CMP polished to obtain a top silicon layer 401 with a smooth surface.
It should be noted that the preparation method described above is applicable to wafer level preparation, as shown in fig. 28.
As shown in fig. 29 to 32, wherein fig. 29 to 31 correspond to the schematic structural diagram of the dashed box area in fig. 27, fig. 30 shows the schematic structural diagram of the cross section at C-C 'in fig. 29, fig. 31 shows the schematic structural diagram of the cross section at D-D' in fig. 29, and finally step 6) is performed, the top silicon layer is patterned and etched to form the structure of the silicon nanowire 501 suspended and crossing the groove.
Specifically, the patterning etching is anisotropic dry etching, and the nanowire structure includes silicon bosses 502 located at two sides of the groove and a plurality of silicon nanowires 501 connected to the silicon bosses 502.
It should be noted that the preparation method described above is applicable to wafer level preparation, as shown in fig. 32.
As described above, the preparation method of the silicon nanowire structure based on the patterned SOI substrate has the following beneficial effects:
1) The SOI substrate with the patterned structure is manufactured firstly, the hollowed-out silicon nanowire can be directly manufactured through dry etching, and isotropic wet etching is not needed when the silicon nanowire is manufactured, so that the generation of concave cavities can be effectively avoided.
2) In the preparation process of the invention, the atmosphere adopted in bonding is selected as hydrogen/nitrogen or mixed gas of oxygen/nitrogen, so that the gas in the cavity of the insulating layer can be diffused from silicon or absorbed by the silicon in the subsequent intelligent stripping and high Wen Jiagu bonding processes, and the air pressure in the cavity is reduced, so that the cavity structure has internal pressure similar to the external atmospheric pressure under the high-temperature environment, the pressure born by the cavity structure is smaller, and the structure is not easily damaged by the internal and external air pressure difference, thereby obtaining the SOI substrate with the patterned structure of the thin-layer top silicon layer.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A method for fabricating a semiconductor nanowire structure based on a patterned SOI substrate, the method comprising:
step 1), providing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating layer on the surface of the first semiconductor substrate, and forming a second insulating layer on the surface of the second semiconductor substrate;
step 2), carrying out stripping ion implantation on the first semiconductor substrate based on the first insulating layer, and defining a stripping interface in the first semiconductor substrate;
step 3), patterning and etching the first insulating layer by adopting an anisotropic dry etching process to form a groove penetrating to the first semiconductor substrate;
step 4), bonding the first insulating layer and the second insulating layer, wherein the second insulating layer seals the groove to form a cavity;
step 5), carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second insulating layer, and stripping the first semiconductor substrate from the stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate;
and 6) graphically etching the top semiconductor layer to form a semiconductor nanowire structure which is suspended and spans the groove, wherein the semiconductor nanowire structure comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses, and the width of the groove is smaller than the length of the semiconductor nanowires.
2. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 1, wherein: the thickness of the top semiconductor layer is not more than 50 nanometers, the total thickness of the first insulating layer and the second insulating layer is not more than 150 nanometers, and the depth of the groove is not more than 50 nanometers.
3. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 1, wherein: the bonding atmosphere in step 4) comprises hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and during the annealing process in step 5), the mixed gas in the cavity is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer so as to reduce the air pressure in the cavity.
4. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 1, wherein: the annealing process includes annealing at a first temperature to strip the first semiconductor substrate from a strip interface, and annealing at a second temperature to strengthen a bonding strength of the first insulating layer and the second insulating layer, the first temperature ranging from 200 to 900 ℃ and the second temperature ranging from 400 to 1200 ℃.
5. A method for fabricating a semiconductor nanowire structure based on a patterned SOI substrate, the method comprising:
step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming a first insulating layer on the surface of the first semiconductor substrate;
step 2), carrying out stripping ion implantation on the second semiconductor substrate, and defining a stripping interface in the second semiconductor substrate;
step 3), patterning and etching the first insulating layer by adopting an anisotropic dry etching process to form a groove in the first insulating layer, wherein the groove does not penetrate through the first insulating layer;
step 4), bonding the second semiconductor substrate and the first insulating layer, wherein the second semiconductor substrate seals the groove to form a cavity;
step 5), carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second semiconductor substrate, and stripping the second semiconductor substrate from a stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate;
and 6) graphically etching the top semiconductor layer to form a semiconductor nanowire structure which is suspended and spans the groove, wherein the semiconductor nanowire structure comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses, and the width of the groove is smaller than the length of the semiconductor nanowires.
6. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 5, wherein: the thickness of the top semiconductor layer is not greater than 50 nanometers, the thickness of the first insulating layer is not greater than 150 nanometers, and the depth of the groove is not greater than 50 nanometers.
7. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 5, wherein: the bonding atmosphere in step 4) comprises hydrogen, a mixed gas of hydrogen and nitrogen, a mixed gas of oxygen and nitrogen, oxygen or vacuum, and during the annealing process in step 5), the mixed gas in the cavity is absorbed by the top semiconductor layer or diffused out of the top semiconductor layer so as to reduce the air pressure in the cavity.
8. The method for fabricating a patterned SOI substrate based semiconductor nanowire structure of claim 5, wherein: the annealing process includes annealing at a first temperature to strip the second semiconductor substrate from the peeling interface, and annealing at a second temperature to strengthen the bonding strength of the first insulating layer and the second semiconductor substrate, the first temperature ranging from 200 to 900 ℃ and the second temperature ranging from 400 to 1200 ℃.
9. A patterned SOI substrate-based semiconductor nanowire structure, comprising:
a semiconductor substrate;
the insulation layer is provided with a groove, and the groove does not penetrate through the insulation layer;
a semiconductor nanowire structure suspended in the air and crossing over the groove, wherein the semiconductor nanowire structure is formed by the preparation method of the semiconductor nanowire structure based on the patterned SOI substrate according to any one of claims 1 to 8, the semiconductor nanowire structure comprises semiconductor bosses positioned at two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses, and the width of the groove is smaller than the length of the semiconductor nanowires;
wherein the thickness of the insulating layer is not more than 150 nanometers, and the depth of the groove is not more than 50 nanometers.
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