KR20030034470A - Method for fabricating transistor having silicon-germanium channel - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor including a silicon-germanium(Si- Ge) channel is provided to improve resistance characteristic of source and drain, minimize thermal diffusion of germanium ions, and form the Si-Ge channel exactly by the predetermined length. CONSTITUTION: A Si-Ge channel layer is formed on the active region of a Silicon- On-Insulator(SOI) wafer, consisting of a semiconductor layer(1) and a buried oxide layer(2) by epitaxial growth or ion implementation method. A gate oxide layer is grown on the whole surface of the semiconductor layer and then gate material is deposited on the resultant structure. The gate oxide layer and gate material is over-etched to form a Si-Ge channel(4), when a gate(6) and gate oxide layer pattern(5) are also formed. Source and drain region(7) are formed on the predetermined area by ion implementation and then expitaxially grown to form a source and drain epitaxial layer(8). An insulating layer(9) is formed on the sidewall of the gate. An insulation oxide layer(10) is formed between electrodes formed in contact holes, which are made to expose the gate and source/drain epitaxial layer.

Description

Method for manufacturing a transistor comprising a silicon-germanium channel {METHOD FOR FABRICATING TRANSISTOR HAVING SILICON-GERMANIUM CHANNEL}

The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a transistor including a silicon-germanium channel.

In general, a MOSFET transistor has a structure in which a surface channel is connected between two diffusion junction regions, that is, a source and a drain region. In addition, during the fabrication process of such a transistor, it is common to perform an ion implantation process on the surface channel to adjust the threshold voltage.

Recently, silicon-germanium channels by germanium ion implantation have been used to improve the characteristics of PMOS transistors. When using silicon-germanium channels, the conductivity of the electrons in the drain becomes higher, resulting in higher conductivity throughout the device and higher mobility in the surface channels.

Conventional methods for forming silicon-germanium channels are as follows. First, a sacrificial oxide film is formed on a semiconductor substrate on which an element isolation film is formed, followed by ion implantation of germanium ions using the sacrificial oxide film as a protective film. Then, the sacrificial oxide film is removed and subsequent processes such as gate formation are followed.

By the way, in the prior art, germanium ion implantation is performed over the entire operation region of the semiconductor substrate. That is, germanium ion implantation is performed not only in the region where the channel is to be formed, but also in the region where the source / drain is to be formed. Therefore, the resistance characteristics of the source / drain become worse, and thermal diffusion of germanium ions implanted into the source / drain region during the source / drain diffusion cannot be prevented, so that the length of the channel becomes much shorter than the desired length, which makes it difficult to control the characteristics.

Accordingly, the present invention has been made to solve the above problems, the object of the present invention is to improve the resistance characteristics of the source / drain, to minimize the thermal diffusion of germanium ions, silicon-germanium exactly as desired length It is to provide a method of manufacturing a transistor comprising a silicon-germanium channel capable of forming a channel.

1 to 5 are cross-sectional views of process steps of a method of manufacturing a transistor including a silicon-germanium channel according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: Semiconductor Substrate 2: Buried Oxide

3: Device Separator 4: Silicon-Germanium Channel

5: gate oxide film 6: gate

7: source / drain region 8: source / drain epitaxial layer

9: sidewall insulating layer 10: inter-electrode insulating oxide film

11: electrode

In order to achieve the above object, the present invention forms a silicon-germanium channel layer on the entire operation region of a semiconductor substrate, and then removes a predetermined portion of the silicon-germanium channel layer through transient etching during gate etching, thereby removing silicon-germanium only on the lower portion of the gate. Provided is a method for manufacturing a transistor comprising a silicon-germanium channel, characterized in that to form a channel.

According to the present invention, a method of manufacturing a transistor including a silicon germanium channel includes forming a silicon germanium channel layer on an entire surface of an operating region of a semiconductor substrate, and forming a gate oxide layer and a gate material layer on the silicon germanium channel layer. Successively forming, selectively etching the gate material layer, the gate oxide layer and the silicon-germanium channel layer to form a silicon-germanium channel having the same length as the gate, the gate oxide layer and the gate, and source / drain ion implantation Forming a source / drain region at a predetermined portion of the semiconductor substrate and epitaxially growing the source / drain region to form a source / drain epitaxial layer; forming a sidewall insulating film on the sidewall of the gate; An inter-electrode insulating oxide film is formed on the entire surface of the gate and source / drain epitaxial layers. Forming a contact hole so that each of the predetermined portions is exposed, and forming an electrode in each contact hole.

In the manufacturing method of the present invention, the silicon-germanium channel layer may be formed by ion implantation or epitaxial growth. In the case of ion implantation, the selective etching of the silicon-germanium channel layer is performed by ion implantation energy. In the epitaxial growth method, an SOI; Silicon-On-Insulator) Silicon wafers can be used. Using SOH wafer, before and after the step of forming the silicon-germanium channel layer, the thicknesses of the semiconductor substrates can be measured and compared based on the buried oxide film, and the silicon-germanium channel layer can be selectively etched by the thickness difference. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5 are cross-sectional views of process steps of a method of manufacturing a transistor including a silicon-germanium channel according to an embodiment of the present invention.

This embodiment uses a silicon-on-insulator (SOI) wafer as a semiconductor substrate. However, conventional bulk wafers can also be used, and SOI wafers can be used for monitoring with bulk wafers. As shown in FIG. 1, the SOI wafer has a structure in which a buried oxide film 2 is formed inside the semiconductor substrate 1. The investment oxide film 2 performs a specific function in connection with the present invention, which will be described later. In addition, an element isolation film 3 is formed in a predetermined region of the semiconductor substrate 1. The element isolation film 3 is formed by a local oxidation method or a trench isolation method known in the art. The region between the device isolation films 3 is defined as the operation region of the transistor.

Subsequently, as shown in FIG. 2, a silicon-germanium channel layer 4a is formed on the semiconductor substrate 1, that is, on the operating region. The silicon-germanium channel layer 4a is formed by the epitaxial growth method in this embodiment, or may be formed by the ion implantation method in another embodiment. When the ion implantation method is used, a protective film such as a sacrificial oxide film may be used. The silicon-germanium channel layer 4a is formed to a thickness of approximately 300 to 500 kPa.

After the silicon-germanium channel layer 4a is formed, a gate oxide film is grown on the entire surface of the semiconductor substrate 1 by a known method and a gate material is deposited thereon. The gate material layer and the gate oxide layer are etched in a predetermined gate pattern to form the gate 6 and the gate oxide layer 5 below it, as shown in FIG. 3. The gate 6 has a laminated structure of, for example, a polysilicon layer, a tungsten nitride film, a tungsten layer, and a hard mask layer, wherein the polysilicon layer is about 700 GPa, the tungsten nitride film and the tungsten layer are about 800 GPa, and the hard mask layer is about 2000 GPa. Has a lamination thickness.

On the other hand, the present invention is characterized by performing excessive etching during the gate pattern etching. The transient etching is for removing a portion of the silicon-germanium channel layer (4a in FIG. 2) to form the silicon-germanium channel 4. That is, the excessive etching may be made by the thickness of the silicon-germanium channel layer to be removed. When the silicon-germanium channel layer is formed by the ion implantation method, excessive etching is performed according to the depth according to the ion implantation energy, and when the silicon-germanium channel layer is formed by the epitaxial growth method, the semiconductor substrate before and after the epitaxial growth, respectively. Measure and compare the thickness of the over-etched by that much. At this time, the above-described buried oxide film 2 is usefully used as a reference layer for thickness measurement.

As described above, the silicon germanium channel 4 is formed only in the lower portion of the gate oxide film 5 by transient etching. Thereafter, source / drain regions 7 are formed in predetermined portions of the semiconductor substrate through source / drain ion implantation.

Subsequently, as shown in FIG. 4, the source / drain region 7 is epitaxially grown to form the source / drain epitaxial layer 8, and a sidewall insulating film ( 9) form. Conventionally, thermal diffusion is performed after source / drain ion implantation to form source / drain regions, but in the present invention, epitaxial growth is performed after source / drain ion implantation. Therefore, the thermal diffusion of germanium ions is minimized while not affecting the length of the silicon-germanium channel, and the resistance characteristics of the source / drain are improved.

Subsequently, as shown in FIG. 5, an inter-electrode insulating oxide film 10 such as BPSG is formed on the entire surface of the resultant, and a predetermined portion of the gate 6 and the source / drain epitaxial layer 8 are exposed. A contact hole is formed if possible. Then, an electrode 11 is formed in each contact hole.

As described above, the present invention forms the silicon-germanium channel layer on the entire operation region of the semiconductor substrate, and then removes a portion of the silicon-germanium channel layer through the excessive etching during the gate etching, thereby removing the silicon-germanium channel only on the lower portion of the gate. As a result, the silicon-germanium channel can be formed exactly as long as desired. That is, since the length of the silicon-germanium channel is determined by the length of the gate, it is easy to control the characteristics.

In addition, since the source / drain is formed by the epitaxial growth method after the source / drain ion implantation, thermal diffusion of germanium ions is minimized, thereby not affecting the length of the silicon-germanium channel and improving the resistance characteristics of the source / drain.

The present invention is not only useful for controlling the channel length of DRAM cell transistors, but also for peripheral devices in other memory devices. In addition, the present invention can be applied to a specific application integrated circuit (ASIC) or a logic device.

In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (7)

Forming a silicon-germanium channel layer over an operating region of the semiconductor substrate; Continuously forming a gate oxide layer and a gate material layer on the silicon-germanium channel layer; Selectively etching the gate material layer, the gate oxide layer, and the silicon-germanium channel layer to form a gate, a gate oxide layer, and a silicon-germanium channel having the same length as the gate; Forming a source / drain region on a predetermined portion of the semiconductor substrate through source / drain ion implantation and epitaxially growing the source / drain region to form a source / drain epitaxial layer; Forming a sidewall insulating film on sidewalls of the gate; Forming an inter-electrode insulating oxide film on the entire surface of the resultant, and forming contact holes to expose predetermined portions of the gate and the source / drain epitaxial layer, respectively; And Forming a electrode in each of the contact holes; and manufacturing a transistor comprising a silicon-germanium channel. The method of claim 1, wherein the forming of the silicon germanium channel layer is performed by ion implantation. The method of claim 1, wherein the forming of the silicon-germanium channel layer is performed by an epitaxial growth method. 4. The method of claim 3, wherein the semiconductor substrate is an S-OI wafer having a buried oxide film formed therein. 4. The method of claim 3, wherein the semiconductor substrate is a bulk wafer. The transistor of claim 2, wherein the selective etching of the silicon-germanium channel layer is performed by ion implantation energy used in an ion implantation method for forming the silicon-germanium channel layer. Manufacturing method. The method of claim 4, wherein the selective etching of the silicon-germanium channel layer is performed by measuring and comparing the thicknesses of the semiconductor substrates based on the buried oxide layer before and after forming the silicon-germanium channel layer, respectively. Method of manufacturing a transistor comprising a silicon-germanium channel characterized in that performed as much.