KR20010004237A - A method for forming semiconductor memory device including self-aligned contact process - Google Patents

A method for forming semiconductor memory device including self-aligned contact process Download PDF

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KR20010004237A
KR20010004237A KR1019990024860A KR19990024860A KR20010004237A KR 20010004237 A KR20010004237 A KR 20010004237A KR 1019990024860 A KR1019990024860 A KR 1019990024860A KR 19990024860 A KR19990024860 A KR 19990024860A KR 20010004237 A KR20010004237 A KR 20010004237A
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spacer
etching barrier
insulating layer
film
forming
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KR1019990024860A
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Korean (ko)
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김동석
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김영환
현대전자산업 주식회사
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Publication of KR20010004237A publication Critical patent/KR20010004237A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

PURPOSE: A method for manufacturing a semiconductor memory device including a self-aligned contact process is provided to improve an electrical characteristic, by guaranteeing a sufficient contact region in a cell region without varying a layout or having an influence on a peripheral circuit region. CONSTITUTION: A gate having a mask insulating layer(23) is formed on a semiconductor substrate(20). The first etching barrier-insulating layer is formed on the resultant structure. The first etching barrier insulating layer is anisotropically etched to form the first spacer(24) on a side wall of the gate. The second etching barrier-insulating layer is formed on the resultant structure. The second etching barrier insulating layer in a peripheral circuit region is selectively and anisotropically etched to form the second spacer, wherein the first and second spacers constitute a lightly doped drain(LDD) spacer. A planarized interlayer dielectric oxide layer is formed on the resultant structure. The interlayer dielectric oxide layer in a cell region and the second etching barrier insulating layer are selectively etched to form a self-aligned contact hole.

Description

자기정렬 콘택 공정을 포함하는 반도체 메모리 소자 제조방법{A method for forming semiconductor memory device including self-aligned contact process}A method for forming semiconductor memory device including self-aligned contact process

본 발명은 반도체 기술에 관한 것으로, 특히 자기정렬 콘택(self-aligned contact, SAC) 공정을 포함하는 반도체 메모리 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a semiconductor memory device including a self-aligned contact (SAC) process.

SAC 공정은 절연막 간의 식각 선택비를 이용하여 콘택 공정의 마진을 크게 증가시킬 수 있으며, 양산성 면에서도 문제가 없어 고집적 반도체 메모리 소자 제조에 널리 사용되고 있다.SAC process can greatly increase the margin of the contact process by using the etching selectivity between the insulating film, there is no problem in terms of mass production is widely used in the manufacture of highly integrated semiconductor memory device.

통상적인 SAC 공정은 식각 베리어로 실리콘질화막(Si3N4) 또는 실리콘산화질화막(SiOxNy)을 사용하고 있다.A typical SAC process uses a silicon nitride film (Si 3 N 4) or a silicon oxynitride film (SiO x N y) as an etching barrier.

첨부된 도면 도 1은 종래기술에 따라 자기정렬 콘택홀이 형성된 반도체 메모리 소자의 단면을 도시한 것으로, 이하 이를 참조하여 설명한다.1 is a cross-sectional view of a semiconductor memory device having a self-aligned contact hole according to the related art, which will be described below with reference to the drawings.

종래기술에 따른 SAC 공정은, 우선 게이트 산화막(11), 게이트 전극(12), 마스크 절연막(13)이 형성된 실리콘 기판(10) 상에 LDD(lightly doped drain) 구조 형성을 위한 절연막을 증착하고 이를 이방성 전면 식각하여 절연막 스페이서(14)를 형성한다. 이때, 절연막 스페이서(14)는 셀 영역 및 주변회로 영역에 같은 프로파일로 형성된다. 소오스/드레인 이온주입 공정은 그 설명을 생략한다.In the SAC process according to the related art, an insulating film for forming a lightly doped drain (LDD) structure is first deposited on a silicon substrate 10 on which a gate oxide film 11, a gate electrode 12, and a mask insulating film 13 are formed. Anisotropic full surface etching is performed to form the insulating film spacers 14. At this time, the insulating film spacer 14 is formed in the same profile in the cell region and the peripheral circuit region. The source / drain ion implantation process omits the description.

다음으로, 전체구조 상부에 SAC 공정을 위한 베리어 질화막(15)을 증착한다.Next, the barrier nitride film 15 for the SAC process is deposited on the entire structure.

계속하여, 전체구조 상부에 평탄화된 층간절연 산화막(16)을 형성하고, 층간절연 산화막(16) 및 베리어 질화막(15)을 선택 식각하여 자기정렬 콘택홀을 형성한다.Subsequently, the planarized interlayer insulating oxide film 16 is formed over the entire structure, and the interlayer insulating oxide film 16 and the barrier nitride film 15 are selectively etched to form self-aligned contact holes.

상기와 같은 종래의 SAC 공정을 실시하는 경우, 게이트 전극(14) 간의 간격이 주변회로 영역에 비해 좁은 셀 영역에서 게이트 전극(워드라인) 측벽에 절연막 스페이서(14) 및 스페이서 형태의 베리어 질화막(15)이 배치되므로 실질적인 콘택 영역을 충분히 확보할 수 없어 소자의 전기적 특성이 열화되는 문제점이 있었다. 미설명 도면 부호 'a'는 콘택 영역의 선폭을 나타낸 것이다.In the conventional SAC process, the insulating film spacer 14 and the barrier nitride film 15 in the form of a spacer are formed on the sidewalls of the gate electrode (word line) in the cell region where the gap between the gate electrodes 14 is narrower than that of the peripheral circuit region. ), There is a problem in that the substantial contact area cannot be sufficiently secured, so that the electrical characteristics of the device are deteriorated. Unexplained reference numeral 'a' indicates a line width of the contact region.

본 발명은 반도체 메모리 소자의 자기정렬 콘택(SAC) 공정시 셀 영역에서 충분한 콘택 영역을 확보할 수 있는 반도체 메모리 소자 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of securing a sufficient contact region in a cell region during a self-aligned contact (SAC) process of a semiconductor memory device.

도 1은 종래기술에 따라 자기정렬 콘택홀이 형성된 반도체 메모리 소자의 단면도.1 is a cross-sectional view of a semiconductor memory device having a self-aligned contact hole formed in accordance with the prior art.

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정도.2A to 2C illustrate a semiconductor device manufacturing process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 실리콘 기판 21 : 게이트 산화막20 silicon substrate 21 gate oxide film

22 : 게이트 전극 23 : 마스크 절연막22 gate electrode 23 mask insulating film

24 : 제1 스페이서 25 : 제2 스페이서 질화막24: first spacer 25: second spacer nitride film

25a : 제2 스페이서 26 : 포토레지스트 패턴25a: second spacer 26: photoresist pattern

27 : 층간절연 산화막27: interlayer insulating oxide film

상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 메모리 소자 제조방법은, 반도체 기판 상에 마스크 절연막을 구비한 게이트를 형성하는 제1 단계; 상기 제1 단계를 마친 전체구조 상부에 제1 식각 베리어 절연막을 형성하는 제2 단계; 상기 제1 식각 베리어 절연막을 이방성 식각하여 상기 게이트 측벽에 제1 스페이서를 형성하는 제3 단계; 상기 제2 단계를 마친 전체구조 상부에 제2 식각 베리어 절연막을 형성하는 제4 단계; 주변회로 영역의 상기 제2 식각 베리어 절연막을 선택적으로 이방성 식각하여 상기 제1 스페이서와 함께 LDD 스페이서를 이루는 제2 스페이서를 형성하는 제5 단계; 상기 제5 단계를 마친 전체구조 상부에 평탄화된 층간절연 산화막을 형성하는 제6 단계; 및 셀 영역의 상기 층간절연 산화막 및 상기 제2 식각 베리어 절연막을 선택 식각하여 자기정렬 콘택홀을 형성하는 제7 단계를 포함하여 이루어진다.A characteristic semiconductor memory device manufacturing method of the present invention for solving the above technical problem, the first step of forming a gate having a mask insulating film on a semiconductor substrate; A second step of forming a first etching barrier insulating layer on the entire structure of the first step; A third step of anisotropically etching the first etching barrier insulating layer to form a first spacer on the sidewall of the gate; A fourth step of forming a second etching barrier insulating film on the entire structure of the second step; A fifth step of selectively anisotropically etching the second etching barrier insulating layer in the peripheral circuit region to form a second spacer forming an LDD spacer together with the first spacer; A sixth step of forming a planarized interlayer insulating oxide film on the entire structure of the fifth step; And a seventh step of selectively etching the interlayer dielectric oxide film and the second etching barrier insulating film in the cell region to form a self-aligning contact hole.

LDD 구조 형성을 위한 절연막 스페이서는 주로 주변회로 영역의 트랜지스터의 특성에 영향을 미치며, 베리어 질화막(또는 산화질화막)은 주로 셀 영역에서 SAC 공정을 수행하는데 필요한 것이다. 본 발명은 스페이서 셀 영역과 주변회로에 서로 다른 스페이서 식각 공정을 수행함으로서 주변회로 영역에서는 필요한 스페이서 절연막의 두께를 확보하고, 셀 영역에서는 기존의 베리어 질화막의 두께 만큼의 콘택 영역을 더 확보할 수 있다.The insulating film spacer for forming the LDD structure mainly affects the characteristics of the transistors in the peripheral circuit region, and the barrier nitride film (or oxynitride film) is mainly required to perform the SAC process in the cell region. According to the present invention, by performing different spacer etching processes on the spacer cell region and the peripheral circuit, the thickness of the spacer insulating film required in the peripheral circuit region may be secured, and the contact region as much as the thickness of the existing barrier nitride layer may be further secured in the cell region. .

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2C illustrate a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.

본 실시예에 따른 공정은 우선, 도 2a에 도시된 바와 같이 게이트 산화막(21), 게이트 전극(22), 마스크 절연막(23)(산화막/산화질화막 또는 산화막/질화막 또는 질화막/산화질화막)이 형성된 실리콘 기판(20) 상에 제1 스페이서 질화막을 증착하고 이를 이방성 전면 식각하여 제1 스페이서(24)를 형성한다. 이때, 제1 스페이서 질화막은 종래의 스페이서 질화막보다 얇은 두께로 증착하며, 제1 스페이서(24)는 셀 영역 및 주변회로 영역에 같은 프로파일로 형성된다. 이때, 실리콘 기판(20)에는 LDD 이온주입 공정을 마친 상태이다.In the process according to the present embodiment, first, as shown in FIG. 2A, a gate oxide film 21, a gate electrode 22, and a mask insulating film 23 (oxidation film / oxynitride film or oxide film / nitride film or nitride film / oxynitride film) are formed. The first spacer nitride film is deposited on the silicon substrate 20 and then anisotropically etched to form the first spacer 24. In this case, the first spacer nitride film is deposited to a thickness thinner than that of the conventional spacer nitride film, and the first spacer 24 is formed in the same profile in the cell region and the peripheral circuit region. At this time, the silicon substrate 20 is in a state of completing the LDD ion implantation process.

다음으로, 도 2b에 도시된 바와 같이 전체구조 상부에 제2 스페이서 질화막(25)을 증착하고, 셀 영역을 덮는 포토레지스트 패턴(26)을 형성한 다음 이를 식각 마스크로 사용하여 주변회로 영역의 제2 스페이서 질화막(25)을 이방성 건식 식각함으로써 제2 스페이서(25a)를 형성한다. 이때, 제2 스페이서 질화막(25)은 상기 제1 스페이서(24)와 함께 주변회로 영역에서 LDD 구조 형성에 필요한 두께를 이룰 수 있는 두께로 증착한다. 이후, 소오스/드레인 이온 주입을 실시한다.Next, as shown in FIG. 2B, a second spacer nitride layer 25 is deposited on the entire structure, a photoresist pattern 26 covering the cell region is formed, and the second spacer nitride layer 26 is formed as an etching mask. The second spacer 25a is formed by anisotropic dry etching the two spacer nitride film 25. In this case, the second spacer nitride layer 25 is deposited together with the first spacer 24 to a thickness capable of forming a thickness necessary for forming the LDD structure in the peripheral circuit region. Thereafter, source / drain ion implantation is performed.

계속하여, 도 2c에 도시된 바와 같이 포토레지스트 패턴(26)이 제거된 상태에서, 전체구조 상부에 평탄화된 층간절연 산화막(27)을 형성하고, 셀 영역에서 층간절연 산화막(27) 및 제2 스페이서 질화막(25)을 선택 식각하여 자기정렬 콘택홀을 형성한다.Subsequently, in the state where the photoresist pattern 26 is removed, as shown in FIG. 2C, a planarized interlayer insulating oxide film 27 is formed on the entire structure, and the interlayer insulating oxide film 27 and the second interlayer insulating film 27 are formed in the cell region. The spacer nitride layer 25 is selectively etched to form a self-aligned contact hole.

상기와 같은 공정을 실시하는 경우, 주변회로 영역에서는 LDD 구조에 적당한 두께의 스페이서를 얻을 수 있으며, 셀 영역에서는 기존의 베리어 질화막 만큼의 콘택 영역이 더 확보할 수 있게 된다. 미설명 도면 부호 'b'는 콘택 영역의 선폭을 나타낸 것으로, 상기 도 1의 콘택 영역의 선폭(a)에 비해 증가되었음을 알 수 있다.In the case of performing the above process, a spacer having a thickness suitable for the LDD structure can be obtained in the peripheral circuit region, and in the cell region, the contact region as much as the existing barrier nitride layer can be further secured. Reference numeral 'b', which is not described, indicates the line width of the contact region, and it can be seen that the line width is increased compared to the line width a of the contact region of FIG.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 제1 및 제2 스페이서의 재료로서 질화막을 사용하였으나, 본 발명은 제1 및/또는 제2 스페이서의 재료로서 산화질화막을 사용하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the nitride film is used as the material of the first and second spacers, but the present invention can be applied to the case of using the oxynitride film as the material of the first and / or second spacers.

전술한 본 발명은 레이아웃의 변경이나 주변회로 영역에의 영향 없이 셀 영역에서 충분한 콘택 영역을 확보할 수 있으며, 이로 인하여 소자의 전기적 특성을 향상시키는 효과가 있다.The present invention described above can secure a sufficient contact area in the cell area without changing the layout or the influence of the peripheral circuit area, thereby improving the electrical characteristics of the device.

Claims (3)

반도체 기판 상에 마스크 절연막을 구비한 게이트를 형성하는 제1 단계;Forming a gate having a mask insulating film on the semiconductor substrate; 상기 제1 단계를 마친 전체구조 상부에 제1 식각 베리어 절연막을 형성하는 제2 단계;A second step of forming a first etching barrier insulating layer on the entire structure of the first step; 상기 제1 식각 베리어 절연막을 이방성 식각하여 상기 게이트 측벽에 제1 스페이서를 형성하는 제3 단계;A third step of anisotropically etching the first etching barrier insulating layer to form a first spacer on the sidewall of the gate; 상기 제2 단계를 마친 전체구조 상부에 제2 식각 베리어 절연막을 형성하는 제4 단계;A fourth step of forming a second etching barrier insulating film on the entire structure of the second step; 주변회로 영역의 상기 제2 식각 베리어 절연막을 선택적으로 이방성 식각하여 상기 제1 스페이서와 함께 LDD 스페이서를 이루는 제2 스페이서를 형성하는 제5 단계;A fifth step of selectively anisotropically etching the second etching barrier insulating layer in the peripheral circuit region to form a second spacer forming an LDD spacer together with the first spacer; 상기 제5 단계를 마친 전체구조 상부에 평탄화된 층간절연 산화막을 형성하는 제6 단계; 및A sixth step of forming a planarized interlayer insulating oxide film on the entire structure of the fifth step; And 셀 영역의 상기 층간절연 산화막 및 상기 제2 식각 베리어 절연막을 선택 식각하여 자기정렬 콘택홀을 형성하는 제7 단계A seventh step of forming a self-aligned contact hole by selectively etching the interlayer dielectric oxide film and the second etch barrier insulating film in a cell region 를 포함하여 이루어진 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 식각 베리어 절연막이,The first etching barrier insulating film, 질화막 또는 산화질화막인 것을 특징으로 하는 반도체 소자 제조방법.A semiconductor device manufacturing method characterized in that the nitride film or oxynitride film. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2 식각 베리어 절연막이,The second etching barrier insulating film, 질화막 또는 산화질화막인 것을 특징으로 하는 반도체 소자 제조방법.A semiconductor device manufacturing method characterized in that the nitride film or oxynitride film.
KR1019990024860A 1999-06-28 1999-06-28 A method for forming semiconductor memory device including self-aligned contact process KR20010004237A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420119B1 (en) * 2001-05-04 2004-03-02 삼성전자주식회사 Semiconductor device having LDD-type source/drain regions and fabrication method thereof
KR100653035B1 (en) * 2001-12-18 2006-11-30 매그나칩 반도체 유한회사 Method of forming a dielectric spacer in a semiconductor device
KR100733140B1 (en) * 2006-06-13 2007-06-28 삼성전자주식회사 Method of forming an etching mask
KR100905999B1 (en) 2007-06-12 2009-07-06 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100931479B1 (en) * 2002-11-06 2009-12-11 매그나칩 반도체 유한회사 Manufacturing method of semiconductor device
US7749846B2 (en) 2007-04-12 2010-07-06 Samsung Electronics Co., Ltd. Method of forming contact structure and method of fabricating semiconductor device using the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420119B1 (en) * 2001-05-04 2004-03-02 삼성전자주식회사 Semiconductor device having LDD-type source/drain regions and fabrication method thereof
US7388264B2 (en) 2001-05-04 2008-06-17 Samsung Electronics Co., Ltd. Semiconductor device having LDD-type source/drain regions and fabrication method thereof
KR100653035B1 (en) * 2001-12-18 2006-11-30 매그나칩 반도체 유한회사 Method of forming a dielectric spacer in a semiconductor device
KR100931479B1 (en) * 2002-11-06 2009-12-11 매그나칩 반도체 유한회사 Manufacturing method of semiconductor device
KR100733140B1 (en) * 2006-06-13 2007-06-28 삼성전자주식회사 Method of forming an etching mask
US7749846B2 (en) 2007-04-12 2010-07-06 Samsung Electronics Co., Ltd. Method of forming contact structure and method of fabricating semiconductor device using the same
KR100905999B1 (en) 2007-06-12 2009-07-06 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US7687341B2 (en) 2007-06-12 2010-03-30 Hynix Semiconductor Inc. Method for fabricating semiconductor device

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