JP2002026309A - Manufacturing method of field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a field-effect transistor, which uses a replacement gate process. SOLUTION: An interlayer insulating film 2 is formed on a substrate 1, and it is vertically removed relative to the substrate 1 so that a part of the substrate 1 is exposed. A silicon nitride film 3 is allowed to stick for covering the interlayer insulating film 2, which is etched so as to remain only on a side surface of the interlayer insulating film 2 to provide a replacement gate wall 4. The interlayer insulating film 2 is removed and ion is implanted with the replacement gate wall 4 as a mask. The implanted ion is annealed for diffusion to form a source diffusion layer 5 and a drain diffusion layer 6. An interlayer insulating film 7 is formed to cover the replacement gate wall 4, the source diffusion layer 5, and the drain diffusion layer 6, and then flattened up to the upper part of the replacement gate wall 4. The replacement gate wall 4 is removed and a gate insulating film 8 and a gate electrode 9 are formed in a gate region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a field effect transistor (FET), and more particularly, to a method of manufacturing an FET manufactured by using a replacement gate process.

[0002]

2. Description of the Related Art Along with miniaturization of an FET structure, it is desired to make a gate oxide film as a gate insulating film thinner. For example, to put the desired FET structure into practical use,
It is required that the gate length be 100 nm or less, and accordingly, the thickness of the gate oxide film is required to be 2 nm or less. However, when the thickness of the gate oxide film is 2 nm or less, the leak current increases, and as a result, the power consumption increases and the circuit operation deteriorates, so that it has been difficult to put the gate oxide film to practical use. Therefore, as a gate insulating film,
A method of reducing a leakage current by using a high dielectric film having a higher relative dielectric constant than an oxide film (SiO ₂ ) to reduce the physical film thickness and increase the electrical film thickness has been adopted. . However, since many high-dielectric materials have low heat resistance (for example, the heat resistance temperature of BST is 800 ° C.), activation annealing (about 1000 ° C.) for forming the source diffusion layer and the drain diffusion layer is performed. Is performed, silicide and a compound such as SiO ₂ are formed by a reaction between the high dielectric film and the gate electrode, or SiO ₂ or the like is formed by interfacial oxidation between the high dielectric film and the silicon substrate. A layer having a lower dielectric constant than the dielectric constant of the dielectric film is formed. The formed layer having a low relative dielectric constant is connected in series with the high dielectric film, thereby reducing the gate capacitance. As a result, the gate capacitance of the high dielectric film used to increase the gate capacitance is reduced. The effect of increase cannot be obtained.

As a method of manufacturing an FET that solves such a problem, a method of manufacturing an FET that performs an annealing process after forming a gate insulating film and a gate electrode is described below.
There is a method of manufacturing an FET using a replacement gate process in which a gate insulating film and a gate electrode are formed after an annealing process. In a method of manufacturing a MOSFET using a replacement gate process, a dummy replacement gate wall to be removed in a later step is provided for ion implantation for forming a source diffusion layer and a drain diffusion layer. Next, an annealing process for diffusing implanted ions is performed to form a source diffusion layer and a drain diffusion layer, and the replacement gate wall is removed to form a gate insulating film and a gate electrode. In the method using the replacement gate process, a material having low heat resistance can be used as a material for the gate insulating film and the gate electrode.

FIGS. 2A to 2F are cross-sectional views showing a method of manufacturing a semiconductor device using a conventional replacement gate process. The manufacturing method shown in FIG. 2 is a method for manufacturing an FET using a replacement gate process. In FIG. 2, 2
1 is a substrate made of Si or the like, 22 is a substituted gate insulating film made of SiO ₂ or the like, 23 is a substituted gate wall made of a silicon nitride film, 24 is a source diffusion layer, 25 is a drain diffusion layer,
26 is an interlayer insulating film made of PSG or the like, 27 is a gate insulating film made of Al ₂ O ₃ or the like, 28 is a gate electrode made of Al or the like, 29 is a mask, 30 is an interlayer insulating film made of PSG or the like, and 31 is Al And the like.

Next, a method of manufacturing the same will be described.

[0006] First, as shown in FIG. ₂ (a), SiO 2
Onto a silicon substrate 21 on which an insulating film made of
For example, after a silicon nitride film is deposited by a CVD method, a mask is formed using a photo-developing technique, and the insulating film and the silicon nitride film are selectively etched to form a replacement gate insulating film 22 and a replacement gate wall 23. Is formed, and the substrate 21 where the replacement gate insulating film 22 and the replacement gate wall 23 are not formed is exposed.

Next, as shown in FIG. 2B, after As.sup. ⁺ Is ion-implanted into the silicon substrate 21 using the replacement gate wall 23 as a mask, an annealing process is performed to activate the implanted ions and to perform the source implantation. A diffusion layer 24 and a drain diffusion layer 25 are formed. Next, an interlayer insulating film 26 made of PSG or the like is formed so as to cover the replacement gate wall 23.

[0008] Next, as shown in FIG.
(Chemical mechanical polishing) or the like, using an interlayer insulating film 2
6 is flattened. The planarization is performed until the upper part of the replacement gate wall 23 is exposed.

Next, as shown in FIG. 2D, the replacement gate wall 23 and the replacement gate insulating film 22 are selectively etched by a highly selective etching method. At this time,
In order to form the replacement gate wall 23 by etching,
It is necessary to use a material having a higher etching selectivity than the interlayer insulating film 25 as a material of the replacement gate wall 23. Normally, when silicon is used for the substrate 21, a silicon dioxide-based material such as BPSG, SiO ₂ , and PSG is used for the interlayer insulating film 26. As a combination of a material that can be used in a silicon manufacturing process and has a higher etching selectivity than a silicon dioxide-based material and an etching method, a combination of an etching method using silicon nitride and hot phosphoric acid is optimal. For this purpose, silicon nitride is used as the material of the replacement gate wall 23.

Next, as shown in FIG. 2E, an insulating film layer 27 and a gate electrode 28 are formed by using a growth method having good covering properties.

Next, as shown in FIG. 2F, a mask 29 is formed using, for example, a photo-developing technique, and the gate electrode 28 and the gate insulating film 27 are selectively etched. Next, the mask 29 is removed.

Finally, as shown in FIG. 2G, an interlayer insulating film 30 made of PSG or the like is formed so as to cover the whole, and the gate electrode 27, the source diffusion layer 24, and the drain diffusion layer 25 are formed. Interlayer insulating film 3 to make contact
0, a contact hole is formed, and the contact hole is filled with a wiring metal such as Al. Next, a wiring layer 31 made of a wiring metal such as Al is formed to obtain an FET.

[0013]

However, the first problem is that when forming a replacement gate wall, anisotropic etching is performed between a silicon nitride film as a material of the replacement gate wall and silicon as a substrate. It is difficult to obtain desired selectivity, and the silicon substrate is also etched.

The reason is that an etching gas (chlorine-based, sulfur-based,
F ₆ system, etc.), and there is a property of etching a silicon substrate.

The second problem is that the silicon nitride film used for the replacement gate wall is a material that is difficult to etch, and the thickness to be etched is the height of the replacement gate wall.
It is difficult to form the replacement gate wall perpendicular to the substrate.

The reason is that, since the film thickness to be etched to form the replacement gate is the height of the gate and the etching is performed in a wide range, the etching accuracy greatly affects the gate shape.

The necessity of the vertical gate shape will be described. In FET structures that require high integration,
The shape in which the gate is not vertical and the gate length is increased due to etching as in the related art does not fit the actual condition because there is no room for pattern design. Also, in order to form the gate insulating film and the gate electrode in the trench after removing the replacement gate wall having a high aspect ratio, the gate formed vertically is formed more vertically than the conventional shape in which the gate length is increased by etching. The shape is easier. That is, as the gate length becomes shorter and the pattern is designed with higher integration, the aspect ratio of the gate shape becomes larger. As a result, if the gate shape is not vertically formed, the gate required for a highly integrated FET structure is required. The shape cannot be physically obtained. This requires that the replacement gate wall be formed vertically.

The third problem is that the processing accuracy of the replacement gate wall and the replacement gate insulating film is determined by the precision of the photo-developing technique and the etching technique, so that the gate length required for practical use is 100 nm or less. It is very difficult to form a fine replacement gate wall.

Therefore, in order to solve the above-mentioned conventional problems, an object of the present invention is to provide a method of manufacturing an FET in which the influence of the selectivity of anisotropic etching upon forming a replacement gate wall is reduced. .

Another object of the present invention is that the shape of the replacement gate wall is determined by the shape of the wall of the interlayer insulating film or the like formed in advance, so that the shape of the replacement gate wall perpendicular to the substrate can be easily obtained. An object of the present invention is to provide a method for manufacturing an FET.

Still another object of the present invention is to provide a method of manufacturing an FET in which a fine replacement gate wall is formed with high accuracy, assuming that the gate length is determined by the growth film thickness of the replacement gate wall.

[0022]

To achieve the above object, a first aspect of the present invention is an electric field effect device having a gate region, a source diffusion layer, and a drain diffusion layer on a substrate using a replacement gate process. Forming a first interlayer insulating film on the substrate; removing the first interlayer insulating film from the substrate to expose a part of the substrate; Forming a replacement gate wall in the gate region by depositing a silicon nitride film covering the first interlayer insulating film and etching the silicon nitride film so as to remain on a side surface of the first interlayer insulating film. And the first
Removing the interlayer insulating film.

In the method of manufacturing a semiconductor device according to the present invention, the gate length is determined by the growth thickness of the replacement gate wall, and the shape of the replacement gate wall is determined by the shape of the previously formed interlayer insulating film wall. Further, a replacement gate process for controlling the processing shape of the replacement gate wall with high precision is used.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, in order to clarify the above and other objects, features, and advantages of the present invention, embodiments of the present invention will be described below with reference to the accompanying drawings. .

FIG. 1 is a diagram illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device shown in FIG. 1 is an n-type MO using a replacement gate process.
SFET. In FIG. 1, 1 is a substrate made of Si or the like, 2 is an interlayer insulating film made of silicon dioxide (SiO ₂ ) or the like, 3 is a silicon nitride film, 4 is a replacement gate wall made of silicon nitride or the like, 5 is a source diffusion layer, 6 is a drain diffusion layer, 7 is an interlayer insulating film made of SiO ₂ or the like, 8 is Al ₂ O ₃
, A gate electrode made of Al or the like, 10 a mask, 11 an interlayer insulating film made of PSG or the like, and 12 a wiring layer made of Al or the like.

Next, the manufacturing method will be described.

[0027] First, as shown in FIG. 1 (a), after the film thickness on the silicon substrate 1 was formed an SiO ₂ interlayer insulating film 2 of 150~400nm by CVD, for example, SiO ₂ interlayer insulating film by dry etching 2 is selectively etched. At this time, since the shape of the wall of the interlayer insulating film formed by the etching becomes the shape of the replacement gate wall, a material that can be processed with high precision such as SiO ₂ is used as the material of the interlayer insulating film 2. Next, a silicon nitride film 3 is attached so as to cover the exposed silicon substrate 1 and the interlayer insulating film 2. The silicon nitride film 3 is formed by using a method such as CVD that can form a uniform film covering the substrate 1 and the interlayer insulating film 2 while maintaining the shapes of the exposed substrate 1 and interlayer insulating film 2. The thickness of the silicon nitride film attached here becomes the gate length.

Next, the silicon nitride film 3 on the side surface of the interlayer insulating film 2 perpendicular to the substrate is not etched by anisotropic dry etching using, for example, a CHF ₃ -based gas, but is horizontally The silicon nitride film 3 on the surface of the substrate 1 and the silicon nitride film 3 on the surface of the interlayer insulating film 2 are etched. By this anisotropic etching, FIG.
As shown in FIG. 2, only the silicon nitride film 3 formed on the upper surface of the substrate 1 and the interlayer insulating film 2 in the horizontal direction with respect to the substrate 1 is selectively etched to form an interlayer in the vertical direction with respect to the substrate 1. Only the silicon nitride film 3 on the side surface of the insulating film 2 is left. The remaining silicon nitride film 3 forms the replacement gate wall 4
Becomes

Next, as shown in FIG. 1C, only the SiO ₂ interlayer insulating film 2 is etched using, for example, hydrofluoric acid.

Next, as shown in FIG. 1 (d), As ⁺ is implanted with an implantation energy of 1 to 10 keV and an implantation concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^{−2 using} the replacement gate wall 4 as a mask. It is injected into the substrate 1 under the conditions. Next, the implanted ions are activated by performing an annealing process at 900 to 1100 ° C. in a nitrogen atmosphere, for example, to form a source diffusion layer 5 and a drain diffusion layer 6 having a depth of 30 to 100 nm.

Next, as shown in FIG.
An interlayer insulating film 7 made of BPSG or the like is formed so as to cover the replacement gate wall 4 by the VD method, and the interlayer insulating film 7 is flattened using, for example, a technique such as CMP (chemical mechanical polishing). The planarization is performed until the upper part of the replacement gate wall 4 is exposed.

Next, for example, as shown in FIG.
Silicon nitride is about 2 times larger than silicon oxide film such as BPSG.
Utilizing the property of hot phosphoric acid that dissolves 0 times faster, only the replacement gate wall 4 is etched without etching the interlayer insulating film 7 to form a groove for the gate electrode.

Next, for example, as shown in FIG.
Fifth of Chemical Vapor Deposition in 1999
Volume 1 pages 7-9 (Chemical Vapor Deposition, V
ol. 5, No. 1, p. 7-8, 1999). ALD (Atomic Layer Deposit) performed under an atmosphere of Al (CH ₃ ) ₃ gas and H ₂ O, which is a film formation method described in the above-mentioned method.
On), an Al ₂ O ₃ film is deposited to a thickness of 2 nm by the method, and then Al is formed to a thickness of 50 nm by reflow sputtering to form a gate insulating film 8 and a gate electrode 9 in order. I do. The ALD method is a method having a very good covering property in which an Al ₂ O ₃ film can be formed one atomic layer at a time.
An l ₂ O ₃ film can be formed.

Next, as shown in FIG. 1H, a mask 10 is formed using, for example, a photo-developing technique, and the gate electrode 9 and the gate insulating film 8 are selectively dry-etched. Next, the mask 10 is removed.

Finally, as shown in FIG. 1I, an interlayer insulating film 11 made of PSG or the like is formed so as to cover the whole.
Gate electrode 9, source diffusion layer 5, and drain diffusion layer 6
A contact hole is formed in the interlayer insulating film 11 so that the contact can be made, and the contact hole is filled with Al or the like. Next, a wiring layer 12 made of Al or the like is formed and F
ET is obtained.

That is, in the above-described embodiment, first, the interlayer insulating film 2 on the substrate 1 is formed on the substrate 1 along one of the outer sides of one of the replacement gate walls 4 where the replacement gate wall 4 is to be formed. The wall of the interlayer insulating film 2 is formed by vertical etching. Next, a silicon nitride film 3 to be a replacement gate wall 4 later is attached so as to cover the interlayer insulating film 2. At this time, the silicon nitride film 3 which becomes the replacement gate wall 4 is adhered to the silicon nitride film 3 by using a method having good coverage.
Has a shape following the shape of the interlayer insulating film 2 etched perpendicularly to the substrate 1. The silicon nitride film 3 serving as the replacement gate wall 4 is formed so as to cover the substrate 1 and the interlayer insulating film 2, and is formed on the upper surface of the substrate 1 and the interlayer insulating film 2 by anisotropic etching. 3 is removed to leave only the silicon nitride film 3 on the side surface of the interlayer insulating film 2. The gate length formed by such a process is:
The thickness is the same as the thickness of the attached silicon nitride film 3. Also,
The film thickness to be etched becomes the gate length. This makes it possible to reduce the thickness of the film to be etched, as compared with the conventional method in which the film thickness to be etched is the height of the gate, and suppress the influence of the etching. According to the method of depositing the silicon nitride film 3 using the CVD method, it is possible to sufficiently suppress the degree of variation of the in-plane film thickness to within ± 10% at the minimum film thickness of 5 nm, which is required for practical use.
It is possible to accurately form a fine gate length of nm.

In the above embodiment, the high dielectric film is made of Al_Two
O_ThreeHowever, in the present invention, the high dielectric film is Si
O_TwoIt is intended to have a higher relative dielectric constant than
Al_TwoO _ThreeInstead of, for example, if the heat resistance is 800 ° C or less
A certain BST, Ta_TwoO_Three, HfO_Two, ZrO_Two , PLZ
T, SrTiO_Three And Si_ThreeN_FourEtc. can also be used
You. In the above embodiment, As⁺ N by injection of
The case of applying the replacement gate process to the type FET
As described above, the replacement gate process is applied to the p-type FET.
In this case, As⁺ B instead of⁺ , B
F_Two ⁺, And In⁺ Etc. can be used.

In this embodiment, the replacement gate wall is formed vertically, but if there is a margin in the gate length, the replacement gate wall may be tapered. In this case, the coatability and flatness of the gate insulating film and the gate electrode formed later are improved, and the lamination process is facilitated.

It should be noted that the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope of the technical idea of the present invention.

[0040]

As described above, the first effect of the present invention is that it is hardly affected by anisotropic etching. The reason is that CHF ₃ used for anisotropic etching
This is because the substrate is not etched instead of the gas and the thickness of the anisotropic etching is reduced from the gate height to the gate length, so that the influence of the anisotropic etching can be reduced.

A second effect of the present invention is that a replacement gate wall having a gate length of 100 nm or less, which is desired for practical use, can be formed. The reason is that the gate length is determined not by the conventional photo-developing technique and etching technique but by the growth film thickness.

A third effect of the present invention is that the replacement gate wall can be formed in a shape perpendicular to the substrate. The reason is that the shape of the replacement gate wall is determined by the shape of the wall of the interlayer insulating film made of a material that can be processed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1, 21 substrate 2, 7, 11, 26, 30 interlayer insulating film 3 silicon nitride film 4, 23 replacement gate wall 5, 24 source diffusion layer 6, 25 drain diffusion layer 8, 27 gate insulating film 9, 28 gate electrode 10 , 29 Mask 12, 31 Wiring layer 22 Replacement gate insulating film

Claims (6)

[Claims] 1. A method for manufacturing a field effect transistor for manufacturing a gate region, a source diffusion layer, and a drain diffusion layer on a substrate by using a replacement gate process, comprising: forming a first interlayer insulating film on the substrate; Forming, removing the first interlayer insulating film from the substrate, and exposing a part of the substrate; adhering a silicon nitride film covering the first interlayer insulating film;
Forming a replacement gate wall in the gate region by etching the silicon nitride film and leaving the silicon nitride film on a side surface of the first interlayer insulating film; and removing the first interlayer insulating film. A method for manufacturing a field-effect transistor. 2. A replacement gate wall is formed in said gate region by depositing a silicon nitride film covering said first interlayer insulating film and etching said silicon nitride film to remain on the side surface of said first interlayer insulating film. Forming the silicon nitride film by CVD to cover the exposed substrate and the first interlayer insulating film; and forming an upper surface of the exposed substrate and an upper surface of the first interlayer insulating film. Forming the replacement gate wall by removing the silicon nitride film formed in step (i) and leaving the silicon nitride film formed on the side surface of the first interlayer insulating film. The method for manufacturing a field-effect transistor according to claim 1. 3. The method according to claim 2, further comprising the steps of: implanting ions using the replacement gate wall as a mask; and diffusing the implanted ions by annealing to form the source diffusion layer and the drain diffusion layer. The method for manufacturing a field-effect transistor according to claim 1. 4. A step of forming a second interlayer insulating film covering the replacement gate wall, the source diffusion layer, and the drain diffusion layer, and placing the second interlayer insulating film on the replacement gate wall. 4. The method for manufacturing a field-effect transistor according to claim 1, further comprising a step of polishing until GaN is exposed. 5. The method according to claim 1, wherein said second interlayer insulating film is made of SiO ₂ , P
5. The method for manufacturing a field-effect transistor according to claim 4, wherein SG or BPSG is used. 6. The method for manufacturing a field effect transistor according to claim 1, wherein said silicon nitride film is removed by said etching using CHF ₃ gas.