JP2000349289A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench gate structure where it can prevent decline in the gate dielectric breakdown voltage of the device, and a method for manufacturing the device. SOLUTION: A semiconductor device is manufactured, in such a way that after a trench groove is formed into silicon 3 and the internal surface of the groove is covered with a gate oxide film 1, the groove is filled up with a vapor- phase deposited polysilicon 2, and the polysilicon 2 is back-etched until the gate oxide film 1 formed on the flat section of the silicon 3 is exposed (a). Then a thick oxide film 4 (CVD oxide film) is vapor-phase deposited on the flat section of the silicon 3 and the surface of the polysilicon 2 (b). Thereafter, the oxide film 4 is removed by subjecting it to back etching the film 4, until the surface of the flat section of the silicon 3 is exposed (c). Moreover, a screen oxide film 5 is formed on the surface of the flat section of the silicon 3 and the surface of the oxide film 4 (d). Since the thick oxide film 4 is formed, the quality of the gate oxide film 1 is maintained at a high level, and the decline of the gate withstand voltage of the semiconductor device can be prevented. Since the gate oxide film 1 is not damaged, additionally reliability of the gate withstand voltage of the device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a trench gate structure.

[0002]

2. Description of the Related Art In recent years, a trench gate structure has been adopted in order to improve the ON characteristics and ON resistance of IGBTs (insulated gate bipolar transistors), MOSFETs (MOS gate field effect transistors), MOS thyristors (MOS gate thyristors), and the like. More and more. This trench gate structure digs a trench,
The surface of this groove is covered with a gate oxide film, and the trench groove covered with the gate oxide film is filled with polysilicon to be a gate electrode.

Thereafter, an ion implantation step of As or the like is performed to form a source region and a drain region. In order to prevent damage to the surface of silicon in the ion implantation step, a film having a thickness of about 50 nm is formed. A screen oxide film is formed on the silicon surface.

FIGS. 5A to 5C are cross-sectional views showing a main part of a manufacturing method for forming a conventional trench gate structure part in order of steps.

In FIG. 1A, a trench is formed in a silicon 23 and is covered with a gate oxide film 21. Then, the polysilicon 22 doped with an n-type impurity or a p-type impurity (D-Poly-Si: Doped Poly)
-Silicon) to fill the trench with silicon 2
The polysilicon 22 is back-etched until the gate oxide film 21 formed on the flat portion 3 is exposed. By this back etching, the surface of the polysilicon 22 is lower in height than the surface of the gate oxide film 21 formed on the silicon flat portion.

In FIG. 1B, etching is performed to remove the gate oxide film 21 formed on the flat portion of the silicon 23. By this etching, the gate oxide film 21
Is lower than the height D of the surface of the polysilicon 22 by the thickness of the gate oxide film 21.

In FIG. 1C, the screen oxide film 25 is formed thereafter.

Although not shown, to form a source region thereafter, ions are implanted through a screen oxide film with As or the like as described above.

[0009]

In this screen oxide film forming step, a screen oxide film 25 is formed on each of the silicon surface, the polysilicon surface, and the portion A between the polysilicon and silicon. The screen oxide film 25 formed on the polysilicon 22 lacks denseness and has low electrical breakdown strength. However, since an interlayer insulating film or the like is formed on a surface of the polysilicon 22 in a later step (not shown), electrical insulation between the polysilicon 22 and a wiring formed on the interlayer insulating film (not shown) is reduced. Good.

However, silicon 23 and polysilicon 2
2 between the silicon 23 (where the source region is formed) and the polysilicon 22 (the gate electrode) because the dielectric breakdown strength of the screen oxide film 25 formed from the polysilicon side is small The dielectric breakdown voltage of the device decreases. That is, at this point A, the gate withstand voltage decreases.

The gate oxide film 21 formed on the flat portion of the silicon 23 without forming the screen oxide film 25
Is used in place of the screen oxide film 25, impurities to be ion-implanted enter the gate oxide film 21 at the portion A sandwiched between the silicon 23 and the polysilicon 22, and the dielectric strength of the gate oxide film 21 is reduced. .

An object of the present invention is to provide a semiconductor device having a trench gate structure and a method of manufacturing the same, which can solve the above-mentioned problems and can prevent a decrease in gate breakdown voltage.

[0013]

In order to achieve the above object, in a semiconductor device having a trench gate structure, a gate electrode formed in a trench with a first insulating film interposed therebetween and a first insulating layer in the trench groove are formed. A second layer formed on the film and on the gate electrode at the same height as the surface of the semiconductor substrate;
A structure including an insulating film.

In a method for manufacturing a semiconductor device having a trench gate structure, a step of forming a trench in a semiconductor substrate, a step of forming a first insulating film on the surface of the semiconductor substrate and the surface of the trench, Forming a gate electrode having a height lower than the surface height of the semiconductor substrate, forming a second insulating film higher than the surface height of the semiconductor substrate on the first insulating film and the gate electrode, Removing the first insulating film until the surface of the semiconductor substrate is exposed;
Forming a third insulating film on the surface of the semiconductor substrate and the surface of the second insulating film.

It is preferable that the first insulating film is a gate oxide film and the third insulating film is a screen oxide film.

Preferably, the gate electrode is formed of polysilicon.

By doing so, no ion species is introduced into the first insulating film serving as the gate oxide film in the subsequent ion implantation step via the second insulating film, and By forming the second insulating film, the film quality of the first oxide film sandwiched between the gate electrode and the semiconductor substrate can be kept good.

A fourth insulating film is formed on the first insulating film and the gate electrode.
Forming an insulating film, leaving only the fourth insulating film on the gate electrode, and removing the first insulating film and the fourth insulating film until the surface of the semiconductor substrate under the exposed first insulating film is exposed. And a manufacturing method including the steps.

Preferably, the fourth insulating film is an oxide film formed by a CVD method.

[0020]

FIG. 1 is a sectional view showing a main part of a trench gate structure according to a first embodiment of the present invention.

A trench having a depth of about 3 μm and a width of about 1 μm is selectively formed in a semiconductor substrate (silicon 3). A gate oxide film 1 having a thickness of about 1000 ° is formed on the side and bottom of the trench. This trench is filled with polysilicon 2 serving as a gate electrode. This polysilicon 2 is doped polysilicon (D-Poly-Si) doped with n-type or p-type impurities. C on polysilicon 1
The oxide film 4 formed by the VD method is reduced to the thickness 2 of the gate oxide film 1.
It is formed with a thickness of about 2 to 4 times. On the surface of the silicon 3, a source region 11, a source electrode (not shown), and the like are formed.

In the semiconductor device having the above-mentioned trench gate structure, the film quality of the gate oxide film 1 is ensured, and a decrease in gate breakdown voltage can be prevented. Further, since the oxide film 4 covers the gate oxide film 1, the gate oxide film 1 is not damaged in the ion implantation step, and the reliability of the gate breakdown voltage is improved. In addition, 12 is a well region and 13 is a base region.

FIGS. 2A to 2D show a method of manufacturing a trench gate structure according to a second embodiment of the present invention. FIGS. 2A to 2D are cross-sectional views showing main steps in the order of steps.

In FIG. 2A, the silicon 3 has a depth of 3
A trench having a width of about 1 μm and a thickness of about 1 μm is formed.
A gate oxide film 1 of about 000 ° is covered. Then n
2 (D-Poly-Si: Doped Poly-Si) doped with a p-type impurity or a p-type impurity
The silicon 2 is back-etched until the gate oxide film 1 formed on the flat portion of the silicon 3 is exposed. By this back etching, the surface of the polysilicon 2 is lower in height than the surface of the gate oxide film 1 formed on the flat portion of the silicon 3.

In FIG. 1B, an oxide film 4 (CVD oxide film) is deposited in a vapor phase on the flat portion of the silicon 3 and the surface of the polysilicon 2 to a film thickness of about 1 μm by the CVD method.

In FIG. 1C, the oxide film 4 is removed by back etching using RIE (reactive ion etching) until the surface of the flat portion of the silicon 3 is exposed.

In FIG. 2D, a screen oxide film 5 is formed on the surface of the flat portion of the silicon 3 and the surface of the oxide film 4 to a thickness of about 50 nm.

Although not shown, as described above, ions are implanted through the screen oxide film 5 with As or the like in order to form a source region thereafter.

By this manufacturing process, oxide film 4 is formed on gate oxide film 1 in contact with polysilicon 2, so that impurities implanted in the ion implantation process do not directly enter gate oxide film 1. . Further, since there is no screen oxide film 5 formed from the side of the polysilicon 2 at the location B corresponding to the location A shown in FIG. 5C, the quality of the gate oxide film 1 is ensured to be high quality, A decrease in withstand voltage can be prevented. Further, since the gate oxide film 1 is not damaged, the reliability of the gate breakdown voltage can be improved.

FIG. 3 shows the distribution of the gate breakdown voltage of the semiconductor device having the trench gate structure according to the present invention and the conventional trench gate structure. FIG. 3A shows the trench gate structure of the present invention, and FIG. ) Is a conventional trench gate structure. With the trench gate structure of the present invention, the gate breakdown voltage of the semiconductor device can be distributed to a higher side. That is, a decrease in gate breakdown voltage can be prevented.

FIGS. 4A to 4E show a method of manufacturing a trench gate structure according to a third embodiment of the present invention. FIGS. 4A to 4E are sectional views showing main steps in the order of steps.

Referring to FIG. 2A, a trench is formed in silicon 3, a thermal oxide film serving as gate oxide film 1 is formed on the entire surface to a thickness of 2000.degree., And polysilicon 2 is filled in the trench. After etch back, CVD
-Oxide film 6 (Chemical Vapor Depo)
oxide film formed by the position method)
It is grown to 5000 ° and heat treated.

In FIG. 2B, a resist 7 is patterned on the trench by a photolithography process.

In FIG. 3C, the resist 7
Isotropic chemical dry etching (CD
In step E), the CVD-oxide film 6 and the gate oxide film 1 are removed by etching so that the gate oxide film 1 on the silicon 3 remains thin.

In FIG. 4D, the resist 7 is peeled off.

In FIG. 3E, the gate oxide film 1 and the CVD-oxide film 6 formed in the trench portions are removed by wet etching on the entire surface. At this time, the gate oxide film 1 on the silicon 3 is completely removed, but the CVD-oxide film 6 on the upper side wall portion E of the trench remains. This is because the etchant in the upper side wall portion E of the trench stagnates, making wet etching difficult. Thereafter, a screen oxide film 5 is formed. As described above, since the CVD oxide film on the upper side wall portion E of the trench remains, the film quality of the gate oxide film is ensured at a high quality, the gate breakdown voltage can be prevented from lowering, and the reliability is improved. improves.

Further, even when a pattern shift occurs due to the patterning of the resist, the C on the side wall portion E of the trench upper portion is not removed.
Since the VD-oxide film remains, it is possible to prevent a decrease in the gate withstand voltage as described above.

[0038]

According to the present invention, a decrease in gate breakdown voltage can be prevented by ensuring a high quality of the gate insulating film. Further, since the gate insulating film is not damaged by the ion implantation, the reliability of the gate withstand voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a trench gate structure according to a first embodiment of the present invention;

FIGS. 2A to 2D are cross-sectional views of a main part process in a second embodiment of the present invention, showing a method of manufacturing a trench gate structure in the order of steps.

3A and 3B show distributions of gate breakdown voltages of a semiconductor device having a trench gate structure according to the present invention and a conventional trench gate structure, wherein FIG. 3A shows the trench gate structure of the present invention, and FIG. Of breakdown voltage of gate breakdown voltage

FIGS. 4A to 4E show a method of manufacturing a trench gate structure according to a third embodiment of the present invention, wherein FIGS.

FIGS. 5A to 5C are cross-sectional views of a main part process in a conventional manufacturing method for forming a trench gate structure portion shown in the order of processes.

[Explanation of symbols]

 Reference Signs List 1 gate oxide film 2 polysilicon 3 silicon 4 oxide film 5 screen oxide film 6 CVD-oxide film 7 resist 11 source region 12 well region 13 base region 21 gate oxide film 22 polysilicon 23 silicon 25 screen oxide film A, B location C , D Surface height E Top trench location of trench

Claims (6)

[Claims] In a semiconductor device having a trench gate structure, a surface of a semiconductor substrate is formed on a gate electrode formed in a trench via a first insulating film, on the first insulating film in the trench, and on the gate electrode. A semiconductor device, comprising: a second insulating film formed at the same height as the height. 2. A method of manufacturing a semiconductor device having a trench gate structure, wherein: a step of forming a trench in a semiconductor substrate; a step of forming a first insulating film on the surface of the semiconductor substrate and the surface of the trench; A step of forming a gate electrode having a height lower than the surface height of the semiconductor substrate, a step of forming a second insulating film higher than the surface height of the semiconductor substrate on the first insulating film and the gate electrode, 2 insulating film and 1st
A method for manufacturing a semiconductor device, comprising: a step of removing an insulating film until a surface of a semiconductor substrate is exposed; and a step of forming a third insulating film on the surface of the semiconductor substrate and the surface of the second insulating film. 3. The method according to claim 2, wherein the first insulating film is a gate oxide film, and the third insulating film is a screen oxide film. 4. The method according to claim 2, wherein the gate electrode is formed of polysilicon. 5. A step of forming a fourth insulating film on the first insulating film and the gate electrode, a step of leaving only the fourth insulating film on the gate electrode, and a step of exposing the semiconductor substrate under the exposed first insulating film. 3. The method according to claim 2, further comprising the step of removing the first insulating film and the fourth insulating film until the semiconductor device is exposed. 6. The method according to claim 5, wherein the fourth insulating film is an oxide film formed by a CVD method.