JP2005093773A - Trench gate type semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench gate type semiconductor device capable of easily and inexpensively forming and taking out a gate electrode, and to provide a memthod for manufacturing it. <P>SOLUTION: The method for manufacturing the trench gate type semiconductor device comprises the steps of removing all oxide film after forming a trench, then forming a gate insulating film, and filling the gate electrode in the trench. After that, the gate electrode is flattened by grinding with the gate insulating film as a stopper. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a trench gate type semiconductor device and a method for manufacturing a trench gate type semiconductor device, and more particularly to a trench gate type semiconductor device and a method for manufacturing a trench gate type semiconductor device in which variation in electrical characteristics is suppressed.

  Conventionally, there is a trench MOSFET as a trench gate type semiconductor device (hereinafter referred to as a trench MOS type semiconductor device) having a structure in which a gate insulating film is formed in a trench. FIGS. 13 and 14 are views showing a structure in the middle of manufacturing a trench MOSFET manufactured by a conventional manufacturing method. FIG. 13 is a plan view of a main part, and FIG. FIG. 14E is a cross-sectional view corresponding to FIG.

    In FIG. 13, a gate electrode 8 such as polycrystalline silicon is formed in the trench 4 and the trench 4 via the gate insulating film 7, and the gate electrode 8 is drawn from the end of the trench 4 to the thick oxide film 31. . An interlayer insulating film 13 shown in FIG. 14E is formed on the gate electrode 8 on the thick oxide film 31, and a contact hole is formed in the interlayer insulating film 13 so that the gate electrode 8 and the gate electrode wiring 15 are formed. Connected.

Conventionally, a thick oxide film 31 is first formed on the surface of an n-type silicon semiconductor substrate 1 having an n ⁺ drain region 11, and then a p-type well region 2 is formed on the surface layer of the semiconductor substrate 1, A mask made of oxide film 3 having a desired pattern is formed on the surface of region 2, trench etching is performed on silicon semiconductor substrate 1 in the opening of oxide film 3, and trench 4 is formed in silicon semiconductor substrate 1. At this time, the SiO ₂ type side wall protective film 5 is formed on the trench side wall (FIG. 14A). The sidewall protective film 5 is removed using an etchant such as hydrofluoric acid. At this time, the oxide film 3 recedes from the trench 4 and the opening of the oxide film 3 expands (FIG. 14B). Thereafter, damage in the trench 4 is removed by hydrogen annealing. At this time, the side walls 41 and 42 of the trench 4 are flattened, and the corner portions 43, 44, 45 and 46 are rounded (FIG. 14C). Thereafter, the gate insulating film 7 is formed, the trench 4 is filled with a gate electrode 8 such as polycrystalline silicon, and etching back is performed leaving the leading portion 81 on the thick oxide film 31 (FIG. 14D). Thereafter, the source region 9 is diffused and formed by impurity implantation and drive using the gate electrode 8 as a mask, and an interlayer insulating film 13 for insulating the gate electrode 8 and the source electrode 12 is formed. Then, the source electrode 12 electrically connected to the source region 9 and the base contact region 10 and the drain electrode 14 connected to the drain region 11 are formed (FIG. 14E). In this way, a trench MOSFET is formed.

  However, the conventional manufacturing method described above has the following problems.

  First, as shown in FIG. 14D, when the gate electrode 8 is deposited in the trench 4 and then etched back so that the upper end is lower than the opening of the trench 4, the shape controllability is poor and the receding distance. There is a problem that 15 wafer in-plane variations and lot-to-lot variations become large. Further, as a result, there is a problem that the depth of the source region 9 varies and the variation in electrical characteristics increases.

  Second, as shown in FIG. 14E, in the configuration in which the opening of the trench 4 is embedded with the interlayer insulating film 13 such as BPSG, a high temperature process is performed due to the difference in thermal expansion coefficient between the semiconductor substrate 1 and the interlayer insulating film 13. In this case, a stress is generated, and the semiconductor substrate 1 is cracked to increase the leakage current.

  Third, if the etch back amount of the gate electrode 8 is reduced in order to avoid the second problem, an etching residue may occur on the surface of the semiconductor substrate. If this etching residue remains connected to the gate electrode, it contacts the source electrode and shorts the gate and source. Thus, there is a problem that the defect rate increases.

  Fourth, when the hydrogen annealing process is performed on the inner wall of the trench when the oxide film is retracted as shown in FIG. 14B, as shown in FIG. 15 which is an enlarged view of the round portion 6 in FIG. In addition, a strain 16 is generated at the boundary between the oxide film 3 and silicon on the surface of the well region 2, and an electric field is concentrated between the lead portion 81 of the gate electrode 8 and the strain 16 shown in FIG. There was a problem that the withstand voltage was lowered.

  As a means for avoiding the first drawback, a method of performing etch back using CDE is disclosed in Patent Document 1, but the second and third problems cannot be solved.

  Further, in Japanese Patent Application No. 2002-262500 filed by the same applicant as the present application, as a method of solving the first to third problems, a gate lead-out groove is formed separately from the trench 4, and the CMP is performed. Similarly, in Japanese Patent Application No. 2002-301158, as a method for solving the fourth problem, hydrogen annealing is performed in a state where a nitride film is formed at the trench edge where the oxide film has receded. A method for increasing the breakdown voltage by preventing the formation of the strained portion by performing the processing is disclosed.

However, Japanese Patent Application No. 2002-262500 and Japanese Patent Application No. 2002-301158 require an additional process, which increases costs. Moreover, since each cannot solve all the problems, it is necessary to employ both.
Japanese Patent Laid-Open No. 7-326738

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a trench gate type semiconductor device that can easily solve the first to fourth problems at low cost. And

In order to achieve the above object, a trench gate type semiconductor device of the present invention includes a first region of a first conductivity type formed in a surface layer of a semiconductor substrate, and a trench that penetrates the first region and reaches the semiconductor substrate. A second region of the second conductivity type formed in the surface layer of the first region adjacent to the trench, a gate electrode layer formed in the trench through a gate insulating film, and above the trench A metal main electrode positioned and electrically connected to the second region; and a gate electrode wiring positioned above the trench and spaced apart from the metal main electrode and electrically connected to the gate electrode layer. In the trench gate type semiconductor device provided,
A region where the trench intersects is provided immediately below the gate electrode wiring, and the gate electrode layer and the gate electrode wiring are electrically connected in the intersecting region.

  The trenches are formed to have the same width in the semiconductor substrate.

As a manufacturing method,
A first region of a first conductivity type formed in a surface layer of a semiconductor substrate; a trench that penetrates the first region and reaches the semiconductor substrate; and is formed in a surface layer of the first region adjacent to the trench. In a method of manufacturing a trench gate type semiconductor device, comprising: a second region of the second conductivity type; and a gate electrode layer formed in the trench via a gate insulating film. Forming a film to form the trench; removing the insulating film; forming the gate insulating film on the semiconductor substrate surface and the trench inner surface;
A step of depositing a gate electrode layer on the surface of the semiconductor substrate and in the trench so as to fill the trench; and a planarization step of polishing the gate electrode layer using a gate insulating film on the surface of the semiconductor substrate as a stop layer. Suppose.

  Further, a step of diffusing and forming the second region is provided after the planarization step.

  In addition, an annealing process step in a reducing atmosphere is provided after the step of removing the insulating film.

A step of forming an interlayer insulating film on the surface of the semiconductor substrate after the step of forming the second region; a step of patterning the interlayer insulating film to form a contact hole exposing the gate electrode layer; Forming a gate electrode wiring on the surface of the interlayer insulating film including the contact hole;
Suppose that

  The gate electrode layer is made of polycrystalline silicon.

  And a step of removing a gate insulating film on the surface of the semiconductor substrate and a step of forming a screen oxide film on the surface of the semiconductor substrate and the surface of the polycrystalline silicon by thermal oxidation after the planarization step. And

    According to the present invention, since the gate electrode can be entirely polished by CMP in the method of manufacturing a trench gate type semiconductor device, the shape of the gate electrode can be easily controlled, and the number of processes can be reduced.

  Therefore, it is possible to provide a trench type semiconductor device with small variations in shape and electrical characteristics and a manufacturing method capable of mass production at low cost.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
1 and 2 are cross-sectional views showing the main part of a trench gate type semiconductor device according to Embodiment 1 of the present invention. FIG. 3 is a plan view of a mask when forming a trench, and FIG. 1 is a cross-sectional view of a semiconductor device formed at a position corresponding to AA ′ in FIG. 3 and corresponds to BB ′ in FIG. FIG. 2 is a cross-sectional view of the semiconductor device formed at the position where the contact is made. 4 to 10 and FIG. 12 are cross-sectional views showing the main part of the structure of the trench gate type semiconductor device shown in FIG. FIG. 11 is a plan view of a mask used for manufacturing the trench gate type semiconductor device shown in FIG. In the following description, an n-channel trench gate type MOSFET is exemplified, but the present invention relates to a method for processing a gate structure and a gate electrode, and the source structure and the drain structure are arbitrary. Therefore, it is applicable not only to MOSFETs but also to devices such as IGBTs having a trench gate structure on the surface and insulated gate thyristors. The trench pattern is exemplified as a stripe shape, but may be a donut-shaped pattern, a lattice-shaped pattern, or a circular pattern as long as all the trenches are connected.

  The configuration of FIG. 1 will be described below. The portions corresponding to the configuration of the prior art in FIG. Differences from the prior art of FIG. 14 will be described. Since the upper end of the gate electrode 8 is uniform on the same plane as the surface of the semiconductor substrate 1, the depth of the source region 9 formed using the gate electrode 8 as a mask can also be formed to a substantially uniform depth. Further, the interlayer insulating film 13 is not formed in the trench 4.

  As shown in FIG. 2, the gate electrode wiring 15 is formed above the region where the trench 4 is formed, and is connected to the gate electrode 8 through the contact hole 17. As described above, since the gate electrode wiring 15 is connected to the gate electrode 8 formed in the trench 4 through the contact hole 17, it is necessary to form a gate lead-out groove as described in the prior art. Absent.

  As shown in FIGS. 2 and 3, the contact hole 17 is formed in the contact formation portion 21 in which the trench 4 is formed in a lattice shape. Since the contact forming portion 21 is formed to be wider than the portion where the trench 4 is formed in a stripe shape, for example, when the width (diameter) of the contact hole 17 is the same as the width of the gate electrode 8, the contact hole A deviation of about 20% is allowed when forming 17. If the width of the gate electrode 8 and the diameter of the contact hole 17 are 0.8 μm, a deviation of ± 0.16 μm is allowed. When the gate electrode and the gate electrode wiring are connected in the region where the trench intersects in this way, the contact region can be widened without widening the trench.

  Hereinafter, a method for manufacturing the semiconductor device will be described with reference to FIGS.

First, a high-resistance n-type semiconductor substrate 1 having a low-resistance n ⁺ -type semiconductor region 2 on the back surface is prepared.

  Next, an oxide film 22 is formed on the surface of the semiconductor substrate 1 by thermal oxidation or CVD. The oxide film 22 needs to have a thickness of 2000 mm or more so that it can be recognized even after the target for performing mask alignment of the trench pattern of FIG. 3 is formed and the oxide film 3 is formed. Thereafter, in order to form the p-type well region 2 by ion implantation, the oxide film 22 is partially removed using a mask (not shown), and a screen (not shown) is formed on the surface of the semiconductor substrate 1 where the oxide film 22 is removed. An oxide film is formed by thermal oxidation, and boron is implanted and driven to diffuse the well region 2. An oxide film 3 is formed by performing thermal oxidation during diffusion. At this time, the thickness of the oxide film 3 is preferably about 4000 to 5000 mm. The thickness of the oxide film 22 is increased by the thermal oxidation during the diffusion (FIG. 4).

  After the well region 2 is formed, a window is opened in the oxide film 3 using a mask 19 shown in FIG. 3 having an opening 18 in which all the trench patterns are connected and a gate lead portion 20 connected to the gate electrode wiring 15 is formed. Do. The portion where the gate electrode wiring 15 is finally formed is formed in a lattice shape so that the width of the trench 4 is widened to make contact. In this case, the interval between the inner walls of the trench 4 must be less than twice the growth height of the gate electrode 8 filling the trench. Next, using the remaining oxide film 3 as a mask, a trench 4 that penetrates at least the well region 2 and reaches the semiconductor substrate 1 is formed by anisotropic etching.

  After the trench 4 is formed, a cleaning process is performed with a diluted solution of hydrofluoric acid to clean the inside of the trench 4. At this time, as shown in FIG. 5, the end portion of the oxide film 3 is etched back, and is slightly retracted from the opening end of the trench 4. The receding distance t is preferably in the range of 1/10 to 1/2 of the trench width w. Next, etching by CDE and sacrificial oxidation are performed as damage removal, and the inner wall of the trench 4 is thinned to improve the crystal quality.

  Thereafter, as shown in FIG. 6, all the oxide films are removed, and the well region 2 is exposed again on the inner wall of the trench.

  Next, a hydrogen annealing process is performed. If desired, sacrificial oxidation and sacrificial oxide film removal may be performed again.

  As a removal of damage, hydrogen annealing may be performed directly after trench cleaning without performing soft etching such as CDE. Further, sacrificial oxidation and sacrificial oxide film removal may be further performed as desired. By performing this hydrogen annealing treatment, the shapes of the opening and bottom of the trench 4 are rounded as shown in FIG.

  Subsequently, as shown in FIG. 7, a gate insulating film 7 is formed, and the trench 4 is filled with a gate electrode 8. Usually, n-type polycrystalline silicon is used as the gate electrode 8 and is preferably deposited by CVD. At this time, it is desirable that the gate electrode 8 completely fills the trench 4, and the lowest position in the surface region of the gate electrode 8 is higher than the highest position in the surface region of the gate insulating film 7.

  Next, as shown in FIG. 8, with the gate insulating film 7 as a stop layer, the gate electrode 8 is polished by CMP. In particular, in CMP, the polishing rate selection ratio between the gate electrode 8 and the gate insulating film 7 is as high as 100 or more and around 500, and mechanical polishing is performed, so even if there are wide portions such as where the trenches intersect, Unlike methods such as CDE, processing without local depression is possible. In this step, all the leading portions 81 located higher than the gate insulating film 7 as shown in FIGS. 14D and 14E disappear, but all the gate electrodes 8 are connected inside the trench 4. No problem.

  Next, as shown in FIG. 9, a region of the gate insulating film 7 that is not covered with the gate electrode 8 is removed by dry etching or wet etching. In this step, it is desirable to perform anisotropic dry etching so that the gate insulating film 7 is not over-etched and the gate electrode 8 is not lifted.

Next, a screen oxide film 23 is formed on the surface of the well region 2 in order to form the source region 9 by ion implantation. At this time, the surface of the gate electrode 8 is also oxidized, and the corner 24 of the gate electrode 8 is chamfered as shown in FIG. Since the corners of the gate electrode 8 are chamfered, the risk of breaking through the gate insulating film 7 can be reduced. Subsequently, ion implantation is performed using a mask 26 having an opening 25 shown in FIG. 11, and driving is performed as shown in FIG. 12 so that the n ⁺ source region 9 is sufficiently diffused and activated, and the n ⁺ source region 9 is activated. Form. Since the gate electrode 8 is etched back by CMP, the gate electrode 8 does not drop and has a uniform depth. Therefore, the n ⁺ source region caused by variations in the drop of the gate electrode 8 in the prior art. The variation in depth of 9 is eliminated.

Subsequently, after forming a p ⁺ -type contact region 10 as shown in FIG. 1, an interlayer insulating film 13 made of BPSG is formed and patterned. The patterning exposes the source region 9 and the contact region 10 as shown in FIG. 1, and further exposes the gate electrode 8 in the region formed by the lead portion 20 of FIG. 3 as shown in FIG. This is performed so as to form the holes 17. Thereafter, a metal material is evaporated and patterned to form the source electrode 12 and the gate electrode wiring 15. Next, the drain electrode 14 in contact with the n ⁺ semiconductor region 2 on the back surface is formed, and the trench MOSFET is completed.

  According to the present embodiment, since there is no portion where the gate electrode 8 is formed above the surface of the semiconductor substrate, the breakdown voltage is not lowered as in the prior art. Further, since no step is formed in the trench 4 in which the gate electrode 8 is formed, the depth of the source region 9 can be made substantially uniform because the gate electrode 8 can be etched and etched back by CMP. In addition, it is possible to avoid the formation of the interlayer insulating film 13 in the trench 4.

1 is a main part sectional view of a trench gate type semiconductor device according to a first exemplary embodiment of the present invention; 1 is a main part sectional view of a trench gate type semiconductor device according to a first exemplary embodiment of the present invention; It is a top view of the mask at the time of trench formation of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is a top view of the mask used for manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is principal part sectional drawing which shows the structure in the middle of manufacture of the trench gate type semiconductor device concerning Embodiment 1 of this invention. It is a top view which shows the structure in the middle of manufacture of the trench MOS type semiconductor device manufactured with the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the structure in the middle of manufacture of the trench MOS type semiconductor device manufactured by the manufacturing method of the conventional semiconductor device. It is an enlarged view of the round part 6 of FIG.14 (C).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Well region 3 Oxide film 4 Trench 7 Gate insulating film 8 Gate electrode 9 Source region 10 Contact region 13 Interlayer insulating film 15 Gate electrode wiring 17 Contact hole 20 Gate extraction part 20
21 Contact formation part

Claims (8)

A first region of a first conductivity type formed in a surface layer of a semiconductor substrate; a trench that penetrates the first region and reaches the semiconductor substrate; and is formed in a surface layer of the first region adjacent to the trench. A second region of the second conductivity type, a gate electrode layer formed in the trench via a gate insulating film, and a metal main electrode located above the trench and electrically connected to the second region And a trench gate type semiconductor device comprising a gate electrode wiring located above the trench, spaced apart from the metal main electrode and electrically connected to the gate electrode layer,
A trench gate type semiconductor device having a region where the trench intersects below the gate electrode wiring, and the gate electrode layer and the gate electrode wiring are electrically connected in the intersecting region. 2. The trench gate type semiconductor device according to claim 1, wherein the trenches are formed to have the same width in the semiconductor substrate. A first region of a first conductivity type formed in a surface layer of a semiconductor substrate; a trench that penetrates the first region and reaches the semiconductor substrate; and is formed in a surface layer of the first region adjacent to the trench. In a method of manufacturing a trench gate type semiconductor device, comprising: a second region of the second conductivity type; and a gate electrode layer formed in the trench via a gate insulating film.
Forming an insulating film on the surface layer of the semiconductor substrate to form the trench;
Removing the insulating film;
Forming the gate insulating film on the semiconductor substrate surface and the trench inner surface;
Depositing a gate electrode layer in the semiconductor substrate surface and in the trench so as to fill the trench;
A planarization step of polishing the gate electrode layer using the gate insulating film on the surface of the semiconductor substrate as a stop layer;
A method of manufacturing a trench gate type semiconductor device, comprising: 4. The method of manufacturing a trench gate type semiconductor device according to claim 3, further comprising a step of diffusing and forming the second region after the planarization step. 5. The method of manufacturing a trench gate type semiconductor device according to claim 3, further comprising an annealing treatment step in a reducing atmosphere after the step of removing the insulating film. After the step of forming the second region, a step of forming an interlayer insulating film on the surface of the semiconductor substrate, a step of patterning the interlayer insulating film to form a contact hole exposing the gate electrode layer, and the contact Forming a gate electrode wiring on the interlayer insulating film surface including the hole;
6. The method of manufacturing a trench gate type semiconductor device according to claim 4, further comprising: 7. The method of manufacturing a trench gate semiconductor device according to claim 3, wherein the gate electrode layer is made of polycrystalline silicon. After the planarization step, the method includes a step of removing a gate insulating film on the surface of the semiconductor substrate, and a step of forming a screen oxide film on the semiconductor substrate surface and the polycrystalline silicon surface by thermal oxidation. A method for manufacturing a trench gate type semiconductor device according to claim 7.

Images