JP2009224660A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the yield of a semiconductor element by reducing contact defects and leak defects at a place where a semiconductor and a conductor comes in contact with each other. <P>SOLUTION: An element structure is formed on a surface layer of an SOI substrate 22, a mask oxide film is formed on a surface thereof, and the opening width of a mask is varied to form a trench 31 for element isolation which reaches a buried insulating layer 24 and an active portion trench 35 which does not reach the buried insulating layer 24 at the same time. A first oxide film 32 is deposited by a CVD method on an inner circumferential surface of the trench 31 for element isolation, and the active portion trench 35 is buried with the first oxide film 32. The trench 31 for element isolation is buried with a polysilicon film 33. A portion of the polysilicon film 33 on a substrate surface is etched back to be removed. A BPSG film 36 is deposited to close an upper portion of the trench 31 for element isolation. A contact hole is formed at an interlayer insulating film 50 to bring metal wiring lines 53, 54 and 55 and the semiconductor into contact with each other through buried plugs 51, 52 and 56. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  FIG. 9 is a cross-sectional view showing a configuration of a conventional semiconductor device. As shown in FIG. 9, in a conventional high breakdown voltage lateral IGBT (Insulated Gate Bipolar Transistor) 1, a first trench 2 is formed in an element isolation region, and a second trench is formed in an element active region in which a drift current flows. A trench 3 is formed. The first trench 2 reaches a buried insulating layer 5 of an SOI (Silicon on Insulator) substrate 4. The second trench 3 does not reach the buried insulating layer 5 but has a depth up to the middle of the semiconductor active layer 6. Both the first trench 2 and the second trench 3 are filled with insulating films 7 and 8. According to this configuration, since the breakdown voltage of the IGBT is maintained in the vertical direction by the insulating film 8 between the collector region and the base region, the device pitch can be reduced.

  The semiconductor device shown in FIG. 9 is manufactured as follows. First, an SOI substrate 4 in which the thickness of the buried insulating layer 5 is 1 μm and the thickness of the semiconductor active layer 6 is 14 μm is prepared. A diffusion region, a selective oxide film, a gate insulating film, a gate electrode, and the like are formed on the surface of the semiconductor active layer 6. Thereafter, an oxide film is deposited on the surface of the substrate to a thickness of about 0.4 μm by a CVD (Chemical Vapor Deposition) method. An opening having a width of 1.2 μm is formed in the oxide film, and trench etching is performed using the opening as a mask to form the first trench 2. The width of the bottom of the first trench 2 is about 0.7 μm. A mask oxide film having a thickness of about 0.2 μm remains on the substrate surface.

  Next, an oxide film is filled in the first trench 2 by the CVD method. In order to completely fill the first trench 2 with the CVD oxide film, it is necessary to deposit the oxide film to a thickness of about 1.0 μm. Therefore, an oxide film having a total thickness of about 1.2 μm remains on the substrate surface. Next, an opening having a width of 0.8 μm is formed in the oxide film, and trench etching is performed using the opening as a mask to form the second trench 3. The depth of the second trench 3 is about 10 μm. Since the oxide film on the surface of the substrate is not etched by about 0.15 μm by the trench etching, an oxide film having a thickness of about 1.05 μm remains on the surface of the substrate. Further, the second trench 3 is filled with an oxide film by a CVD method. In order to completely fill the second trench 3 with the CVD oxide film, it is necessary to deposit the oxide film to a thickness of about 0.8 μm.

  Next, a BPSG (Boro-Phospho Silicate Glass) film is deposited on the substrate surface, and the surface is flattened by reflow. Then, a contact hole is formed in the CVD oxide film and BPSG film on the substrate surface by etching, a metal embedded plug 9 is formed in the contact hole by a CVD method, a metal wiring 10 is formed, and a passivation film (not shown) is formed. By doing so, the high breakdown voltage lateral IGBT 1 having the configuration shown in FIG. 9 is obtained.

  By the way, an insulating film is formed on the surface of the semiconductor substrate, a plurality of openings having different widths are provided in the insulating film, and the semiconductor substrate is etched to form a plurality of grooves having different depths according to the width of the opening. Further, a method for forming an insulating isolation region by embedding a dielectric in a plurality of grooves is known (for example, see Patent Document 1). Further, it is known that a shallow trench and a deep trench can be simultaneously formed by a single photolithography method and an etching method due to the microloading effect (see, for example, Patent Document 2). In addition, a method is known in which an insulating film is formed on the side wall of the trench reaching the buried insulating layer of the SOI substrate, and polysilicon is buried in the trench (see, for example, Patent Document 3). In addition, a lateral IGBT has been proposed in which a trench formed in an SOI substrate is filled with an insulating film to bend a drift region carrying a withstand voltage to increase an effective drift length (see, for example, Patent Document 4). .

JP-A-6-291178 ([Configuration] in [Summary]) JP 2004-241586 A (paragraph number [0009]) JP 2000-315736 A (paragraph numbers [0030] to [0032]) Japanese Patent Laying-Open No. 2006-5175 ([Solution] in [Summary])

  However, in the above-described conventional manufacturing method, the interlayer insulating film between the semiconductor region and the metal wiring fills the second trench by leaving the mask oxide film, the oxide film filling the first trench, and the second trench. It is composed of an oxide film and a BPSG film. Therefore, the interlayer insulating film is as thick as 2.5 to 3 μm, and the thickness variation of the interlayer insulating film is increased accordingly. Further, when the contact hole is opened, it is difficult to accurately detect the end point of etching because the area to be etched is small.

  For this reason, the contact hole may not be formed to a sufficient depth, and the semiconductor region may not be exposed. In this case, the embedded plug does not contact the semiconductor region, resulting in contact failure. Alternatively, the contact hole may be formed deeper than necessary and penetrate the shallow PN junction. In this case, the P-type region and the N-type region are short-circuited via the embedded plug, resulting in a leak failure. Thus, there is a problem that the yield is lowered due to contact failure or leak failure.

  As a method for avoiding this, it is conceivable to thin the interlayer insulating film by etch back or CMP (Chemical Mechanical Polishing). However, if the oxide film on the upper portion of the trench disappears due to variations in etching back or CMP, there is a problem in that a seam of the oxide film filling the trench called a seam appears and a defect occurs.

  In order to solve the above-described problems caused by the prior art, the present invention reduces a contact failure and a leak failure at a portion where a semiconductor and a conductor are in contact with each other, and can improve a device yield. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, a manufacturing method of a semiconductor device according to claim 1 includes a trench formation step of simultaneously forming a first trench and a second trench in a semiconductor active layer, and the first A second trench filling step of covering the sidewall and bottom of the trench with the first insulating film and filling the second trench with the first insulating film; and a groove remaining inside the first insulating film in the first trench A first trench burying step of filling the semiconductor film with a semiconductor film, an etching step of removing the semiconductor film deposited outside the first trench by etching, leaving the semiconductor film only in the first trench, and the first And a first trench covering step of covering the semiconductor film in the trench with a second insulating film.

  According to a second aspect of the present invention, in the semiconductor device manufacturing method according to the first aspect, in the trench forming step, the width of the second trench is made smaller than the width of the first trench, The second trench is formed shallower than the first trench.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the second aspect, wherein in the trench forming step, the first trench is provided as a buried insulating layer provided below the semiconductor active layer. The second trench is formed so as not to reach the buried insulating layer.

  According to a fourth aspect of the present invention, in the semiconductor device manufacturing method according to the second or third aspect, in the second trench embedding step, the first insulating film is completely embedded in the second trench. And the first trench is deposited to a thickness that does not fill the first trench.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the first to fourth aspects, wherein a gate insulating film is formed on the semiconductor active layer before the trench forming step. And a gate forming step.

  According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the first to fifth aspects, wherein an impurity diffusion region is formed in the semiconductor active layer before the trench forming step. And a diffusion region forming step.

  According to a seventh aspect of the present invention, in the semiconductor device manufacturing method according to the sixth aspect of the present invention, the first insulating film is deposited by a CVD method in the second trench filling step.

  According to the present invention, the first trench and the second trench are formed simultaneously, the first trench is filled with the semiconductor film via the insulating film, and the portion of the semiconductor film stacked on the substrate surface is removed. The interlayer insulating film becomes thin. Therefore, the variation in the thickness of the interlayer insulating film and the variation in etching when forming the contact hole are reduced, and a contact hole having a depth with no excess or deficiency can be formed. Moreover, the appearance of the seam can be avoided by closing the first trench with the second insulating film.

  According to the method for manufacturing a semiconductor device according to the present invention, it is possible to reduce contact failure and leakage failure at a portion where the semiconductor and the conductor are in contact with each other, thereby improving the yield of the element.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. As shown in FIG. 1, the high breakdown voltage lateral IGBT 21 according to the embodiment is formed on an SOI substrate 22. The SOI substrate 22 has a buried insulating layer 24 on a support substrate 23, and further has a semiconductor active layer (hereinafter simply referred to as an active layer) 25 thereon. The active layer 25 is divided by a first trench (hereinafter referred to as an element isolation trench) 31 constituting a trench isolation structure. The element isolation trench 31 reaches the buried insulating layer 24 through the selective oxide film 48 and the active layer 25. The element isolation trench 31 is filled with a semiconductor film such as a polysilicon film 33 via a first insulating film such as a first oxide film 32.

  A region surrounded by the trench isolation portion and the buried insulating layer 24 is an element formation region 34. A base region 41, a base contact region 42, and an emitter region 43 are provided in the emitter portion of the surface layer of the active layer 25 in the element formation region 34. A gate polysilicon electrode 45 is provided on the surface of the base region 41 between the emitter region 43 and the active layer 25 via a gate oxide film 44. In addition, a collector portion is provided at a position away from the emitter portion in the surface layer of the active layer 25. A buffer region 46 and a collector region 47 are provided in the collector portion.

  Between the emitter part and the collector part, there is a second trench (hereinafter referred to as an active part trench) 35 for bending the active layer 25 to increase the effective drift length. The active portion trench 35 penetrates the selective oxide film 49 and reaches the active layer 25 but does not reach the buried insulating layer 24. The active portion trench 35 is filled with the first oxide film 32. An interlayer insulating film 50 is provided on the gate polysilicon electrode 45. The interlayer insulating film 50 includes a remaining mask film (not shown) at the time of trench formation, the first oxide film 32 deposited thereon, and a second insulating film deposited thereon, for example, a BPSG film 36. It is composed of.

  The metal wiring 55 serving as the gate wiring (G) is electrically connected to the gate polysilicon electrode 45 through the embedded plug 56 penetrating the interlayer insulating film 50. The metal wiring 53 serving as the emitter wiring (E) is electrically connected to the emitter region 43 and the base region 41 through a buried plug 51 that penetrates the interlayer insulating film 50. The metal wiring 54 serving as the collector wiring (C) is electrically connected to the collector region 47 through the embedded plug 52 that penetrates the interlayer insulating film 50. The interlayer insulating film 50 and the metal wirings 53, 54, 55 are covered with a passivation film (not shown).

  2-7 is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning Embodiment. First, as shown in FIG. 2, an SOI substrate 22 having a buried insulating layer 24 having a thickness of 1 μm, for example, on a support substrate 23 and further having an active layer 25 having a thickness of 14 μm, for example, is prepared thereon. A base region 41, a base contact region 42, an emitter region 43, a buffer region 46, a collector region 47, selective oxide films 48 and 49, a gate oxide film 44 and a gate are formed on the surface layer of the active layer 25 of the SOI substrate 22 by a known method. An element structure such as a polysilicon electrode 45 is formed.

  Next, for example, a second oxide film 61 is deposited to a thickness of, for example, 0.4 μm on the substrate surface by CVD (Chemical Vapor Deposition). Further, a photoresist 62 is applied to the surface of the second oxide film 61, and a first opening 63 having a width of, for example, 2.5 μm is provided in the element isolation region by photolithography technique, and for example, 0 in the element active region. A resist mask having a second opening 64 having a width of 8 μm is formed.

  Next, as shown in FIG. 3, openings are formed in the second oxide film 61 and the selective oxide films 48 and 49 using the resist mask as a mask, and the active layer 25 is exposed. Then, after removing the resist mask, trench etching is performed using the second oxide film 61 as a mask to simultaneously form the element isolation trench 31 and the active portion trench 35. At that time, a trench having a depth corresponding to the opening width of the mask is formed. Therefore, the element isolation trench 31 having a wide opening width is deeper than the active portion trench 35 having a narrow opening width.

  According to the dimension example, in the second oxide film 61, the opening width for forming the element isolation trench 31 is 2.5 μm, and the opening width for forming the active portion trench 35 is 0.8 μm. . In this case, if the etching is performed so that the depth of the active portion trench 35 becomes 10 μm, for example, the depth of the element isolation trench 31 becomes 16 μm. However, this is a dimension when it is assumed that the element isolation trench 31 is formed in a semiconductor layer thicker than 16 μm. In the dimension example, since the thickness of the active layer 25 is 14 μm, the element isolation trench 31 reaches the buried insulating layer 24 through the active layer 25.

  Then, the buried insulating layer 24 is over-etched by a depth corresponding to the etching of the active layer 25 by 2 μm. By performing over-etching in this way, the element isolation trench 31 can surely reach the buried insulating layer 24 even if the active layer 25 has a thickness variation, so that an isolation structure having sufficient element isolation characteristics is obtained. Can be provided. Further, the active portion trench 35 having a sufficient depth can be provided in the element formation region 34.

  Next, the substrate is cleaned with dilute hydrofluoric acid to remove the polymer in the trench. Further, the inner wall of the trench is etched with an isotropic dry etcher, and etching damage generated on the inner wall of the trench during the trench etching is removed. In the case of the dimension example, by these processes, the opening width of the element isolation trench 31 is expanded to, for example, 2.7 μm, and the opening width of the active portion trench 35 is expanded to, for example, 1.0 μm.

  Next, as shown in FIG. 4, for example, a first oxide film 32 is deposited on the entire surface of the substrate by, for example, a low pressure CVD method. At that time, the active portion trench 35 is completely filled with the first oxide film 32, but the element isolation trench 31 is not completely filled with the first oxide film 32, and the side wall and the bottom thereof are covered. Further, a groove is left inside the element isolation trench 31.

  In the case of the dimension example, as the first oxide film 32, for example, if an HTO (High Temperature Oxide) film is deposited to a thickness of 1 μm, the active portion trench 35 is filled with the HTO film, and the upper portion thereof is completely HTO film. It will be in a state of being blocked by. On the other hand, in the element isolation trench 31, the HTO film is deposited on the bottom with a thickness of about 0.6 μm, and the HTO film is deposited on the trench side wall with a thickness of about 0.6 μm to 0.8 μm. . In FIG. 4, the second oxide film remaining on the substrate surface after the trench etching is integrated with the first oxide film 32 and is not clearly shown (the same applies to FIGS. 5 to 7).

  Next, as shown in FIG. 5, for example, a polysilicon film 33 is deposited on the entire surface of the substrate by, for example, a low pressure CVD method to completely fill the groove remaining inside the first oxide film 32 in the element isolation trench 31. In the case of the above dimension example, the width of the bottom of the groove remaining in the element isolation trench 31 is about 1.5 μm. Accordingly, if the polysilicon film 33 is deposited to a thickness of 1 μm, for example, the element isolation trench 31 is filled with the polysilicon film 33. At this time, the polysilicon film 33 is also deposited on the first oxide film 32 on the substrate surface.

  Next, as shown in FIG. 6, the portion of the polysilicon film 33 on the first oxide film 32 is removed by, for example, etch back by dry etching. At this time, the polysilicon film 33 is left in the element isolation trench 31.

  Next, as shown in FIG. 7, a BPSG film 36 is deposited to a thickness of 0.4 μm, for example, on the entire surface of the substrate by a known method. Then, reflow is performed to completely cover the upper part of the element isolation trench 31 with the BPSG film 36. In the case of the dimension example, the thickness of the interlayer insulating film 50 made up of the remaining mask film and the first oxide film 32 and the BPSG film 36 at the time of trench formation (not shown) is about 1.5 μm.

  Next, as shown in FIG. 1, a contact hole is formed in the interlayer insulating film 50 by a well-known method, and the contact hole is filled with buried plugs 51, 52, 56 of tungsten by, for example, a CVD method, and the metal wirings 53, 54, 55 is formed. Finally, a passivation film is formed on the entire surface of the substrate by a known method to complete the IGBT.

  FIG. 8 is a cross-sectional view of a main part for explaining the element isolation withstand voltage of the semiconductor device according to the embodiment, and is an enlarged view of the bottom of the element isolation trench. As shown in FIG. 8, the IGBT formed in the first region 71 (not shown in the drawing) and the IGBT formed in the second region 72 (not shown in the drawing) Isolation is performed by an element isolation region including an element isolation trench 31, a first oxide film 32, and a polysilicon film 33. The thickness of the portion of the first oxide film 32 in contact with the first region 71 or the second region 72 is about 0.6 μm near the bottom of the thinnest element isolation trench 31. Since the breakdown electric field of the first oxide film 32 is 8 MV / cm, the element isolation breakdown voltage is about 480 V, and a sufficient element isolation breakdown voltage is obtained.

  In the manufacturing method described above, the element isolation trench 31 and the active portion trench 35 are formed after forming the MOS gate structure of the gate oxide film 44 and the gate polysilicon electrode 45. The reason is as follows. This is because the gate oxide film is contaminated with heavy metals and there is no concern that the quality of the gate oxide film is deteriorated, and a high-quality gate oxide film can be formed. Therefore, if it is possible to prevent the gate oxide film from being contaminated by heavy metals, the trench may be formed first and then the gate structure may be formed.

  However, when the trench is formed first, the mask oxide film for forming the trench is formed on the entire surface of the substrate by the thermal oxidation method or the CVD method. Therefore, the mask oxide film is formed on the entire surface of the substrate before forming the MOS gate structure. It is necessary to remove by drain etching. When removing the mask oxide film, it is necessary to form a mask so that the oxide film and the polysilicon film in the trench are not removed, so that the number of processes increases as a whole.

  Also, the first oxide film 32 is deposited by the CVD method. The reason is that if a heat treatment is performed at a high temperature of 1000 ° C. or higher for a long time as in the thermal oxidation method, the diffusion region formed before that is formed. This is because the density profile may change. In the case where the first oxide film 32 is formed by the thermal oxidation method, the diffusion region may be formed in advance in consideration of the change in the concentration profile of the diffusion region due to the thermal oxidation.

  As described above, according to the embodiment, the interlayer insulating film 50 is thinned. For example, according to the above dimension example, the thickness of the interlayer insulating film 50 is about half that of the conventional structure. The variation in thickness is reduced. In addition, variations in etching when forming contact holes are reduced. Therefore, a contact hole having a depth with no excess or deficiency can be formed in the interlayer insulating film 50. As a result, it is possible to prevent the contact hole from being too shallow and causing a contact failure, or the contact hole from being too deep and causing a leakage failure, so that the yield of the device can be improved.

  In addition, since the BPSG film 36 blocks the upper portion of the element isolation trench 31, it is possible to avoid the appearance of seams due to the first oxide film 32 and the polysilicon film 33 in the element isolation trench 31. Further, since the element isolation trenches 31 and the active portion trenches 35 having different depths are formed simultaneously by changing the opening width, the trench forming process can be performed only once, and the manufacturing cost can be reduced.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the insulating film (insulating layer) is not limited to an oxide film, and may be another insulating film such as a nitride film. Further, the semiconductor is not limited to silicon but may be a compound semiconductor. Moreover, the dimension described in embodiment is an example, and this invention is not limited to those values. The present invention can also be applied to the manufacture of a high breakdown voltage lateral MOSFET (insulated gate field effect transistor) in which a region having the same conductivity type as that of the active layer 25 is formed instead of the collector region 47 of FIG.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a high breakdown voltage semiconductor device, and is particularly suitable for manufacturing a high breakdown voltage lateral IGBT and a high breakdown voltage lateral MOSFET.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the manufacturing stage of the semiconductor device concerning embodiment of this invention. It is principal part sectional drawing explaining the element isolation pressure | voltage resistance of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Semiconductor device 24 Embedded insulating layer 25 Semiconductor active layer 31 1st trench 32 1st insulating film 33 Semiconductor film 35 2nd trench 36 2nd insulating film

Claims (7)

A trench forming step of simultaneously forming the first trench and the second trench in the semiconductor active layer;
A second trench filling step of covering the sidewall and bottom of the first trench with a first insulating film and filling the second trench with the first insulating film;
A first trench filling step of filling a groove remaining inside the first insulating film in the first trench with a semiconductor film;
Removing the semiconductor film deposited outside the first trench by etching, leaving the semiconductor film only in the first trench;
A first trench covering step of covering the semiconductor film in the first trench with a second insulating film;
A method for manufacturing a semiconductor device, comprising:   The width of the second trench is made narrower than the width of the first trench, and the second trench is formed shallower than the first trench in the trench forming step. A method for manufacturing a semiconductor device.   In the trench formation step, the first trench is formed so as to reach a buried insulating layer provided under the semiconductor active layer, and the second trench is formed so as not to reach the buried insulating layer. The method of manufacturing a semiconductor device according to claim 2, wherein:   The said 2nd trench embedding process WHEREIN: The said 1st insulating film is deposited to the thickness which the said 2nd trench fills completely, and the said 1st trench does not fill. A method for manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 1, further comprising a gate forming step of forming a gate insulating film in the semiconductor active layer before the trench forming step.   6. The method of manufacturing a semiconductor device according to claim 1, further comprising a diffusion region forming step of forming an impurity diffusion region in the semiconductor active layer before the trench forming step. .   The method of manufacturing a semiconductor device according to claim 6, wherein in the second trench filling step, the first insulating film is deposited by a CVD method.

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