KR100744086B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
- Publication number
- KR100744086B1 KR100744086B1 KR1020050036263A KR20050036263A KR100744086B1 KR 100744086 B1 KR100744086 B1 KR 100744086B1 KR 1020050036263 A KR1020050036263 A KR 1020050036263A KR 20050036263 A KR20050036263 A KR 20050036263A KR 100744086 B1 KR100744086 B1 KR 100744086B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- forming
- groove
- recess
- sacrificial insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 3
- 229910010252 TiO3 Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- -1 ZrO3 Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 3
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 31
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 리세스-게이트 구조의 반도체소자 제조방법에 관한 것으로서, 특히 게이트전극의 일부를 기판에 매립하는 리세스-게이트 구조에서 혼형상의 돌출부가 형성된 홈을 가지는 리세스 공정 후에 단차피복성이 떨어지는 재질의 희생절연막을 전면에 도포하고, 전면식각으로 상기 돌출부를 노출시킨 후, 이를 제거하여 평탄한 바닥면을 가지는 리세스 홈을 형성하고, 후속공정을 진행하였으므로, 홈 바닥면의 돌출부에 의한 트랜지스터의 험프 현상이 방지되어 누설전류가 감소되고, Vt가 증가되며, 리플레쉬 특성이 향상되어 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a recess-gate structure. In particular, in a recess-gate structure in which a part of a gate electrode is embedded in a substrate, a stepped coating property is formed after a recess process having a groove having a mixed protrusion formed therein. Since a sacrificial insulating film made of a falling material was applied to the entire surface, and the protrusion was exposed by the entire surface etching, the recess was removed to form a recess groove having a flat bottom surface, and the subsequent process was performed. Humps can be prevented to reduce leakage current, increase Vt, and improve refresh characteristics, improving process yield and device operation reliability.
리세스, 희생절연막 Recess, sacrificial insulating film
Description
도 1a 내지 도 1e는 본 발명에 따른 반도체소자의 제조공정도.1A to 1E are manufacturing process diagrams of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명> <Explanation of symbols for the main parts of the drawings>
10 : 반도체기판 12 : 소자분리 산화막 10: semiconductor substrate 12: device isolation oxide film
14 : 홈 16 : 돌출부14 groove 16: protrusion
18 : 희생절연막 20 : 게이트절연막18: sacrificial insulating film 20: gate insulating film
22 : 다결정실리콘층 24 : W 실리사이드층22 polycrystalline silicon layer 24 W silicide layer
26 : 하드마스크층 28 : 스페이서 26: hard mask layer 28: spacer
본 발명은 게이트전극의 일부가 반도체기판에 매립되는 리세스-게이트 구조의 반도체소자의 제조방법에 관한 것으로서, 특히 리플레쉬 특성을 향상시키기 위한 리세스-게이트 구조 셀인 모스 전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 활성영역 에지 부분을 라운드지게 형성하여 소자의 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a recess-gate structure semiconductor device in which a part of a gate electrode is embedded in a semiconductor substrate, and in particular, a MOS field effect transistor, which is a recess-gate structure cell for improving refresh characteristics. The present invention relates to a method of fabricating a semiconductor device capable of improving the process yield and reliability of device operation by forming rounded edges of an active region of a conductor field effect transistor (hereinafter referred to as a MOS FET).
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다. The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
이러한 감광막 패턴의 분해능(R)은 감광막 자체의 재질이나 기판과의 접착력 등과도 밀접한 연관이 있으나, 일차적으로는 사용되는 축소노광장치의 광원 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture; NA, 개구수)에 반비례한다. The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 라인/스페이스 패턴의 경우 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 이보다 파장이 더 작은 원자외선(deep ultra violet; DUV), 예를들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하여야 한다. Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.
또한 축소노광장치와는 별도로 공정 상의 방법으로는 노광마스크(photo mask)로서 위상반전마스크(phase shift mask)를 사용하는 방법이나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법이나, 두층의 감광막 사이에 에스.오.지(spin on glass; SOG)등의 중간층을 개재시킨 삼층레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다. In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.
또한 소자가 고집적화되고, 디자인 룰이 감소함에 따라 소자의 신뢰성을 확보하기 위하여 캐패시터의 정전용량을 증대시키는 방법으로 고유전막과 극박막을 형성하기도 하는데 이 방법도 한계가 있어, 소자의 리플레쉬 특성을 향상시키는 방법이 고안되어지고 있으며, 게이트전극의 폭이 감소되고, 리플레쉬 특성 향상을 위하여 게이트전극의 일부 두께를 기판에 매립시키는 리세스-게이트 구조를 형성하고 있다. In addition, as the device is highly integrated and the design rule is reduced, the high-k dielectric and the ultra-thin film are formed by increasing the capacitance of the capacitor in order to secure the reliability of the device. A method of improving is being devised, and the width of the gate electrode is reduced, and a recess-gate structure is formed in which a part of the thickness of the gate electrode is embedded in the substrate in order to improve refresh characteristics.
도시되어 잇지는 않으나, 종래 기술에 따른 리세스-게이트 구조를 가지는 반도체소자의 제조방법을 살펴보면 다음과 같다. Although not shown, a method of manufacturing a semiconductor device having a recess-gate structure according to the related art is as follows.
먼저, Si 웨이퍼 반도체기판에서 소자분리 영역으로 예정되어 있는 부분에 얕은 트랜치 구조의 소자분리 산화막을 형성하고, 상기 반도체기판에서 게이트전극이 형성될 부분을 리세스 마스크를 사용하여 일정 깊이 식각하여 홈을 형성하나. 이때 소자분리 산화막은 식각되지 않는다. First, a shallow trench structured device isolation oxide film is formed on a portion of the Si wafer semiconductor substrate, which is intended as a device isolation region, and a portion of the semiconductor substrate where the gate electrode is to be formed is etched to a predetermined depth by using a recess mask. Form. At this time, the device isolation oxide film is not etched.
그다음 상기 반도체기판 상에 게이트절연막을 형성하고, 상기 게이트 절연막상에 게이트전극을 형성한다. 여기서 상기 홈에 의해 활성영역에서의 게이트전극의 일부 두께가 반도체기판의 홈에 묻히게 된다. Then, a gate insulating film is formed on the semiconductor substrate, and a gate electrode is formed on the gate insulating film. Here, a part of the thickness of the gate electrode in the active region is buried in the groove of the semiconductor substrate by the groove.
상기와 같은 종래 기술에 따른 리세스-게이트 구조를 가지는 반도체소자의 제조방법은 리세스-게이트 구조에 의해 리플레쉬 특성은 향상되나, 리세스된 활성 영역의 에지 부분에 혼형상의 돌출부가 형성되며, 이 부분으로 인하여 게이트절연막의 특성이 열화되어 게이트전극의 누설전류가 증가되고, 트랜지스터에 험프 현상이 발생하여 Vt를 감소시키고, 리플레쉬 타임을 감소시켜 공정 수율 및 소자 동작의 신뢰성을 저하시키는 등의 문제점이 있다. In the method of manufacturing a semiconductor device having a recess-gate structure according to the related art, a refresh characteristic is improved by the recess-gate structure, but a hybrid protrusion is formed at an edge portion of the recessed active region. This deteriorates the characteristics of the gate insulating film, increasing the leakage current of the gate electrode, causing a hump phenomenon in the transistor, reducing Vt, and reducing the refresh time, thereby lowering process yield and reliability of device operation. There is a problem.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 게이트전극의 일부를 기판에 매립시키는 리세스-게이트 구조에서 활성영역 에지부분에서의 돌출부 형성을 방지할 수 있는 반도체소자의 제조방법을 제공함에 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to manufacture a semiconductor device capable of preventing the formation of protrusions at the edges of active regions in a recess-gate structure in which part of a gate electrode is embedded in a substrate. In providing a method.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은, Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 활성영역을 정의하는 소자분리 산화막을 형성하는 공정과, Forming a device isolation oxide film defining an active region on the semiconductor substrate;
상기 반도체기판의 활성영역에서 게이트전극과 중첩되는 부분에 리세스 홈을 형성하되, 홈의 바닥면에 돌출부가 형성되는 공정과, Forming a recess groove in a portion overlapping with the gate electrode in the active region of the semiconductor substrate, and forming a protrusion on the bottom surface of the groove;
상기 구조의 전표면에 희생절연막을 형성하는 공정과, Forming a sacrificial insulating film on the entire surface of the structure;
상기 희생절연막을 전면식각하여 상기 돌출부를 노출시키는 공정과, Exposing the protrusion by etching the sacrificial insulating layer on the entire surface;
상기 돌출부를 제거하여 평탄한 바닥면을 가지는 홈을 형성하는 공정과, Removing the protrusion to form a groove having a flat bottom surface;
상기 희생절연막을 제거하는 공정과, Removing the sacrificial insulating film;
상기 구조의 전표면에 게이트절연막을 형성하는 공정을 구비함에 있다. A process of forming a gate insulating film on the entire surface of the structure is provided.
또한 본 발명의 다른 특징은, 상기 리세스 홈 형성공정은 염소 베이스로 실시하고, 상기 희생절연막은 1 내지 1000Å 두께로 형성하되, 상기 반도체기판과 소자분리 산화막의 상부는 두껍게 도포되고, 홈의 측벽에는 얇게 증착되며, 상기 희생절연막은 단차피복성이 떨어지는 플라즈마유도 화학기상증착 방법의 산화막, USG 또는 ECR 산화막으로 형성하고, 상기 플라즈마 유도 화학기상증착 산화막은 100 내지 700℃ 에서, 0.1mtorr 내지 100torr 압력에서, Ar, N2, O2, Ne, N2O 또는 H2O2 등의 혼합가스 분위기에서 형성하며, 상기 희생절연막 전면 식각공정은 불소 베이스의 건식식각이며, 상기 노출되어 있는 실리콘 돌출부의 제거 공정은 염소 베이스 가스로 식각하고, 상기 희생절연막 제거 공정은 액체 케미컬을 이용한 습식식각 방법으로 제거하되, 상기 액체 케미컬은 불소계열 케미컬을 사용하여, 케미컬 온도 25 내지 100℃ 에서 식각하며, 상기 게이트절연막은, 화학기상증착이나 원자층 증착 또는 물리기상증착 방법으로 형성하되, SiO2, Si3N4, Al2O3, AlHfSiOx, HfO3, SrTiO3, ZrO3, La2O3 또는 (Ba,Sr)TiO3 재질로 형성되고, 상기 게이트절연막 형성 후, 상기 홈을 W, WN, Pt, Ru, Ir, TiN, Ti, Co, Ru 또는 Rb 재질로 메우는 공정을 구비하는 것을 특징으로 한다. In another aspect of the present invention, the recess groove forming process is performed on a chlorine base, and the sacrificial insulating layer is formed to a thickness of 1 to 1000 Å, and the upper portion of the semiconductor substrate and the device isolation oxide layer is thickly coated, and the sidewalls of the groove are formed. Is deposited thinly, the sacrificial insulating film is formed of an oxide film, USG or ECR oxide film of the plasma-induced chemical vapor deposition method is less stepped coating, the plasma-induced chemical vapor deposition oxide film is 0.1mtorr to 100torr pressure at 100 ~ 700 ℃ In a mixed gas atmosphere such as Ar, N2, O2, Ne, N2O, or H2O2, wherein the entire etching process of the sacrificial insulating film is a dry etching of fluorine-based, and the removing process of the exposed silicon protrusion is a chlorine base gas. Etching and removing the sacrificial insulating film is removed by a wet etching method using a liquid chemical, the liquid chemical Etching is performed at a chemical temperature of 25 to 100 ° C. using a fluorine-based chemical, and the gate insulating film is formed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. However, SiO2, Si3N4, Al2O3, AlHfSiOx, HfO3, SrTiO3, It is formed of ZrO3, La2O3 or (Ba, Sr) TiO3 material, and after forming the gate insulating film, the step of filling the groove with W, WN, Pt, Ru, Ir, TiN, Ti, Co, Ru or Rb material It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 도 1e는 본 발명에 따른 반도체소자 제조 공정도이다. 1A is a process diagram of manufacturing a semiconductor device according to the present invention.
먼저, Si 웨이퍼 반도체기판(10)상에 얕은 트랜치 공정을 진행하여 활성영역을 정의하는 소자분리 산화막(12)을 형성하고, 상기 반도체기판(10) 활성영역에서 게이트전극과 중첩되는 부분에 리세스 마스크를 이용한 사진식각 공정으로 일정 깊 이 식각하여 리세스 홈(14)을 형성한다. 여기서 상기 홈(14) 형성을 위한 식각 공정은 실리콘과 산화막간의 식각선택비를 고려하여 염소 베이스로 실시하며, 이때 상기 리세스된 활성영역 바닥 에지 부분에 혼형상의 돌출부(16)가 형성된다. (도 1a 참조). First, a shallow trench process is performed on the Si
그다음 단차피복성이 떨어지는 피복방법, 예를들어 플라즈마유도 화학기상증착 방법의 산화막이나, USG, ECR 산화막등으로된 희생절연막(18)을 1 내지 1000Å 정도 두께로 전면에 도포하면, 반도체기판(10)과 소자분리 산화막(12)의 상부는 두껍게 도포되고, 홈(14)의 측벽에는 얇게 증착된다. 여기서 상기 플라즈마 유도 화학기상증착 산화막 형성은 100 내지 700℃ 정도의 온도에서, 0.1mtorr 내지 100torr 압력에서, Ar, N2, O2, Ne, N2O 또는 H2O2 등의 혼합가스 분위기에서 실시한다. (도 1b 참조). Then, when the sacrificial
그후, 상기 희생절연막(18)을 건식식각 방법으로 전면 식각하여 상기 돌출부(16)를 노출시킨다. 이때 상기 식각 공정은 불소 베이스로 실시한다. (도 1c 참조). Thereafter, the
그다음 상기 노출되어 있는 실리콘 돌출부(16)를 염소 베이스 가스로 식각하여 평탄화시킨 후, 남아 있는 희생절연막(18)을 액체 케미컬을 이용한 습식식각 방법으로 제거하여 평탄화된 홈(14)을 얻는다. 여기서 상기 액체 케미컬은 HF, NH3F4 등의 불소계열 케미컬을 사용하며, 케미컬의 온도는 25 내지 100℃에서 식각을 실시한다. (도 1d 참조). Then, the exposed
그후, 상기 구조의 전표면에 게이트절연막(20)을 형성하되, 화학기상증착이 나 원자층 증착 또는 물리기상증착 등으로 방법으로, SiO2, Si3N4, Al2O3, AlHfSiOx, HfO3, SrTiO3, ZrO3, La2O3 또는 (Ba,Sr)TiO3 등의 재질로 형성한다. Thereafter, the
그다음 상기 구조의 전표면에 게이트전극이 되는 다결정실리콘층(22)과 W 실리사이드층(24) 및 질화막 재질의 하드마스크층(26)을 순차적으로 형성하고, 게이트 패턴닝 마스크를 사용하는 사진식각 방법으로 패턴닝하여 하드마스크층(26) 패턴과 중첩된 W 실리사이드층(24) 및 다결정실리콘층(22) 패턴으로된 게이트전극을 형성하고, 상기 패턴들의 측벽에 스페이서(28)를 형성한다. (도 1e 참조). Next, a photolithography method using a gate patterning mask is formed by sequentially forming a
본 발명의 다른 실시예로서, 게이트전극의 저항을 더욱 감소시키기 위하여 상기 게이트절연막을 형성한 후, 상기 홈을 금속재질, 예를들어 W, WN, Pt, Ru, Ir, TiN, Ti, Co, Ru 또는 Rb 등으로 메우고 후속 게이트전극 형성 공정을 진행할 수도 있다. In another embodiment of the present invention, after the gate insulating film is formed to further reduce the resistance of the gate electrode, the groove is formed of a metal material, for example, W, WN, Pt, Ru, Ir, TiN, Ti, Co, It may be filled with Ru or Rb, and the subsequent gate electrode forming process may be performed.
이상에서 설명한 바와 같이, 리세스-게이트 구조를 가지는 본 발명에 따른 반도체소자의 제조방법은 게이트전극의 일부를 기판에 매립하는 리세스-게이트 구조에서 혼형상의 돌출부가 형성된 홈을 가지는 리세스 공정 후에 단차피복성이 떨어지는 재질의 희생절연막을 전면에 도포하고, 전면식각으로 상기 돌출부를 노출시킨 후, 이를 제거하여 평탄한 바닥면을 가지는 리세스 홈을 형성하고, 후속공정을 진행하였으므로, 홈 바닥면의 돌출부에 의한 트랜지스터의 험프 현상이 방지되어 누설전류가 감소되고, Vt가 증가되며, 리플레쉬 특성이 향상되어 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, the method of manufacturing a semiconductor device according to the present invention having a recess-gate structure includes a recess process having grooves in which a hybrid protrusion is formed in a recess-gate structure in which a part of the gate electrode is embedded in a substrate. Later, a sacrificial insulating film of a material having poor step coverage was applied to the entire surface, and the protrusion was exposed by front etching, and then the recess was removed to form a recessed groove having a flat bottom surface. The hump phenomenon of the transistors due to the protruding portion of the transistor is prevented to reduce the leakage current, increase the Vt, and improve the refresh characteristics, thereby improving the process yield and the reliability of device operation.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050036263A KR100744086B1 (en) | 2005-04-29 | 2005-04-29 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050036263A KR100744086B1 (en) | 2005-04-29 | 2005-04-29 | Manufacturing method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20060114228A KR20060114228A (en) | 2006-11-06 |
| KR100744086B1 true KR100744086B1 (en) | 2007-08-01 |
Family
ID=37652030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020050036263A KR100744086B1 (en) | 2005-04-29 | 2005-04-29 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100744086B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130136063A (en) | 2012-06-04 | 2013-12-12 | 삼성디스플레이 주식회사 | Thin film transistor, thin film transistor array panel including the same and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990002332A (en) * | 1997-06-19 | 1999-01-15 | 윤종용 | Manufacturing Method of Semiconductor Device |
| KR20030003341A (en) * | 2001-06-30 | 2003-01-10 | 주식회사 하이닉스반도체 | Method of fabricating transistor using trench gate |
| JP2005093773A (en) | 2003-09-18 | 2005-04-07 | Fuji Electric Device Technology Co Ltd | Trench gate type semiconductor device and its manufacturing method |
-
2005
- 2005-04-29 KR KR1020050036263A patent/KR100744086B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990002332A (en) * | 1997-06-19 | 1999-01-15 | 윤종용 | Manufacturing Method of Semiconductor Device |
| KR20030003341A (en) * | 2001-06-30 | 2003-01-10 | 주식회사 하이닉스반도체 | Method of fabricating transistor using trench gate |
| JP2005093773A (en) | 2003-09-18 | 2005-04-07 | Fuji Electric Device Technology Co Ltd | Trench gate type semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060114228A (en) | 2006-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7354847B2 (en) | Method of trimming technology | |
| KR101004691B1 (en) | Method for forming micropattern in semiconductor device | |
| KR100965775B1 (en) | Method for forming micropattern in semiconductor device | |
| US7442648B2 (en) | Method for fabricating semiconductor device using tungsten as sacrificial hard mask | |
| US6528418B1 (en) | Manufacturing method for semiconductor device | |
| US6432816B2 (en) | Method for fabricating semiconductor device | |
| KR100726148B1 (en) | Manufacturing method for semiconductor device | |
| JP2001036044A (en) | Manufacture of capacitor of semiconductor device | |
| KR100465596B1 (en) | A manufacturing method for semiconductor device | |
| US20110248385A1 (en) | Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device | |
| CN109494149B (en) | Method for manufacturing semiconductor structure | |
| KR100527577B1 (en) | Fabricating method for semiconductor device | |
| KR100744086B1 (en) | Manufacturing method for semiconductor device | |
| JP4283017B2 (en) | Manufacturing method of semiconductor device | |
| US7300883B2 (en) | Method for patterning sub-lithographic features in semiconductor manufacturing | |
| KR20070113604A (en) | Method for forming micro pattern of semiconductor device | |
| KR100557581B1 (en) | Manufacturing method for semicondutor device | |
| US8524608B1 (en) | Method for fabricating a patterned structure of a semiconductor device | |
| KR100346449B1 (en) | Manufacturing method for semiconductor device | |
| KR100944344B1 (en) | Manufacturing method for semiconductor device | |
| KR100955184B1 (en) | Manufacturing method for semiconductor device | |
| KR100565753B1 (en) | Method for forming gate of semi-conductor device | |
| KR100527531B1 (en) | Manufacturing method for semiconductor device | |
| KR20060114447A (en) | Manufacturing method for semiconductor device | |
| KR20010057490A (en) | Manufacturing method for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100624 Year of fee payment: 4 |
|
| LAPS | Lapse due to unpaid annual fee |