JPH07249770A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To obtain a vertical MOSFET in which fluctuation of threshold voltage is suppressed by composing a gate insulating film of a heat treated CVD insulating film and a thermal oxide film thereby reducing the charge being charged up at the gate insulating film. CONSTITUTION:A drain region 11 is provided on the main surface of a semiconductor substrate 10 and a base region 12 is provided on the drain region 11, and then a source region 13 is provided on the surface of the base region. A gate insulating film 20 is then deposited on the inner wall face of a trench, and its periphery, penetrating the base region from the surface of the source region and reaching the drain region. A gate electrode G is then provided on the gate insulating film 20 composed of a thermal oxidation film 21 formed heat treating the surface of the semiconductor substrate 10 in oxidative atmosphere, and an annealed CVD insulating film 22 on the thermal oxidation film 21. Since the gate insulating film has stabilized electrical and mechanical characteristics, charge-up is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench gate structure having a U-shaped cross section for a semiconductor device having a vertical insulated gate field effect transistor.

[0002]

2. Description of the Related Art Insulated gate field effect transistors (hereinafter referred to as MOSFETs) have been reduced in on-state resistance due to advances in fine processing technology. Especially, low breakdown voltage MOS
The low on-resistance of FETs is remarkable, and at present, further progressing from the diffusion self-alignment type of the planar structure, which is seen to be the limit to the size reduction of the unit cell due to the limitation of the photoresist,
Attention has been paid to a vertical MOSFET having a trench structure that can further reduce the cell size. This vertical MOSFE
T has a small cell size because a channel region is formed on the side surface of the trench by forming a source region and a trench on the first main surface of the semiconductor substrate and a drain region on the second main surface. As a result, the on-resistance can be reduced. Referring to FIG. 10, a conventional vertical MOSF
Explain ET. The figure is a partial cross-sectional view showing a vertical MOSFET of a semiconductor device including a MOS integrated circuit. The plurality of trenches formed in the semiconductor substrate are arranged in a matrix on the surface thereof at intervals of 3 μm, for example. N ⁺
A low impurity concentration N-type first semiconductor layer 11 used for a drain region on the first main surface of the silicon semiconductor substrate 10.
Are formed by epitaxial growth. Then, a P-type second semiconductor layer 12 used for a channel region is formed on the first semiconductor layer 11 by impurity diffusion.

This semiconductor substrate and the first and second semiconductor layers form an epitaxial wafer. The trenches 14 arranged in a matrix form the second semiconductor layer 12
Is formed from the surface to the inside of the first semiconductor layer 11, the width thereof is, for example, 1 μm, and the depth thereof is, for example, 4 μm. The source region 13 is the second semiconductor layer 12
Is formed in the surface region of each of the trenches 14 and is arranged along both sides of each trench 14. The source region 13 is formed in the trench 14
Are divided into a large number of unit cells having a substantially rectangular plane pattern, and are regularly arranged in a matrix. The surface of the second semiconductor layer 12 is covered with the composite gate insulating film 15 which is also formed inside the trench 14. The gate electrode G is made of, for example, polysilicon doped with impurities, is buried inside the trench 14, and is formed on the composite gate insulating film 15. The gate electrodes in the adjacent trenches 14 are continuously formed. The lowermost first insulating film 151 of the composite gate insulating film 15 is composed of a silicon oxide film (SiO ₂ film) formed by thermal oxidation. On top of this, a silicon nitride film (Si ₃ N
₄ films) are formed by CVD (Cemical Vapor Deposition). Further, a third insulating film 153 is formed on the second insulating film 152. This insulating film is made of a SiO ₂ film, and is CVD like the second insulating film.
It is formed by the method.

The second semiconductor layer 1 on the gate electrode G, on the exposed surface of the source region 13 and in the channel formation region.
2 so as to cover the exposed surface of SiO ₂ , for example, SiO ₂
An insulating film 17 made of a film or the like is formed. A gate wiring 18 electrically connected to the gate electrode G through the contact hole of the insulating film 17 is formed. Similarly, a source electrode S made of a metal such as Al that is in contact with the source region 13 through the contact hole of the insulating film 17 is formed. The source electrode S commonly contacts the surface of the second semiconductor layer 12 together with the source region 13. As a result, the substrate region and the source region are short-circuited to each other, and the influence of the NPN transistor parasitic on the drain region, the substrate region, and the source region is reduced. A drain electrode D made of a metal such as Al electrically connected to the drain region of the first semiconductor layer 11.
Are formed on the back surface of the semiconductor substrate 10, that is, on the second main surface. The source electrode S and the drain electrode D are integrally provided for each cell, and the gate electrode G of each cell is commonly connected by the gate wiring 18, so that the cells are connected in parallel.

In the N-channel vertical MOSFET, the source electrode S is grounded and a positive voltage is applied to the drain electrode D and the gate electrode G. When the gate voltage is increased during such a forward bias, the channel region on the side surface of the trench 14 facing the gate electrode G of the second semiconductor layer 12 is inverted from P type to N type to become an inversion layer, and the source is formed. Electrons flow from the region 13 to the first semiconductor layer 11 just below the inversion layer.

[0006]

As described above, the gate insulating film 15 of the conventional vertical MOSFET has the trench 14
The thermal oxide film (Si
An O ₂ film 151, a nitride film (Si ₃ N ₄ film) 152, and an oxide film (SiO ₂ film) 153 are laminated to form a composite insulating film (see FIG. 10). Generally, such a three-layer composite insulating film is referred to as an ONO film by taking the symbols of an oxide film and a nitride film, respectively. This oxide film 153 is shown in FIG.
0 when growing by CVD and the first insulating film 15
Similar to 1, it can be formed by thermal oxidation. The gate insulating film 15 is formed not only on the inner wall surface of the trench 14 but also around the trench opening. FIG. 11 is an enlarged view of a region R centered on this portion, particularly the trench 14. As shown in this figure, the thermal oxide film 151 on the shoulder portion is thinner than the other portions. Therefore, when the gate insulating film is composed of only the thermal oxide film, the gate breakdown voltage is deteriorated due to the thin portion.
As a result, a silicon nitride film (S) is usually formed on the thermal oxide film 151 by CVD, which is a relatively uniform method.
i ₃ N ₄ film) 152 is formed. However, in the nitride film formed by the CVD method, pinholes are often formed on the surface of the film, so that the apparent dielectric constant is changed to deteriorate the electrical characteristics or reduce the mechanical strength.

In order to correct this pinhole, for example,
Re-oxidation is performed to form a silicon oxide film 153.
In this silicon oxide film 153, the crystal grains in at least the surface region forming the nitride film 152 are partially fused by the heat at the time of formation, and the pinholes disappear. by the way,
The cause of thinning of the thermal oxide film on the shoulder portion of the trench can be determined by the mechanism of oxide formation shown in FIG. When the silicon semiconductor surface of the second semiconductor layer 12 is heated in an oxidizing atmosphere, oxygen atoms penetrate into the inside of the semiconductor surface and silicon oxide is formed on the surface (FIG. 12).
(A)). At this time, as the heating progresses, the silicon oxide layer enters the inside of the semiconductor layer 12, but the shoulder portion does not proceed with the oxidation and the cross-sectional shape of the shoulder portion gradually becomes sharp (FIG. 12B). Therefore, in order to make the thickness of this portion sufficient, other portions must be made thicker. If the insulating film in the gate channel becomes too thick,
It cannot be made too thick because low voltage driving is not possible. As described above, the vertical MOSFET currently uses a composite film such as an ONO film as a gate insulating film, but when a current flows through such a composite insulating film having a different dielectric constant, each of the composite films is It is known that charges are charged up at the interface so that current balance in the insulating film is established. This means that charges are stored in the composite gate insulating film, and the threshold voltage Vth of the MOSFET changes due to the leak current in the gate insulating film. The fluctuation of the threshold voltage Vth is a serious problem in terms of characteristics and reliability. The present invention has been made under such circumstances, and the vertical M in which the charge charged up in the gate insulating film is reduced and the fluctuation of the threshold voltage Vth is suppressed.
An object is to provide a semiconductor device having an OSFET and a method for manufacturing the same.

[0008]

The semiconductor device of the present invention comprises:
A first conductivity type semiconductor substrate, a first conductivity type first semiconductor layer formed on the first main surface of the semiconductor substrate and used as a drain region, and formed on the first semiconductor layer. A second conductive type second semiconductor layer used as a base region, a first conductive type impurity diffusion region selectively formed in a surface region of the second semiconductor layer and used as a source region, The impurity diffusion region and the second semiconductor layer are penetrated from the surface of the impurity diffusion region,
A gate insulating film formed on the inner wall surface of the trench formed so that its bottom surface reaches the semiconductor layer and on the impurity diffusion region around the trench, and formed on the gate insulating film, and A gate electrode formed in and around the trench, a source electrode formed on the second semiconductor layer and electrically connected to at least the source region, and on a second main surface of the semiconductor substrate. And a drain electrode formed, the gate insulating film,
A thermal oxide film formed by heat treating the surface of the second semiconductor layer including the inside of the trench in an oxidizing atmosphere, and a heat treated CVD insulating film formed on the thermal oxide film. There is. A silicon nitride film or a silicon oxide film may be used as the CVD insulating film.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first conductive type first semiconductor layer used as a drain region on a first main surface of a semiconductor substrate, and the first step.
Forming a second conductive type second semiconductor layer used as a base region on the semiconductor layer, and forming a first conductive type impurity diffusion region used as a source region in the surface region of the second semiconductor layer. Selectively forming; forming a trench from the surface of the impurity diffusion region, penetrating the impurity diffusion region and the second semiconductor layer and reaching the bottom in the first semiconductor layer; A thermal oxide film as a first insulating film by heat treatment in an oxidizing atmosphere on the inner wall surface of the first insulating film and on the impurity diffusion region around the trench, and a second insulating film on the first insulating film. Forming a CVD insulating film which is an insulating film, forming a thermal oxide film which is a third insulating film on the second insulating film by heat treatment in an oxidizing atmosphere, and the third insulating film Membrane first A step of removing from the top of the insulating film,
Forming a gate electrode in and around the trench on the second insulating film; and forming a source electrode electrically connected to at least the source region on the second semiconductor layer. And a step of forming a drain electrode on the second main surface of the semiconductor substrate, and a gate insulating film is constituted by the first and second insulating films, and the second insulating film is the first insulating film. The first feature is that annealing is performed by the heat treatment in the step of manufacturing the insulating film of No. 3.

Also, a step of forming a first semiconductor layer of a first conductivity type used as a drain region on the first main surface of the semiconductor substrate, and a step of forming a first region used on the first semiconductor layer as a base region. Forming a second conductive type second semiconductor layer; selectively forming a first conductive type impurity diffusion region used as a source region in a surface region of the second semiconductor layer; The impurity diffusion region and the second semiconductor layer are penetrated from the surface of the region,
Forming a trench whose bottom reaches in the semiconductor layer, and forming a thermal oxide film as a first insulating film on the inner wall surface including the bottom of the trench and on the impurity diffusion region around the trench in an oxidizing atmosphere. Forming by a heat treatment inside, forming a CVD insulating film which is a second insulating film on the first insulating film, and forming a third insulating film on the second insulating film. Forming a CVD oxide film, removing the third insulating film from the second insulating film, and forming a gate electrode in the trench and around the trench on the second insulating film. And forming a source electrode electrically connected to at least the source region on the second semiconductor layer, and forming a drain electrode on the second main surface of the semiconductor substrate. , The first and second And the gate insulating film and the insulating film, the second insulating film, to be annealed by heat treatment in the step of producing the third insulating film second
It is a feature of.

[0011]

Since the gate insulating film is composed of the heat-treated CVD insulating film and the thermal oxide film, the electrical and mechanical characteristics are stable and the accumulated charge is less than before. Further, since the CVD insulating film is heat-treated by growing an oxide film on the surface of the CVD insulating film, the CVD insulating film is uniformly annealed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment of the present invention will be described with reference to FIGS. 1 is a plan view of a semiconductor substrate in which a wiring portion on the surface is omitted, FIG. 2 is a plan view showing a wiring portion on the semiconductor substrate, and FIG. FIG. 3 is a cross-sectional view including a wiring portion shown in FIG. 2. The figure shows a vertical MOSFET of a semiconductor device having a MOS integrated circuit. The plurality of trenches 14 provided in the semiconductor substrate 10 in which the epitaxial semiconductor layers 11 and 12 are formed on the first main surface are arranged in a matrix on the surface thereof, for example, at intervals of about 3 μm. N ⁺ silicon semiconductor substrate 1
An N-type first semiconductor layer 11 having a low impurity concentration and used for the drain region is formed on the first main surface of 0 by epitaxial growth. Then, a P-type second semiconductor layer 12 used for a channel region is formed on the first semiconductor layer 11 by impurity diffusion. In this embodiment, the second semiconductor layer 12 is formed by partially performing impurity diffusion on the first semiconductor layer 11,
By forming the second epitaxial growth layer on the first semiconductor layer 11, this can be used as the second semiconductor layer.

Trenches 14 arranged in a matrix
From the surface of the second semiconductor layer 12 to the first semiconductor layer 11
Is formed to the inside of, and its width is, for example, about 1
μm, and the depth thereof is, for example, about 4 μm. The source region 13 is formed in the surface region of the second semiconductor layer 12,
It is arranged along the periphery of each trench 14. The source region 13 is divided by the trench 14 into a large number of unit cells having a substantially rectangular plane pattern.
The unit cells are regularly arranged in a matrix.
The surface of the second semiconductor layer 12 is covered with the composite gate insulating film 20 which is also formed inside the trench 14. The gate electrode G is made of, for example, polysilicon doped with impurities, and a part thereof is embedded in the trench 14 and a part thereof is formed on the composite gate insulating film 20 around the opening of the trench 14. Composite gate insulating film 20
The lowermost first insulating film 21 is composed of a silicon oxide film (SiO ₂ film) formed by thermal oxidation.
On top of this, a silicon nitride film (Si
₃ N ₄ film) is formed by CVD.

The second semiconductor layer 1 on the gate electrode G, on the exposed surface of the source region 13 and in the channel formation region.
2 to cover over the exposed surface, for example PSG
(Phosphorus silicate glass) thickness of about 600
An insulating film (interlayer insulating film) 17 having a thickness of nm is formed. Through the contact hole of the insulating film 17, the gate electrode G
A metal gate wiring 18 made of Al or the like electrically connected to the gate wiring 18 is formed (FIG. 2). Similarly, a source electrode S made of a metal such as Al is formed in contact with the source region 13 through the contact hole of the insulating film 17. Wirings such as the gate wiring 18 and the source electrode S are patterned on the interlayer insulating film 17.
As shown in FIG. 2, an Al gate wiring 18 is formed on the insulating film 17, and the gate wiring 18 is
1 to the gate pad 23. Gate wiring 18
Are arranged above the semiconductor substrate 10 between the rows of trenches, and the trenches 14 are not formed under the gate pads 23. In addition, the source electrode 24 has a source pad 24.
Are formed. Each trench 14 formed in a matrix is formed in the source region 13 (FIG. 1). It is also possible to form a plurality of trenches, for example two trenches, in one source region.

The source electrode S is commonly contacted with the surface of the second semiconductor layer 12 together with the source region 13. As a result, the substrate region and the source region are short-circuited to each other, and N which is parasitic on the drain region, the substrate region, and the source region is connected.
The effect of the PN transistor is reduced. The drain electrode D of a metal such as Al electrically connected to the drain region of the first semiconductor layer 11 is formed on the back surface of the semiconductor substrate 10.
That is, it is formed on the second main surface. The source electrode S and the drain electrode D are integrally provided for each cell, and the gate electrode G of each cell is commonly connected by the gate wiring 18, so that the cells are connected in parallel. The N-channel vertical MOSFET has a source electrode S
Is grounded, and a positive voltage is applied to the drain electrode D and the gate electrode G. When the gate voltage is increased during such a forward bias, the channel region on the side surface of the trench 14 facing the gate electrode G of the second semiconductor layer 12 is inverted from P type to N type to become an inversion layer, and the source is formed. Electrons flow from the region 13 to the eleventh semiconductor layer 11 just below the inversion layer. This vertical M
The gate insulating film 20 of the OSFET is formed of a thermal oxide film (SiO 2) on the inner surface of the trench 14 and the peripheral surface of the semiconductor substrate.
₂ film) 21 and a nitride film (Si ₃ N ₄ film) 22 are laminated to form a composite insulating film.

The gate insulating film 20 is formed by heat-treated CVD.
Since it is composed of the insulating film 22 and the thermal oxide film 21,
The electrical and mechanical characteristics are stable, and the amount of charge that is charged up is smaller than before. Next, Fig. 4
A method of manufacturing the semiconductor device of the above embodiment will be described with reference to FIGS. 4 to 8 are cross-sectional views of manufacturing steps of the semiconductor device, and FIG. 4 is a plan view illustrating the crystal structure of the gate insulating film. An N-type silicon epitaxial layer 11 which is a first semiconductor layer is grown on the first main surface of the N ⁺ silicon semiconductor substrate 10 having a thickness of about 150 μm. Further, a second semiconductor layer 12 which is a P-type channel region forming layer is formed on the epitaxial layer 11. Next, the ^{P +} (photo etching process) step and ion implantation are used to form an N ⁺ impurity diffusion region 13 to be a source region from the surface of the second semiconductor layer 12 in the surface region of the second semiconductor layer 12. Then, the plurality of trenches 14 penetrating the second semiconductor layer 12 from the surface of the source region 13 to reach the first semiconductor layer 11.
Are formed by, for example, an RIE (Reactive Ion Etching) method and are arranged in a matrix (see FIG. 1 and FIG. 4).

Next, the thermal oxide film 21 as the first insulating film is formed on the surface of the second semiconductor layer 12 including the inner wall surface of the trench 14.
Are formed (FIG. 5). The surface of the second semiconductor layer 12 is heat-treated at about 1000 ° C. in an oxidizing atmosphere to form a thermal oxide film 21.
Is formed. This heat treatment temperature is generally 900 to 110.
0 ° C is suitable. Next, CV is formed on the thermal oxide film 21.
Nitride film (CVD nitride film) 22 such as silicon formed by the D method 22
Are deposited (FIG. 6). This is the second insulating film 22. The CVD method is a method of forming a thin film such as a silicon nitride film or a silicon oxide film by a chemical reaction in a vapor phase state, and is deposited uniformly regardless of the state of the underlying layer, but the film quality (film denseness) It is inferior to the thermal oxide film. That is, FIG.
As shown in (a), pinholes and the like are present between the crystal grains of the CVD nitride film, and the denseness tends to be poor. Next, the nitride film 22 is heated to 950 ° C. or higher in an oxidizing atmosphere,
It is oxidized at 1150 ° C. or lower, for example, 1000 ° C. for about 1 hour to form a thermal oxide film which is the third insulating film 25 (FIG. 7).

Here, in the conventional vertical MOSFET, the so-called ONO film was formed by including the third insulating film as well as the first and second insulating films as its gate insulating film. In the present invention, the third insulating film 25 is formed on the second insulating film 22 and then the third insulating film 25 is formed.
Is removed by a method such as etching (FIG. 8). In order to remove the third insulating film 25, which is the thermal oxide film of silicon in this embodiment, this insulating film 2 is used.
For example, wet etching is performed using a material having a high etching selection ratio with respect to the CVD nitride film which is the second insulating film 22 so that only 5 is etched. As the material, for example, 5% or less of hydrofluoric acid (HF) is used. Therefore, the gate insulating film 20 of this vertical MOSFET
Is composed of a first insulating film 21 and a second insulating film 22, and has a thickness of, for example, about 100 nm in this embodiment. The second insulating film 22 is uniformly annealed by the heat treatment when forming the third insulating film 25. As a result, as shown in FIG. 9, the CVD nitride film 22 had a grain structure in which pinholes were present and lacked in denseness. However, as shown in FIG. Intergranular grain boundaries are partially fused and reformed into a highly dense film with few pinholes.

Next, a polysilicon film 16 doped with impurities such as phosphorus is deposited up to the periphery of the trench 14 so that the trench 14 is sufficiently filled. This polysilicon film 16 is used as a gate electrode. Then, the polysilicon film 16 is etched back to the trench 14 and its periphery so as to become a gate electrode. Then the second
An insulating film (interlayer insulating film) 17 such as a PSG film is formed on the surface of the semiconductor layer 12 by the CVD method or the like. As the insulating film material, a material such as a BPSG film other than the PSG film may be used. After that, contact holes for the gate line G and the source electrode S are opened in a part of the interlayer insulating film 17. After that, a pattern of the gate wiring S and the source electrode S made of Al, Al / Si alloy or the like is deposited on the insulating film 17. Next, the drain electrode D of Al, Al / Si alloy, or the like is formed on the entire second main surface of the semiconductor substrate 10.

Next, another method of manufacturing the semiconductor device of the above embodiment will be described. In the previous method, a thermal oxide film of silicon was used as the third insulating film to anneal the CVD nitride film which is the second insulating film.
A VD insulating film is used. When depositing this CVD insulating film on the second insulating film, the growth temperature is about 900 ° C. or 9 ° C.
If the temperature is around 50 ° C., the heat can anneal the second insulating film. Although an oxide film is used as the material of the CVD insulating film, a nitride film may be used. CVD
The insulating film is formed on the second insulating film and then removed by etching or the like. Similar to the removal of the thermal oxide film, etching is performed with a material having a high etching selection ratio with respect to the CVD nitride film which is the second insulating film so that only the CVD insulating film is etched.

[0021]

According to the present invention, since the gate insulating film is composed of two layers, that is, a heat-treated CVD insulating film and a thermal oxide film, the electrical and mechanical characteristics are stable and the charge-up is improved. Charge accumulation is less than before. Further, since the CVD insulating film is heat-treated by growing an oxide film on the surface of the CVD insulating film, the CVD insulating film is uniformly annealed.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor substrate used in a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a wiring region on the surface of the semiconductor substrate of FIG.

FIG. 3 is a sectional view of a portion taken along the line AA ′ in FIG.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device of the example.

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device of the example.

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device of the example.

FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device of the example.

FIG. 8 is a cross-sectional view of the manufacturing process of the semiconductor device of the example.

FIG. 9 is a plan view illustrating the internal structure of the gate insulating film of the semiconductor device of the example.

FIG. 10 is a sectional view of a conventional semiconductor device.

11 is a partial plan view illustrating a method of manufacturing a gate insulating film of the semiconductor device of FIG.

12 is a partial plan view of a gate insulating film of the semiconductor device of FIG.

[Explanation of symbols]

10 semiconductor substrate 11 first semiconductor layer (N-type silicon epitaxial growth layer) 12 second semiconductor layer (P-type silicon epitaxial growth layer) 13 source region 14 trenches 15 and 20 gate insulating film 16 gate electrode 17 insulating film (interlayer insulating film) ) 18 gate wiring 21 first insulating film 22 second insulating film 23 gate pad 24 source pad 25 third insulating film

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate and used as a drain region, and the first semiconductor. A second semiconductor layer of a second conductivity type formed on the layer and used as a base region, and an impurity of the first conductivity type selectively formed in a surface region of the second semiconductor layer and used as a source region. A diffusion region, an inner wall surface of a trench formed so as to reach the bottom surface in the first semiconductor layer and penetrate the impurity diffusion region and the second semiconductor layer from the surface of the impurity diffusion region, and the trench. A gate insulating film formed on the impurity diffusion region in the periphery, a gate electrode formed on the gate insulating film and formed in and around the trench, and formed on the second semiconductor layer. A source electrode electrically connected to at least the source region and a drain electrode formed on the second main surface of the semiconductor substrate, wherein the gate insulating film includes a portion including the inside of the trench. A thermal oxide film formed by heat-treating the surface of the second semiconductor layer in an oxidizing atmosphere, and a heat-treated CV formed on the thermal oxide film.
A semiconductor device comprising a D insulating film. 2. The semiconductor device according to claim 1, wherein the CVD insulating film is a silicon nitride film or a silicon oxide film. 3. A step of forming a first-conductivity-type first semiconductor layer used as a drain region on a first main surface of a semiconductor substrate, and a step of forming a first region on the first semiconductor layer as a base region. Forming a second conductive type second semiconductor layer; selectively forming a first conductive type impurity diffusion region used as a source region in a surface region of the second semiconductor layer; Forming a trench that penetrates the impurity diffusion region and the second semiconductor layer from the surface of the region and reaches the bottom of the first semiconductor layer, and the impurity on the inner wall surface of the trench and around the trench. Forming a thermal oxide film, which is a first insulating film, on the diffusion region by heat treatment in an oxidizing atmosphere; and forming a CVD insulating film, which is a second insulating film, on the first insulating film. When Forming a thermal oxide film, which is a third insulating film, on the second insulating film by heat treatment in an oxidizing atmosphere; and removing the third insulating film from the second insulating film. Forming a gate electrode in and around the trench on the second insulating film; and forming a source electrode electrically connected to at least the source region on the second semiconductor layer. A step of forming a drain electrode on the second main surface of the semiconductor substrate, and forming a gate insulating film with the first and second insulating films,
The method of manufacturing a semiconductor device, wherein the second insulating film is annealed by heat treatment in the step of manufacturing the third insulating film. 4. A step of forming a first semiconductor layer of a first conductivity type used as a drain region on a first main surface of a semiconductor substrate, and a step of forming a first semiconductor layer on the first semiconductor layer as a base region. Forming a second conductive type second semiconductor layer; selectively forming a first conductive type impurity diffusion region used as a source region in a surface region of the second semiconductor layer; Forming a trench that penetrates the impurity diffusion region and the second semiconductor layer from the surface of the region and reaches the bottom surface of the trench in the first semiconductor layer; and on an inner wall surface including the bottom surface of the trench and around the trench. Forming a thermal oxide film that is a first insulating film on the impurity diffusion region by heat treatment in an oxidizing atmosphere; and forming a CVD insulating film that is a second insulating film on the first insulating film. Formation A step of forming a CVD oxide film, which is a third insulating film, on the second insulating film; a step of removing the third insulating film from the second insulating film; Forming a gate electrode in and around the trench on the second insulating film; forming a source electrode electrically connected to at least the source region on the second semiconductor layer; A step of forming a drain electrode on the second main surface of the semiconductor substrate, and forming a gate insulating film with the first and second insulating films,
The method of manufacturing a semiconductor device, wherein the second insulating film is annealed by heat treatment in the step of manufacturing the third insulating film.