KR100516153B1 - Method for fabricating a SOI MOSFET device having elevated source/drain formed by using a reflow process - Google Patents

Abstract

Provided is a method of manufacturing a microchannel SOI MOSFET (MOSFET) device using an SOI substrate. The present invention forms an elevated source / drain (ESD) using a reflow process of a hydrogen silsesquioxane (HSQ) film, and forms an insulating film having a low dielectric constant as an interlayer insulating film. Accordingly, the present invention uses an SOI substrate having a low resistance source / drain and a low dielectric constant interlayer insulating film and a very thin silicon channel layer to suppress the short channel effect, improve driving capability, and improve the RC delay time. SOI MOSFET devices with improved low power and high speed operation can be fabricated.

Description

Method for fabricating a SOI MOSFET device having elevated source / drain formed by using a reflow process} [0003] Method of fabricating a SOI MOSFET device having an elevated source / drain formed using a reflow process

The present invention mospet ((elevated source / drain) (silicon on insulator)

In general, semiconductor devices are being reduced in size in order to achieve low power, high integration, and ultra-fast operation characteristics. In particular, the MOSFET device, which occupies most of the semiconductor device, needs to shorten the channel length, reduce the source / drain junction depth, and reduce the gate insulating film thickness. In addition, the MOSFET device must achieve high performance of device characteristics by increasing driving current and reducing leakage current even in devices of the same size. However, as the size of the semiconductor device decreases, short channel effects appear, thereby reducing the turn-on speed of the device and making it difficult to adjust the threshold voltage. As a result, there are many limitations to fabricating high performance and ultrafine MOSFET devices using conventional manufacturing processes.

In order to solve this problem, an SOI MOSFET device using a very thin single crystal silicon film as a channel on a buried oxide has been proposed. However, the source / drain formation technique in the ultrathin single crystal silicon film is easy to form a shallow junction, but the sheet resistance is very high due to the thin junction thickness. In addition, in the source / drain formation technique by ion implantation or plasma doping, defects in the substrate are generated due to ion implantation, resulting in deterioration of device characteristics and the need for expensive junction formation equipment.

In order to solve this problem, an SOI MOSFET device having an elevated source / drain (ESD) formed by epitaxial growth has been proposed. The SOI MOSFET device having such an elevated source / drain is very expensive to manufacture, has difficulty in securing uniformity of the entire substrate, and requires a subsequent impurity implantation process. Therefore, a new manufacturing process is required to solve these problems and to realize high integration and high performance integrated circuits.

Accordingly, an object of the present invention is to solve the problems of the prior art, and to provide a method for manufacturing a SOI MOSFET device having low source / drain sheet resistance and capable of low power and high speed operation.

In order to achieve the above technical problem, the present invention includes forming a gate stack on a single crystal silicon film of an SOI substrate, and then forming gate spacers on both sidewalls of the gate stack. After the conductive film is formed on the gate spacer, the gate stack, and the single crystal silicon film, sources / drains are formed in the single crystal silicon films on both sides of the gate stack. After forming an HSQ film on the conductive film, the HSQ film is reflowed to form a planarization layer exposing an upper surface of the conductive film on the gate stack. The conductive layer formed on the upper surface of the gate stack and the gate spacer is selectively etched to form holes, and an elevated source / drain is formed on the source / drain. An interlayer insulating layer is formed on the gate stack, the gate spacer, and the planarization layer while filling the hole.

As described above, the present invention forms an elevated source / drain on the source / drain through the reflow process, the planarization process using the height difference between the gate stack and the source / drain, and the selective etching process of the conductive film. Minimized SOI MOSFETs can be manufactured with low power and high speed operation.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the size or thickness of films or regions is exaggerated for clarity.

1 to 16 are diagrams for explaining the manufacturing method of the SOI MOSFET device according to the present invention.

1 shows a step of preparing an SOI substrate 16.

Specifically, an SOI substrate 16 composed of a buried oxide film 12 and a very thin single crystal silicon film 14 is prepared on the lower single crystal silicon film 10 as a substrate material. The single crystal silicon film 14 may be formed by thinning a portion of the single crystal silicon film 14 by using an oxidation process, and then etching the oxide film formed by the oxidation process. Alternatively, a portion of the single crystal silicon film 14 may be removed by using a silicon etching solution or a plasma dry etching method to thin the single crystal silicon film 14.

2 shows a step of forming the first insulating film 18.

Specifically, the first insulating film 18 is formed on the thin single crystal silicon film 14 of the SOI substrate 16 to have an electrically thin thickness. The first insulating film 18 later becomes a gate insulating film. The first insulating film 18 is formed of a silicon oxide film, a nitride film, or an insulating film having a high dielectric constant of 2 nm or less in thickness. The first insulating film 18 is formed using various thin film formation methods such as thermal oxidation, CVD, sputtering, and ALD.

3 illustrates a step of forming the first conductive film 20.

Specifically, a first conductive film 20 is formed on the first insulating film 18. The first conductive film 20 later becomes a gate electrode. The first conductive film 20 may be formed using a silicon film or a metal film containing impurities. In order to control the threshold voltage of the transistor, the first conductive layer 20 uses a material having a work function larger than that of the silicon channel layer, that is, a work function of 4.4 to 5.2 eV, for the n-type MOSFET device. For the -type MOSFET device, a material having a work function smaller than that of the silicon channel layer, that is, a material having a work function of 4.1 to 4.8 eV is preferable. The first conductive film 20 is formed using various thin film formation methods such as CVD, sputtering, ALD, and MBE.

4 illustrates forming a hard mask 22.

Specifically, the hard mask 22 is formed on the first conductive film 20. The hard mask 22 acts as a gate etch mask when later forming a gate stack. The hard mask 22 is formed using a silicon oxide film, a silicon nitride film, or a metal oxide film. The hard mask 22 is formed using various thin film formation methods such as thermal oxidation, CVD, sputtering, spin coating, and the like.

5 illustrates forming a gate stack 24.

Specifically, a gate mask pattern (not shown) for forming a gate electrode is formed on the hard mask 22. Subsequently, the hard mask 22, the first conductive layer 20, and the first insulating layer 18 are sequentially etched using the gate mask pattern as an etching mask. In this case, the gate stack 24 made of the gate insulating film 18a, the gate electrode 20a, and the hard mask pattern 22a is formed on the single crystal silicon layer 14. The hard mask 22, the first conductive layer 20, and the first insulating layer 18 may be etched using a dry etching method. The gate mask pattern may use an organic register or an inorganic register, and is formed using DUV, EUV or electron beam lithography equipment. When the gate mask pattern is formed using electron beam lithography, HSQ may be used as an inorganic register, and in this case, the hard mask may not be necessary.

6 shows a step of forming the second insulating film 26.

Specifically, the second insulating layer 26 is formed on the entire surface of the SOI substrate 16 on which the gate stack 24 is formed. It is formed on the surface and sidewalls of the gate stack 24 of the second insulating film 26 and on the single crystal silicon film 14. The second insulating film is formed using a silicon oxide film or a silicon nitride film. The second insulating film is formed using a thin film forming method such as ALD method, MOALD method, CVD method, MOCVD method and the like.

7 illustrates forming a gate spacer 26a.

Specifically, the second insulating layer 26 is anisotropically etched to form gate spacers 26a on both sidewalls of the gate stack 24. In other words, the second insulating layer 26 is etched using the anisotropic etching apparatus to expose the single crystal silicon layer 14. In this case, gate spacers 26a are formed on both side walls of the gate stack 26.

8 shows forming the second conductive film 28.

Specifically, the second conductive layer 28 is formed on the entire surface of the SOI substrate 16 on which the gate stack 24 and the gate spacer 26a are formed. That is, the second conductive film 28 is formed on the surface of the single crystal silicon film 14, the surface of the gate stack, and the gate spacer. The second conductive film 28 is formed in-situ using a silicon film, a silicon-germanium alloy, or a germanium film containing impurities. Impurities contained in the second conductive film 28 include phosphorus or arsenic in the case of an n-type MOSFET, and fluorine or indium in the case of a p-type MOSFET. The second conductive layer 28 is formed to a thickness of 30 to 50nm. The second conductive film 28 is formed using a thin film formation method such as CVD, sputtering, ALD, MBE, or the like. The second conductive layer 28 has an amorphous or polycrystalline state when deposited, and is later formed to a thickness of 30 to 50 nm to reduce the source / drain and gate overlap capacitance and the sheet resistance of the source / drain.

9 illustrates forming a source / drain 30.

Specifically, impurities are introduced into the single crystal silicon film 14 below the second conductive film 28 to form an electrically conductive source / drain 30. That is, impurities are introduced into the single crystal silicon film 14 on both sides of the gate stack 24 to form the source / drain 30. The impurity introduction for the source / drain is performed by using a thermal diffusion method for thermally diffusing impurities contained in the second conductive layer 28.

10 to 12 illustrate forming a second conductive layer pattern 28a and a hydrogen silsesquioxane (HSQ) layer.

Specifically, FIG. 10 is a plan layout diagram of the MOSFET device manufactured up to FIG. 9. Referring to FIG. 10, a second conductive layer 28 is formed on the SOI substrate 16. Referring to FIG. 11, after forming a mask pattern (not shown) for forming an elevation source / drain on the second conductive layer 28, the second conductive layer 28 and the single crystal silicon layer 14 may be formed. Is a planar layout diagram in which the second conductive film pattern 28a is formed by etching sequentially. The second conductive layer 28 and the single crystal silicon layer 14 may be etched by a selective dry etching method of the gate spacer 26a and the hard mask pattern 22a. As shown in FIG. 11, the second conductive film pattern 28a is formed in the horizontal direction, and the hard mask pattern 22a, the gate spacer 26a, and the buried oxide layer 12 are formed. Next, as shown in FIG. 12, an HSQ film 32 is formed on the second conductive film pattern 28a. The HSQ film 32 is formed using a spin coater.

13 shows forming the planarization layer 32a.

In detail, the HSQ layer 32 formed on the second conductive layer pattern 28a on the hard mask pattern 22a may be formed using a gate spacer (eg, a height difference between the gate stack and the source / drain 30). The flattening layer 32a is formed by reflowing toward 26a). The planarization layer 32a is formed by heat-treating the HSQ film 32 on the hard mask pattern 22a by a reflow process. The reflow process is performed by heat-treating the HSQ film deposited by the spin coater for several minutes at 300 to 500 degrees in a nitrogen atmosphere. In this case, the surface of the second conductive layer pattern 28a on the gate stack 24 is exposed to the outside.

14 illustrates etching the second conductive film pattern 28a on the hard mask pattern 22a.

Specifically, the second conductive layer pattern 28 having the surface exposed on the hard mask pattern 22a is selectively etched. In this case, the second conductive layer pattern 28a formed on the sidewall of the gate spacer 26a is also selectively etched to form a hole 33 along the gate spacer 26a. This causes a short circuit between the source / drain 30 and the gate stack 24, and an elevated source / drain 34 is formed on the source / drain 30. Since the sheet resistance of the source / drain can be reduced due to the formation of the elevated source / drain, an SOI MOSFET device having a very small channel length capable of suppressing short channel effects and improving driving capability can be manufactured.

Selective etching of the second conductive layer pattern 28a may be performed using a dry etching method or a wet etching method using an etching selectivity between the hard mask pattern 22a and the second conductive layer pattern 28a. In this case, since the etching solution or the etching gas performs an isotropic etching characteristic using a material, the second conductive layer pattern 28a formed on the sidewall of the gate spacer 26a is also etched to form holes 33 along the gate spacer. Is formed. In other words, the selective etching of the second conductive layer pattern 28a may have an etching selectivity with the hard mask pattern 22a constituting the planarization layer 32a and the gate stack 24. 28a) is carried out using an etching solution or an etching gas capable of isotropic etching.

15 shows a step of forming the interlayer insulating film 36.

Specifically, an interlayer insulating layer 36 is formed on the entire surface of the SOI substrate 16 on which the gate stack 24 and the elevated source / drain 34 are formed. That is, the interlayer insulating layer 36 is formed on the planarization layer 32a while filling the hole 33. The interlayer insulating layer 36 may be formed using an HSQ film or an oxide film or a nitride film deposited by various methods. When the interlayer insulating film 36 is used as an HSQ film, an HSQ film is further formed on the planarization layer 32a.

16 illustrates forming electrodes 44, 46, and 48.

Specifically, the contact holes 38 may be electrically connected to the interlayer insulating layer 36 on the elevation source / drain 34, the hard mask pattern 22a and the interlayer insulating layer 36 on the gate electrode 20a. 40, 42). By forming the electrodes 44, 46, and 48 as the wiring material in the contact holes 38, 40, and 42, an ultra-thin SOI MOSFET device having an ultra-fine channel is completed.

As described above, the present invention forms an elevated source / drain on the source / drain through a reflow process, a planarization process using a height difference between the gate stack and the source / drain, and a selective etching process of the second conductive layer pattern. Accordingly, the present invention provides a SOI MOSFET device having a short channel effect and improved driving ability by minimizing sheet resistance of the source / drain without forming an elevated source / drain by an expensive epitaxial growth method as compared with the conventional art. can do.

In the present invention, since the second conductive film made of a silicon film, a silicon-germanium alloy film, or a germanium film containing impurities can be formed in-situ during the deposition of a thin film, the elementary element / elevation method can be formed by a solid phase diffusion method without a separate impurity implantation process. A drain can be formed. Therefore, since the defect of the SOI substrate is not generated by the ion implantation, the leakage current through the junction can be reduced.

According to the present invention, an interlayer insulating film made of an HSQ film on an elevated source / drain is a low dielectric constant insulating film, which prevents RC delay due to parasitic capacitance of the device, thereby manufacturing an ultra-high speed SOI MOSFET device.

The present invention can form low-resistance elevated sources / drains and sources / drains that require low power and high speed operation, thereby producing SOI MOSFET devices having high performance and high integration microchannels.

1 to 16 are diagrams for explaining the manufacturing method of the SOI MOSFET device according to the present invention.

Claims (10)

Forming a gate stack on the single crystal silicon film of the SOI substrate; Forming gate spacers on both sidewalls of the gate stack; Forming a conductive film on the gate spacer, the gate stack, and the single crystal silicon film; Forming a source / drain in the single crystal silicon film on both sides of the gate stack; Forming an HSQ film on the conductive film; Reflowing the HSQ film to form a planarization layer exposing the top surface of the conductive film on the gate stack; Selectively etching the conductive layer formed on the upper surface of the gate stack and the gate spacer to form a hole, and forming an elevated source / drain on the source / drain; And Forming an interlayer insulating film on the gate stack, the gate spacer, and the planarization layer while filling the hole. The method of claim 1, wherein the gate stack is formed by sequentially forming a gate insulating film, a gate electrode, and a hard mask pattern on a single crystal silicon film of an SOI substrate. The method of manufacturing a SOI MOSFET device according to claim 2, wherein the conductive film constituting the gate electrode is formed of a silicon film or a metal film containing impurities. 4. The conductive film of claim 3, wherein the conductive film constituting the gate electrode is formed of a material having a work function larger than that of the silicon channel layer for the n-type MOSFET, and a material having a work function smaller than the silicon channel layer for the p-type MOSFET. Forming a SOI MOSFET device characterized in that the formation. The method of claim 1, wherein the conductive film is formed in-situ using a silicon film, a silicon-germanium alloy, or a germanium film containing impurities. The method of claim 1, wherein the source / drain is formed by thermally diffusing impurities included in the conductive layer. The method of claim 1, wherein the reflow of the HSQ film is performed by heat treatment for several minutes in a nitrogen atmosphere of 300 to 500 degrees. The etching method of claim 1, wherein the selective etching of the conductive layer is performed using an etching solution or an etching gas capable of isotropically etching the conductive layer and having a hard mask pattern and an etching selectivity constituting the planarization layer and the gate stack. The manufacturing method of SOI MOSFET element. 2. The method of claim 1, wherein contact holes are formed in the interlayer insulating film on the elevated source / drain and gate stack, and electrodes are formed in the contact holes. The method of claim 1, wherein the interlayer insulating film is formed using an HSQ film, an oxide film, or a nitride film.