CN117672856A - Method for forming semiconductor structure - Google Patents
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- CN117672856A CN117672856A CN202211038634.7A CN202211038634A CN117672856A CN 117672856 A CN117672856 A CN 117672856A CN 202211038634 A CN202211038634 A CN 202211038634A CN 117672856 A CN117672856 A CN 117672856A
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000001312 dry etching Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 210000004690 animal fin Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of device regions and at least one isolation region, the device regions are arranged along a first direction, and the isolation regions are positioned between adjacent device regions; forming a dielectric layer and a first gate structure on the substrate, wherein the first gate structure spans across the fin part, the first gate structure is positioned on the isolation region, and the dielectric layer covers the side wall of the first gate structure; forming a mask structure on the dielectric layer, wherein a mask opening exposing the top surface of the first gate structure is formed in the mask structure; removing the first grid structure and the fin part partially covered by the first grid structure by using the mask structure as a mask and adopting an anisotropic dry etching process, and forming isolation openings in the dielectric layer and the fin part; an isolation structure is formed within the isolation opening. The first grid electrode structure is removed through an anisotropic dry etching process, damage to device structures adjacent to the first grid electrode structure can be reduced, and further performance of a finally formed semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
With the increase in the integration level of semiconductor devices, the critical dimensions of transistors are continually shrinking. However, as the transistor size is rapidly reduced, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gates of Fin Field effect transistors (Fin Field-Effect Transistor, finFETs) are in a fork-like 3D architecture resembling a fish Fin. The channel of the FinFET protrudes out of the surface of the substrate to form a fin portion, and the grid electrode covers the top surface and the side wall of the fin portion, so that inversion layers are formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin portion. This design can increase the control of the gate over the channel region, thereby well suppressing the short channel effect of the transistor. However, fin field effect transistors still have short channel effects.
In addition, to further reduce the effect of short channel effects on the semiconductor device, channel leakage current is reduced. The field of semiconductor technology introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in fin parts on two sides of the grid structure; and forming source-drain doped regions in the grooves through an epitaxial growth process.
In order to prevent the source and drain doped regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin portion, and in order to reduce the area of the isolation layer, the integration level of the formed semiconductor structure is improved. The prior art incorporates SDB (Single Diffusion Break) technology.
However, the existing methods still have problems in forming semiconductor structures.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure to improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of device regions and at least one isolation region, the device regions are arranged along a first direction, and the isolation region is positioned between adjacent device regions; forming a dielectric layer and a first gate structure on the substrate, wherein the first gate structure spans across the fin part, the first gate structure is positioned on the isolation region, and the dielectric layer covers the side wall of the first gate structure; forming a mask structure on the dielectric layer, wherein a mask opening exposing the top surface of the first gate structure is formed in the mask structure; using the mask structure as a mask, removing the first grid structure and the fin part partially covered by the first grid structure by adopting an anisotropic dry etching process, and forming isolation openings in the dielectric layer and the fin part; an isolation structure is formed within the isolation opening.
Optionally, the anisotropic dry etching process includes: an atomic layer dry etching process.
Optionally, the etching gas of the atomic layer dry etching process is CH 2 F 2 、O 2 And Ar.
Optionally, the etching temperature of the atomic layer dry etching process is 25-50 ℃.
Optionally, the material of the first gate structure includes: a metal; the metal comprises: tungsten.
Optionally, the mask structure is a multilayer structure; the mask structure comprises a first mask layer and a plurality of second mask layers which are stacked in sequence from bottom to top.
Optionally, the material of the first mask layer includes: tantalum nitride.
Optionally, in the process of forming the dielectric layer and the first gate structure, the method further includes: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the fin parts, the second gate structures are positioned on the device region, and the dielectric layer covers the side walls of the second gate structures.
Optionally, before forming the first gate structure and the second gate structure, the method further includes: and forming a plurality of source-drain doped layers in the fin part, wherein the source-drain doped layers are positioned between the adjacent first gate structure and the second gate structure or between the adjacent second gate structures.
Optionally, before forming the source-drain doped layer, the method further includes: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure spans across the fin portion, and the first dummy gate structure is located on the isolation region; and forming a plurality of second dummy gate structures on the substrate, wherein the second dummy gate structures cross the fin part, and the second dummy gate structures are positioned on the device region.
Optionally, the method for forming the source-drain doped layer includes: etching the fin portion by taking the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of source drain openings in the fin portion; and forming the source-drain doping layer in the source-drain opening.
Optionally, the forming method of the first gate structure and the plurality of second gate structures includes: removing the first dummy gate structure, and forming a first gate opening in the dielectric layer; forming the first gate structure within the first gate opening; removing the second dummy gate structure, and forming a second gate opening in the dielectric layer; the second gate structure is formed within the second gate opening.
Optionally, the method for forming the isolation structure includes: forming an initial isolation structure in the isolation opening and on the dielectric layer; and flattening the initial isolation structure until the top surface of the dielectric layer is exposed, so as to form the isolation structure.
Optionally, the material of the isolation structure includes silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme of the invention, the mask structure is used as a mask, the first grid structure and part of the fin part covered by the first grid structure are removed by adopting an anisotropic dry etching process, and isolation openings are formed in the dielectric layer and the fin part. And removing the first grid electrode structure through an anisotropic dry etching process, so that damage to the device structure adjacent to the first grid electrode structure can be reduced, and further, the performance of the finally formed semiconductor structure is improved.
Further, the material of the first gate structure includes: a metal; the metal comprises: tungsten; the mask structure is a multilayer structure; the mask structure comprises a first mask layer and a plurality of second mask layers which are stacked in sequence from bottom to top; the material of the first mask layer comprises: tantalum nitride; the anisotropic dry etching process comprises the following steps: an atomic layer dry etching process; the technological parameters of the atomic layer dry etching process comprise: etching gas CH 2 F 2 、O 2 Ar; the etching time is 80 s-120 s; the etching temperature is 25-50 ℃. The etching temperature of 25-50 ℃ can maximize the etching selectivity of the atomic layer dry etching process to tungsten and titanium nitride, so that the etching damage to the first mask layer can be further reduced, the damage to the adjacent device structure of the first grid structure is further reduced, and the performance of the finally formed semiconductor structure is further improved.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor structure;
fig. 4 to 12 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the prior art methods still have problems in forming semiconductor structures. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 to 3 are schematic structural views of a semiconductor structure.
Referring to fig. 1, the method includes: providing a substrate 100, wherein the substrate 100 is provided with a fin part 101, the fin part 101 comprises a first device region A1, a second device region A2 and a first isolation region B1 which are arranged along a first direction X, and the first isolation region B1 is positioned between adjacent first device region A1 and second device region A2; forming a dielectric layer 102, a first gate structure 103 and a plurality of second gate structures 104 on the substrate 100, wherein the first gate structure 103 spans across the fin 101 and is located on the first isolation region B1, the plurality of second gate structures 104 spans across the fin 101 and is located on the first device region A1 and the second device region A2, respectively, and the dielectric layer 102 covers sidewalls of the first gate structure 103 and the second gate structure 104; a mask structure 105 is formed on the dielectric layer 102, and a mask opening 106 exposing a top surface of the first gate structure 103 is formed in the mask structure 105.
Referring to fig. 2, with the mask structure 105 as a mask, a wet etching process is used to remove the first gate structure 103 and the fin portion 101 partially covered by the first gate structure 103, so as to form isolation openings 107 in the dielectric layer 102 and the fin portion 101.
Referring to fig. 3, after forming the isolation opening 107, the mask structure 105 is removed; after removing the mask structure 105, an isolation structure 108 is formed within the isolation opening 107.
In this embodiment, by forming the isolation structure 108, the problem of shorting between the source and drain doped layers formed in the fin 101 adjacent to each other can be effectively prevented, thereby achieving an isolation effect.
In this embodiment, the mask structure 105 is a multi-layer structure; the mask structure 105 includes a first mask layer and a plurality of second mask layers (not shown) stacked in sequence from bottom to top. The material of the first mask layer is tantalum nitride, and the material of the first gate structure 103 includes tungsten because the tantalum nitride material and the silicon nitride material of the isolation structure have a high grinding selectivity. However, since the isotropic wet etching process is used to remove the first gate structure 103, and the wet etching process has a relatively low etching selectivity to tantalum nitride and tungsten, the etching solution can simultaneously laterally etch the first mask layer in the process of removing the first gate structure 103 by using the wet etching process, thereby damaging the adjacent second gate structure 104 and affecting the performance of the finally formed semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, which uses the mask structure as a mask, adopts an anisotropic dry etching process to remove the first gate structure and the fin part partially covered by the first gate structure, and forms isolation openings in the dielectric layer and the fin part. And removing the first grid electrode structure through an anisotropic dry etching process, so that damage to the device structure adjacent to the first grid electrode structure can be reduced, and further, the performance of the finally formed semiconductor structure is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 12 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a fin 201 thereon, where the fin 201 includes a plurality of device regions arranged along a first direction X and at least one isolation region, and the isolation region is located between adjacent device regions.
In this embodiment, the plurality of device regions includes: a first device region A1 and a second device region A2; the at least one isolation region comprises: a first isolation region B1, where the first isolation region B1 is located between the first device region A1 and the second device region A2, and the fin 101 extends from above the first device region A1 to above the second device region A2 and spans the isolation region B1.
In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
Referring to fig. 5, an isolation layer 202 is formed on the substrate 200, the isolation layer 202 covers a portion of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.
In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200; and etching to remove part of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.
The material of the isolation layer 202 is an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.
In this embodiment, after forming the isolation layer 202, it further includes: forming a dielectric layer and a first gate structure on the substrate 200, wherein the first gate structure spans across the fin 201, the first gate structure is located on the isolation region, and the dielectric layer covers the side wall of the first gate structure; forming a plurality of second gate structures on the substrate 200, wherein the second gate structures cross the fin 201, the second gate structures are located on the device region, and the dielectric layer covers the side walls of the second gate structures; a plurality of source-drain doped layers are formed in the fin 201, and the source-drain doped layers are located between the adjacent first gate structure and the second gate structure or between the adjacent second gate structures. The specific forming process is shown in fig. 6 to 9.
Referring to fig. 6, a first dummy gate structure 203 is formed on the substrate 200, the first dummy gate structure 203 spans the fin 201, and the first dummy gate structure 203 is located on the isolation region; a plurality of second dummy gate structures 204 are formed on the substrate 200, the second dummy gate structures 204 straddling the fin 201, the second dummy gate structures 204 being located on the device region.
In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 are formed simultaneously by using a global process. The first dummy gate structure 203 is located on the first isolation region B1, and the plurality of second dummy gate structures 204 are located on the first device region A1 and the second device region A2, respectively.
In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 each include: a dummy gate dielectric layer, and a dummy gate layer (not labeled) on the dummy gate dielectric layer.
In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the dummy gate dielectric layer material may also be silicon oxynitride.
In this embodiment, the dummy gate layer is made of polysilicon.
With continued reference to fig. 6, after forming the first dummy gate structure 203 and the second dummy gate structure 204, the method further includes: side walls 205 are formed on the side walls of the first dummy gate structure 203 and the second dummy gate structure 204, respectively.
In this embodiment, the material of the side wall 205 is silicon nitride.
Referring to fig. 7, the fin 201 is etched by using the first dummy gate structure 203 and the second dummy gate structure 204 as masks, and a plurality of source-drain openings (not labeled) are formed in the fin 201; the source-drain doped layer 206 is formed within the source-drain openings.
In this embodiment, the method for forming the source-drain doped layer 206 in the source-drain opening includes: forming an epitaxial layer (not shown) in the source drain openings by adopting an epitaxial growth process; source and drain ions are doped into the epitaxial layer during the formation of the epitaxial layer by using an in-situ doping process, so as to form the source and drain doped layer 206.
In this embodiment, the source and drain ions are N-type ions. In other embodiments, P-type ions may also be used as the source and drain ions.
Referring to fig. 8, after the source-drain doped layer 206 is formed, a dielectric layer 207 is formed on the substrate 200, and the dielectric layer 207 covers sidewalls of the first dummy gate structure 203 and the second dummy gate structure 204.
In this embodiment, the method for forming the dielectric layer 207 includes: forming an initial dielectric layer (not shown) on the substrate 200, wherein the initial dielectric layer covers the first dummy gate structure 203 and the second dummy gate structure 204; the initial dielectric layer is planarized until the top surfaces of the first dummy gate structure 203 and the second dummy gate structure 204 are exposed, forming the dielectric layer 207.
In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
Referring to fig. 9, the first dummy gate structure 203 is removed, and a first gate opening (not labeled) is formed in the dielectric layer 207; forming the first gate structure 208 within the first gate opening; removing the second dummy gate structure 204, and forming a second gate opening (not shown) in the dielectric layer 207; the second gate structure 209 is formed within the second gate opening.
In this embodiment, the first gate structure 208 and the second gate structure 209 are formed simultaneously using a global process. The first gate structure 208 is located on the first isolation region B1, and the plurality of second gate structures 209 are located on the first device region A1 and the second device region A2, respectively.
In this embodiment, the first gate structure 208 and the second gate structure 209 each include: a gate dielectric layer, a work function layer on the gate dielectric layer, and a gate layer (not labeled) on the work function layer.
In this embodiment, the gate dielectric layer includes a high K dielectric material.
The material of the gate layer comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, tungsten is used as the material of the gate layer.
Referring to fig. 10, a mask structure 210 is formed on the dielectric layer 207, and a mask opening 211 exposing a top surface of the first gate structure 208 is formed in the mask structure 210.
In this embodiment, the mask structure 210 is a multi-layer structure; the mask structure 210 includes a first mask layer and a plurality of second mask layers (not shown) stacked in sequence from bottom to top.
In this embodiment, the material of the first mask layer is titanium nitride; the second mask layers are three layers, and the materials from the bottom to the top of the second mask layers are respectively: silicon oxide, silicon nitride, silicon oxide.
Referring to fig. 11, with the mask structure 210 as a mask, an anisotropic dry etching process is used to remove the first gate structure 208 and the fin 201 partially covered by the first gate structure 208, so as to form isolation openings 212 in the dielectric layer 207 and the fin 201.
In this embodiment, the first gate structure 208 is removed by an anisotropic dry etching process, so that damage to the second gate structure 209 adjacent to the first gate structure 208 can be reduced, and further, performance of the finally formed semiconductor structure is improved.
In this embodiment, the anisotropic dry etching process employs an atomic layer dry etching process; the technological parameters of the atomic layer dry etching process comprise: etching gas CH 2 F 2 、O 2 And Ar; the etching time is 80 s-120 s; the etching temperature is 25-50 ℃. The etching temperature of 25-50 ℃ can maximize the etching selectivity of the atomic layer dry etching process to tungsten and titanium nitride, so that the etching damage to the first mask layer can be further reduced, the damage to the device structure adjacent to the first gate structure 208 is further reduced, and the performance of the finally formed semiconductor structure is further improved.
With continued reference to fig. 11, in this embodiment, after forming the isolation opening 212, the method further includes: the mask structure 210 is removed.
Referring to fig. 12, an isolation structure 213 is formed in the isolation opening 212.
In this embodiment, the method for forming the isolation structure 213 includes: forming an initial isolation structure (not shown) within the isolation opening 212 and over the dielectric layer 207; the initial isolation structure is planarized until the top surface of the dielectric layer 207 is exposed, forming the isolation structure 213.
In this embodiment, the planarization process is performed on the initial isolation structure by using a chemical mechanical polishing process.
In this embodiment, the material of the isolation structure 213 includes silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of device regions and at least one isolation region, the device regions are arranged along a first direction, and the isolation region is positioned between adjacent device regions;
forming a dielectric layer and a first gate structure on the substrate, wherein the first gate structure spans across the fin part, the first gate structure is positioned on the isolation region, and the dielectric layer covers the side wall of the first gate structure;
forming a mask structure on the dielectric layer, wherein a mask opening exposing the top surface of the first gate structure is formed in the mask structure;
using the mask structure as a mask, removing the first grid structure and the fin part partially covered by the first grid structure by adopting an anisotropic dry etching process, and forming isolation openings in the dielectric layer and the fin part;
an isolation structure is formed within the isolation opening.
2. The method of forming a semiconductor structure of claim 1, wherein the anisotropic dry etching process comprises: an atomic layer dry etching process.
3. The method of forming a semiconductor structure of claim 2, wherein the etching of the atomic layer dry etching processThe gas being CH 2 F 2 、O 2 And Ar.
4. The method of forming a semiconductor structure as claimed in claim 2, wherein the atomic layer dry etching process has an etching time of 80s to 120s.
5. The method of forming a semiconductor structure of claim 2, wherein the atomic layer dry etching process has an etching temperature of 25 ℃ to 50 ℃.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the first gate structure comprises: a metal; the metal comprises tungsten.
7. The method of forming a semiconductor structure of claim 1, wherein the mask structure is a multi-layer structure; the mask structure comprises a first mask layer and a plurality of second mask layers which are stacked in sequence from bottom to top, wherein the material of the first mask layer comprises tantalum nitride.
8. The method of forming a semiconductor structure of claim 1, further comprising, during forming the dielectric layer and the first gate structure: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the fin parts, the second gate structures are positioned on the device region, and the dielectric layer covers the side walls of the second gate structures.
9. The method of forming a semiconductor structure of claim 8, further comprising, prior to forming the first gate structure and the second gate structure: and forming a plurality of source-drain doped layers in the fin part, wherein the source-drain doped layers are positioned between the adjacent first gate structure and the second gate structure or between the adjacent second gate structures.
10. The method of forming a semiconductor structure of claim 9, further comprising, prior to forming the source drain doped layer: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure spans across the fin portion, and the first dummy gate structure is located on the isolation region; and forming a plurality of second dummy gate structures on the substrate, wherein the second dummy gate structures cross the fin part, and the second dummy gate structures are positioned on the device region.
11. The method of forming a semiconductor structure of claim 10, wherein the method of forming a source drain doped layer comprises: etching the fin portion by taking the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of source drain openings in the fin portion; and forming the source-drain doping layer in the source-drain opening.
12. The method of forming a semiconductor structure of claim 10, wherein the method of forming the first gate structure and the plurality of second gate structures comprises: removing the first dummy gate structure, and forming a first gate opening in the dielectric layer; forming the first gate structure within the first gate opening; removing the second dummy gate structure, and forming a second gate opening in the dielectric layer; the second gate structure is formed within the second gate opening.
13. The method of forming a semiconductor structure of claim 1, wherein the method of forming an isolation structure comprises: forming an initial isolation structure in the isolation opening and on the dielectric layer; and flattening the initial isolation structure until the top surface of the dielectric layer is exposed, so as to form the isolation structure.
14. The method of forming a semiconductor structure of claim 1, wherein the material of the isolation structure comprises silicon nitride.
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| CN202211038634.7A CN117672856A (en) | 2022-08-26 | 2022-08-26 | Method for forming semiconductor structure |
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| CN202211038634.7A CN117672856A (en) | 2022-08-26 | 2022-08-26 | Method for forming semiconductor structure |
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