CN114530379A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114530379A
CN114530379A CN202011323065.1A CN202011323065A CN114530379A CN 114530379 A CN114530379 A CN 114530379A CN 202011323065 A CN202011323065 A CN 202011323065A CN 114530379 A CN114530379 A CN 114530379A
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China
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forming
isolation
region
gate structure
dielectric layer
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涂武涛
陈建
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011323065.1A priority Critical patent/CN114530379A/en
Publication of CN114530379A publication Critical patent/CN114530379A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part, and the fin part comprises a device region and an isolation region; forming an isolation layer on a substrate; forming a first gate structure on a substrate, the first gate structure including a first region and a second region located on the first region; removing the second region to form an initial first opening; removing the isolation region to form a second opening; removing the first region to form a first opening; isolation structures are formed within the first opening and the second opening. The isolation layer is not etched and removed in the process of forming the first opening and the second opening, so that the stress of the fin portion in the device region cannot be changed, and the performance of the transistor structure in the device region cannot be reduced. In addition, in the process of removing the isolation region by etching, the isolation layer is covered by the first region, so that the isolation layer can be prevented from being damaged by etching, the stress of the device region can not be changed, and the performance of the finally formed semiconductor structure is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the increase of the integration level of semiconductor devices, the critical dimensions of transistors are continuously shrinking. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doping layer in the groove by an epitaxial growth process.
In order to prevent the source-drain doped layers of different transistors from being connected with each other, an isolation layer needs to be formed in the fin portion, and meanwhile, in order to reduce the area of the isolation layer, the integration level of the formed semiconductor structure is improved. The prior art has introduced sdb (single Diffusion break) technology.
However, the SDB technology introduced in the prior art results in a semiconductor structure with poor performance.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a plurality of fin parts which are arranged in parallel along a first direction, each fin part comprises a plurality of device regions and an isolation region which is positioned between the adjacent device regions, the isolation regions and the device regions are arranged along a second direction, and the first direction is vertical to the second direction; forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part; forming a first gate structure on the substrate, wherein the first gate structure crosses over the isolation region, and the first gate structure covers part of the side wall and the top surface of the isolation region and part of the top surface of the isolation layer, the first gate structure comprises a first region and a second region, the first region is located on the isolation layer, the second region is located on the first region, and the top surface of the first region is lower than the top surface of the fin portion; forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall of the first grid structure; removing the second region, and forming an initial first opening exposing the top of the isolation region in the first dielectric layer; removing the isolation region exposed by the initial first opening, and forming a second opening in the isolation layer; after the second opening is formed, removing the first area, and forming a first opening in the first dielectric layer; and forming an isolation structure in the first opening and the second opening.
Optionally, before forming the initial first opening, the method further includes: and forming a second dielectric layer on the first dielectric layer and the first grid structure.
Optionally, after removing the first region, the method further includes: and etching back part of the isolation layer.
Optionally, the top surface of the first gate structure is lower than the top surface of the first dielectric layer.
Optionally, in the process of forming the first gate structure, the method further includes: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the device region, and the second gate structures cover partial side walls and the top surface of the device region and partial top surface of the isolation layer.
Optionally, before forming the first gate structure and the second gate structure, the method further includes: and forming a plurality of source-drain doping layers in the fin portion, wherein source-drain ions are arranged in the source-drain doping layers, and the source-drain doping layers are positioned between the adjacent second grid structures or between the adjacent first grid structures and the adjacent second grid structures.
Optionally, the source and drain ions include N-type ions or P-type ions.
Optionally, before forming the first gate structure and the second gate structure, the method further includes: and forming a first dummy gate structure and a plurality of second dummy gate structures on the substrate, wherein the first dummy gate structure crosses the isolation region, the second dummy gate structure crosses the device region, and the first dielectric layer covers the side walls of the first dummy gate structure and the second dummy gate structure.
Optionally, the method for forming the source-drain doping layer includes: etching the fin part by using the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of source-drain openings in the fin part; and forming a source drain doping layer in the source drain opening.
Optionally, the method for forming the source-drain doping layer in the source-drain opening includes: forming an epitaxial layer in the source drain opening by adopting an epitaxial growth process; and doping the source and drain ions in the epitaxial layer by adopting an in-situ doping process in the process of forming the epitaxial layer to form the source and drain doping layer.
Optionally, the method for forming the first dielectric layer includes: forming an initial first dielectric layer on the substrate, wherein the initial first dielectric layer covers the first pseudo gate structure and the second pseudo gate structure; and carrying out planarization treatment on the initial first dielectric layer until the top surfaces of the first pseudo gate structure and the second pseudo gate structure are exposed, so as to form the first dielectric layer.
Optionally, the process of performing planarization treatment on the initial first dielectric layer includes: a chemical mechanical polishing process, a wet etching process, or a dry etching process.
Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure and the second dummy gate structure, and forming a first gate opening and a second gate opening in the first dielectric layer; and forming the first gate structure in the first gate opening and forming the second gate structure in the second gate opening.
Optionally, the method for forming the isolation structure includes: forming initial isolation structures in the first opening, the second opening and the top surface of the second dielectric layer; and carrying out planarization treatment on the initial isolation structure until the top surface of the second dielectric layer is exposed, so as to form the isolation structure.
Optionally, the material of the isolation structure includes: silicon oxide or silicon nitride.
Optionally, the material of the isolation layer includes: silicon oxide or silicon nitride.
Optionally, the first gate structure includes: the gate structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer.
Optionally, the second gate structure includes: the second gate dielectric layer and a second gate layer located on the second gate dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme, a first opening is formed in the first dielectric layer by removing the first grid structure; and removing the isolation region, and forming a second opening in the first dielectric layer. Because the isolation layer is not etched and removed in the process of forming the first opening and the second opening, the stress of the fin portion in the device region cannot be changed, and further the performance of the transistor structure in the device region cannot be reduced, so that the performance of the finally formed semiconductor structure is improved. Further, the process of forming the first opening and the second opening is: removing the second area, and forming an initial first opening in the first dielectric layer; after the initial first opening is formed, removing the isolation region and forming a second opening in the isolation layer; and after the second opening is formed, removing the first region, and forming the first opening in the first dielectric layer. In the process of removing the isolation region by etching, the isolation layer is covered by the first region, so that the isolation layer can be prevented from being damaged by etching, the stress of the device region cannot be changed, and the performance of the finally formed semiconductor structure is improved.
Further, after removing the first region, the method further includes: and etching back part of the isolation layer. And partially releasing the stress in the device region by back etching part of the isolation layer so as to adjust the stress in the device region, so that the stress in the device region is more in line with the stress requirement of the transistor structure, and the performance of the finally formed semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor structure;
fig. 4 to 19 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the SDB technology introduced in the prior art results in a semiconductor structure with poor performance. The following detailed description will be made with reference to the accompanying drawings.
Referring to fig. 1 and fig. 2, fig. 1 is a top view of a semiconductor structure, fig. 2 is a schematic cross-sectional view along a direction a-a of fig. 1, a substrate 100 is provided, the substrate 100 includes a plurality of device regions a1 and an isolation region B1 located between adjacent device regions a1, the isolation region B1 and the device region a1 are arranged along a first direction X; forming a plurality of fin portions 101 arranged in parallel along a second direction Y on the device region a1, wherein the first direction X is perpendicular to the second direction Y, and the fin portions 101 further cross over the isolation region B1; forming an isolation layer 102 on the substrate 100, wherein the isolation layer 102 covers part of the sidewall of the fin 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin 101; forming a first gate structure 103 crossing the fin 101 on the isolation region B1, wherein the first gate structure 103 covers part of the side wall and the top surface of the fin 101; a dielectric layer 104 is formed on the substrate 100, and the dielectric layer 104 covers the sidewalls of the first gate structure 103.
Referring to fig. 3, the direction of fig. 3 is the same as the view direction of fig. 2, the first gate structure 103, the isolation layer 102 on the isolation region B1, and the fin 101 on the isolation region B1 are removed, and an isolation opening (not labeled) is formed in the dielectric layer 104; an isolation structure 105 is formed within the isolation opening.
In this embodiment, the isolation structure 105 is used to prevent interconnection between subsequently formed source-drain doped layers, so as to achieve an isolation effect, and the isolation structure 105 formed by removing the first gate structure 103 can effectively reduce an area occupied by a device structure, thereby improving the integration level of a semiconductor device.
In this embodiment, when the isolation opening is formed, the fin 101 located on the isolation region B1 needs to be removed, and since the etching process is limited by the aspect ratio of the etching opening in the process of removing the fin 101 on the isolation region B1 by etching, the fin 101 located on the isolation region B1 is not easily and completely removed, in this embodiment, the isolation layer located on the isolation region B1 is also removed in the process of removing the fin 101 located on the isolation region B1, so that the aspect ratio of the etching opening can be effectively increased, and the fin 101 located on the isolation region B1 can be completely removed.
However, when the isolation layer 102 on the isolation region B1 is removed, the stress of the fin 101 in the device region a1 may be changed. When PMOS transistor structures are formed in the device region a1, the fin 101 may provide a compressive stress due to the PMOS transistor structures. When the isolation layer 102 on the isolation region B1 is removed, the compressive stress of the fin 101 in the PMOS transistor structure is released partially, so that the compressive stress of the fin 101 in the PMOS transistor structure is reduced, which affects the performance of the PMOS transistor structure, and further reduces the performance of the finally formed semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a first opening in a first dielectric layer by removing a first grid structure; and removing the fin part on the isolation region, and forming a second opening in the first dielectric layer. Because the isolation layer is not etched and removed in the process of forming the first opening and the second opening, the stress of the fin portion in the device region cannot be changed, and further the performance of the transistor structure in the device region cannot be reduced, so that the performance of the finally formed semiconductor structure is improved. Further, the process of forming the first opening and the second opening is: removing the second area, and forming an initial first opening in the first dielectric layer; after the initial first opening is formed, removing the isolation region and forming a second opening in the isolation layer; and after the second opening is formed, removing the first region, and forming the first opening in the first dielectric layer. In the process of removing the isolation region by etching, the isolation layer is covered by the first region, so that the isolation layer can be prevented from being damaged by etching, the stress of the device region can not be changed, and the performance of the finally formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to fig. 19 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 4 is a top view of a semiconductor structure, fig. 5 is a schematic cross-sectional view along a direction B-B in fig. 4, a substrate 200 is provided, the substrate 200 has a plurality of fins 201 arranged in parallel along a first direction X, the fins 201 include a plurality of device regions a1 and isolation regions B1 located between adjacent device regions a1, the isolation regions B1 and the device regions a1 are arranged along a second direction Y, and the first direction X is perpendicular to the second direction Y.
In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of a top surface of the initial substrate; etching the initial substrate by using the patterning layer as a mask to form the substrate 200 and the fin portion 201; after the substrate 200 and the fin 201 are formed, the patterned layer is removed.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the fin 201 is made of silicon; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Referring to fig. 6, in the view direction of fig. 6 and fig. 5, an isolation layer 202 is formed on the substrate 200, wherein the isolation layer 202 covers a portion of the sidewall of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201.
In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200, the initial isolation layer covering sidewalls and a top of the fin 201; performing planarization treatment on the initial isolation layer until the top surface of the fin portion 201 is exposed; after the planarization treatment, part of the initial isolation layer is etched and removed to form the isolation layer 202, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.
The isolation layer 202 is made of an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.
After forming the isolation layer 202, further comprising: forming a first gate structure on the substrate 200, wherein the first gate structure crosses over the isolation region B1, and the first gate structure covers part of the sidewall and the top surface of the isolation region B1 and part of the top surface of the isolation layer 202, the first gate structure comprises a first region on the isolation layer 202 and a second region on the first region, and the top surface of the first region is lower than the top surface of the fin 201; forming second gate structures on the substrate 200, the second gate structures crossing the device region a1, and the second gate structures covering a portion of the sidewalls and the top surface of the device region a1 and a portion of the top surface of the isolation layer 202; a first dielectric layer is formed on the substrate 200, and the first dielectric layer covers sidewalls of the first gate structure and the second gate structure. Please refer to fig. 7 to fig. 13 for a specific forming process.
Referring to fig. 7 and 8, fig. 7 is a top view of a semiconductor structure, fig. 8 is a schematic cross-sectional view along C-C of fig. 7, a first dummy gate structure 203 and a plurality of second dummy gate structures 204 are formed on the substrate 200, the first dummy gate structure 203 crosses the isolation region B1, and the second dummy gate structure 204 crosses the device region a 1.
In this embodiment, the first dummy gate structure 203 includes a first dummy gate dielectric layer and a first dummy gate layer (not labeled) on the first dummy gate dielectric layer; the second dummy gate structure includes a second dummy gate dielectric layer and a second dummy gate layer (not labeled) on the second dummy gate dielectric layer.
In this embodiment, the first dummy gate dielectric layer and the second dummy gate dielectric layer are made of silicon oxide; in other embodiments, the first dummy gate dielectric layer and the second dummy gate dielectric layer may also be made of silicon oxynitride.
In this embodiment, the material of the first dummy gate layer and the second dummy gate layer is silicon.
In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 are formed at the same time, and the first dummy gate structure 203 and the second dummy gate structure 204 are formed at the same time through a global process, which can effectively improve the production efficiency.
In this embodiment, with continuing reference to fig. 7, after the first dummy gate structure 203 and the second dummy gate structure 204 are formed, a first sidewall 205 is formed on a sidewall of the first dummy gate structure 203; a second sidewall 206 is formed on the sidewall of the second dummy gate structure 204.
In this embodiment, the first sidewall 205 and the second sidewall 206 are made of silicon nitride.
Referring to fig. 9, the direction of the view in fig. 9 is the same as that of the view in fig. 7, the fin 201 is etched by using the first dummy gate structure 203 and the second dummy gate structure 204 as masks, and a plurality of source-drain openings (not labeled) are formed in the fin 201; forming a source-drain doping layer 207 in the source-drain opening, wherein source-drain ions are contained in the source-drain doping layer 207, and the source-drain doping layer 207 is located between the adjacent second dummy gate structures 204 or between the adjacent first dummy gate structure 203 and the second dummy gate structure 204.
The source and drain ions comprise N-type ions or P-type ions. In this embodiment, the source and drain ions are P-type ions.
In this embodiment, the method for forming the source-drain doping layer 207 in the source-drain opening includes: forming an epitaxial layer (not shown) in the source and drain openings by using an epitaxial growth process; and doping the source and drain ions in the epitaxial layer by adopting an in-situ doping process in the process of forming the epitaxial layer to form the source and drain doping layer 207.
Referring to fig. 10, after forming the source-drain doping layer 207, forming an initial first dielectric layer (not shown) on the substrate 200, where the initial first dielectric layer covers the first dummy gate structure 203 and the second dummy gate structure 204; and performing planarization treatment on the initial first dielectric layer until the top surfaces of the first dummy gate structure 203 and the second dummy gate structure 204 are exposed, so as to form the first dielectric layer 208.
In this embodiment, the first dielectric layer 208 is made of silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).
In this embodiment, the process of performing the planarization process on the initial first dielectric layer adopts a chemical mechanical polishing process. In other embodiments, the process of performing planarization treatment on the initial first dielectric layer may also adopt a wet etching process or a dry etching process.
Referring to fig. 11 to 13, fig. 11 is a top view of a semiconductor structure, fig. 12 is a schematic cross-sectional view along a direction D-D of fig. 11, fig. 13 is a schematic cross-sectional view along a direction E-E of fig. 11, after forming the first dielectric layer 208, the first dummy gate structure 203 and the second dummy gate structure 204 are removed, and a first gate opening and a second gate opening (not labeled) are formed in the first dielectric layer 208; forming the first gate structure 209 in the first gate opening, wherein the first gate structure 209 crosses over the isolation region B1, and the first gate structure 209 covers a portion of the sidewall and the top surface of the isolation region B1 and a portion of the top surface of the isolation layer 202, wherein the first gate structure 209 includes a first region I located on the isolation layer 202 and a second region II located on the first region I, and the top surface of the first region I is lower than the top surface of the fin 201; the second gate structure 210 is formed within the second gate opening, the second gate structure 210 crosses the device region a1, and the second gate structure 210 covers a portion of the sidewalls and the top surface of the device region a1 and a portion of the top surface of the isolation layer 202.
In this embodiment, the top surfaces of the first gate structure 209 and the second gate structure 210 are lower than the top surface of the first dielectric layer 208.
In this embodiment, the first gate structure 209 includes: a first gate dielectric layer and a first gate layer (not labeled) on the first gate dielectric layer; the second gate structure 210 includes: a second gate dielectric layer and a second gate layer (not labeled) on the second gate dielectric layer.
In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-K dielectric material.
The material of the first gate layer and the second gate layer comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the first gate layer and the second gate layer is tungsten.
Referring to fig. 14, the view directions of fig. 14 and fig. 12 are the same, and after the first gate structure 209 and the second gate structure 210 are formed, a second dielectric layer 211 is formed on the first dielectric layer 208, the first gate structure 209 and the second gate structure 210.
In this embodiment, the second dielectric layer 211 is made of silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-K dielectric material or an ultra-low-K dielectric material.
Referring to fig. 15, fig. 15 and fig. 13, after forming the second dielectric layer 211, the second region II is removed, and an initial first opening 212 exposing the top of the isolation region B1 is formed in the first dielectric layer 208.
In this embodiment, the second zone II is removed first, and the first zone I is reserved, so as to: the isolation layer 202 is protected by the first region I, so that the isolation layer 202 is prevented from being damaged when the isolation region B1 is subsequently removed, and further, the stress of the device region a1 is not changed, thereby improving the performance of the finally formed semiconductor structure.
In this embodiment, the process of removing the second region II adopts a dry etching process; in other embodiments, the process of removing the second region may also adopt a wet etching process.
Referring to fig. 16, the isolation region B1 exposed by the initial first opening 212 is removed, and a second opening 213 is formed in the isolation layer 202.
In the present embodiment, since the material of the first region I and the material of the isolation region B1 are remained with a larger etching selectivity ratio, the isolation region B1 may be removed by a self-aligned process.
In this embodiment, the process of removing the isolation region B1 adopts a dry etching process; in other embodiments, the process of removing the isolation region may also adopt a wet etching process.
Referring to fig. 17, after the second opening 213 is formed, the first region I is removed, and a first opening 214 is formed in the first dielectric layer 208.
In the present embodiment, a first opening 214 is formed in the first dielectric layer 208 by removing the first gate structure 209; the isolation region B1 is removed and a second opening 213 is formed in the first dielectric layer 208. Since the isolation layer 202 is not etched away during the process of forming the first opening 213 and the second opening 214, the stress of the fin 201 in the device region a1 is not changed, and the performance of the transistor structure in the device region a1 is not reduced, thereby improving the performance of the finally formed semiconductor structure.
In this embodiment, the process for removing the first region I adopts a dry etching process; in other embodiments, the process of removing the first region may also adopt a wet etching process.
Referring to fig. 18, after removing the first region I, the method further includes: portions of the isolation layer 202 are etched back.
In this embodiment, the stress in the device region a1 is partially released by etching back a portion of the isolation layer 202, so as to adjust the stress in the device region a1 to better meet the stress requirement of the transistor structure, thereby improving the performance of the finally formed semiconductor structure.
Referring to fig. 19, after the first opening 213 and the second opening 214 are formed, an isolation structure 215 is formed in the first opening 213 and the second opening 214.
In this embodiment, the isolation structure 215 is used to prevent the source-drain doping layers 207 formed subsequently from being connected to each other, so as to achieve an isolation effect, and the area occupied by the device structure can be effectively reduced by removing the first gate structure 209 to form the isolation structure 215, thereby improving the integration level of the semiconductor device.
In this embodiment, the method for forming the isolation structure 215 includes: forming initial isolation structures (not shown) within the first opening 213 and the second opening 214, and a top surface of the second dielectric layer 211; and performing planarization treatment on the initial isolation structure until the top surface of the second dielectric layer 211 is exposed, so as to form the isolation structure 215.
The material of the isolation structure 215 includes: silicon oxide or silicon nitride. In this embodiment, the isolation structure 215 is made of silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of fin parts which are arranged in parallel along a first direction, each fin part comprises a plurality of device regions and an isolation region which is positioned between the adjacent device regions, the isolation regions and the device regions are arranged along a second direction, and the first direction is vertical to the second direction;
forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part;
forming a first gate structure on the substrate, wherein the first gate structure crosses over the isolation region, and the first gate structure covers part of the side wall and the top surface of the isolation region and part of the top surface of the isolation layer, the first gate structure comprises a first region and a second region, the first region is located on the isolation layer, the second region is located on the first region, and the top surface of the first region is lower than the top surface of the fin portion;
forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the side wall of the first grid structure;
removing the second region, and forming an initial first opening exposing the top of the isolation region in the first dielectric layer;
removing the isolation region exposed by the initial first opening, and forming a second opening in the isolation layer;
after the second opening is formed, removing the first area, and forming a first opening in the first dielectric layer;
and forming an isolation structure in the first opening and the second opening.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the initial first opening: and forming a second dielectric layer on the first dielectric layer and the first grid structure.
3. The method of forming a semiconductor structure of claim 1, further comprising, after removing the first region: and etching back part of the isolation layer.
4. The method of forming a semiconductor structure of claim 1, wherein a top surface of the first gate structure is lower than a top surface of the first dielectric layer.
5. The method of forming a semiconductor structure of claim 1, further comprising, during the forming of the first gate structure: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the device region, and the second gate structures cover partial side walls and the top surface of the device region and partial top surface of the isolation layer.
6. The method of forming a semiconductor structure of claim 5, further comprising, prior to forming the first gate structure and the second gate structure: and forming a plurality of source-drain doping layers in the fin portion, wherein source-drain ions are arranged in the source-drain doping layers, and the source-drain doping layers are positioned between the adjacent second grid structures or between the adjacent first grid structures and the adjacent second grid structures.
7. The method for forming a semiconductor structure according to claim 6, wherein the source and drain ions include N-type ions or P-type ions.
8. The method of forming a semiconductor structure of claim 6, further comprising, prior to forming the first gate structure and the second gate structure: and forming a first dummy gate structure and a plurality of second dummy gate structures on the substrate, wherein the first dummy gate structure crosses the isolation region, the second dummy gate structure crosses the device region, and the first dielectric layer covers the side walls of the first dummy gate structure and the second dummy gate structure.
9. The method for forming the semiconductor structure according to claim 8, wherein the method for forming the source-drain doping layer comprises the following steps: etching the fin part by using the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of source-drain openings in the fin part; and forming a source drain doping layer in the source drain opening.
10. The method for forming a semiconductor structure according to claim 9, wherein the step of forming the source and drain doping layer in the source and drain opening comprises: forming an epitaxial layer in the source drain opening by adopting an epitaxial growth process; and doping the source and drain ions in the epitaxial layer by adopting an in-situ doping process in the process of forming the epitaxial layer to form the source and drain doping layer.
11. The method of forming a semiconductor structure of claim 8, wherein the method of forming the first dielectric layer comprises: forming an initial first dielectric layer on the substrate, wherein the initial first dielectric layer covers the first pseudo gate structure and the second pseudo gate structure; and carrying out planarization treatment on the initial first dielectric layer until the top surfaces of the first pseudo gate structure and the second pseudo gate structure are exposed, so as to form the first dielectric layer.
12. The method of forming a semiconductor structure of claim 8, wherein planarizing the initial first dielectric layer comprises: a chemical mechanical polishing process, a wet etching process, or a dry etching process.
13. The method of forming the semiconductor structure of claim 8, wherein the method of forming the first gate structure and the second gate structure comprises: removing the first dummy gate structure and the second dummy gate structure, and forming a first gate opening and a second gate opening in the first dielectric layer; and forming the first gate structure in the first gate opening and forming the second gate structure in the second gate opening.
14. The method of forming a semiconductor structure of claim 2, wherein the method of forming an isolation structure comprises: forming initial isolation structures in the first opening, the second opening and the top surface of the second dielectric layer; and carrying out planarization treatment on the initial isolation structure until the top surface of the second dielectric layer is exposed, so as to form the isolation structure.
15. The method of forming a semiconductor structure of claim 1, wherein the isolation structure comprises a material comprising: silicon oxide or silicon nitride.
16. The method of forming a semiconductor structure of claim 1, wherein the isolation layer comprises a material comprising: silicon oxide or silicon nitride.
17. The method of forming a semiconductor structure of claim 1, wherein the first gate structure comprises: the gate structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer.
18. The method of forming a semiconductor structure of claim 5, wherein the second gate structure comprises: the second gate dielectric layer and a second gate layer located on the second gate dielectric layer.
CN202011323065.1A 2020-11-23 2020-11-23 Method for forming semiconductor structure Pending CN114530379A (en)

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