KR101466846B1 - Mos transistor and method for forming the same - Google Patents

Mos transistor and method for forming the same Download PDF

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KR101466846B1
KR101466846B1 KR1020130055017A KR20130055017A KR101466846B1 KR 101466846 B1 KR101466846 B1 KR 101466846B1 KR 1020130055017 A KR1020130055017 A KR 1020130055017A KR 20130055017 A KR20130055017 A KR 20130055017A KR 101466846 B1 KR101466846 B1 KR 101466846B1
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gate electrode
electrode structure
dummy gate
source region
region
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KR1020130055017A
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Korean (ko)
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KR20140043019A (en
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구오하오 차오
시안용 푸
종샨 홍
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세미컨덕터 매뉴팩춰링 인터내셔널 (상하이) 코포레이션
세미컨덕터 매뉴팩춰링 인터내셔널 (베이징) 코포레이션
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Abstract

The present invention relates to a MOS transistor and a method of forming the same. A method of forming a MOS transistor, comprising: providing a semiconductor substrate having an active region and a cellrow trench isolation structure surrounding the active region; Forming a gate electrode structure on a surface of the active region and forming a dummy gate electrode structure on a surface of the cellrow trench isolation structure; Forming a source region and a drain region in active regions on both sides of the gate electrode structure; Forming an interconnect layer on the surface of the source region, the surface of the drain region, and at least a portion of the top surface of the dummy gate electrode structure, such that the source region or the drain region is electrically connected to the dummy gate electrode structure. Since the conductive plug is not formed directly on the surface of the source region and the drain region, the exposed width of the source region and the drain region can be relatively narrow, and the dummy gate electrode structure is located on the surface of the cellrow trench isolation structure, The additional chip area is not occupied and the chip area occupied by the finally formed MOS transistor is reduced, which is advantageous for improving the integration degree of the chip.

Description

[0001] MOS TRANSISTOR AND METHOD FOR FORMING THE SAME [0002]

The present invention relates to a semiconductor technology, and more particularly, to a MOS transistor having a relatively small area occupied by a chip area and a method of forming the MOS transistor.

With the continuous development of integrated circuit manufacturing technology, the size of MOS transistors is becoming smaller and smaller. According to the ratio reduction rule, when the total size of the MOS transistor is reduced, the sizes of the structures of the source electrode, the drain electrode, the gate electrode, the conductive plug, and the like are also reduced at the same time. 1, a semiconductor device includes a semiconductor substrate 10, an active region 11 located in the semiconductor substrate 10, an active region 11 located within the semiconductor substrate 10, A gate electrode structure 20 located on the surface of the active region 11 and a source region 20 located within the active region 11 on both sides of the gate electrode structure 20. The cell row trench isolation structure 12 surrounds the active region 11, A first metal silicide 30 located on a surface of the source region 13; a second metal silicide 40 located on a surface of the drain region 14; A first conductive plug 35 located on the surface of the first metal silicide 30 and a second conductive plug 45 located on the surface of the second metal silicide 40. Since the first conductive plug 35 is located on the source region 13 and the second conductive plug 45 is located on the drain region 14, The width S1 must be at least larger than the diameter of the first conductive plug 35 and the second conductive plug 45. [ However, due to the limitations of the semiconductor manufacturing process, the size of the conductive plug formed by the present process is relatively large, so that the width of the conventional source and drain regions is also relatively large, which makes it difficult to reduce the overall size of the MOS transistor.

For further details regarding MOS transistors and their formation methods, please refer to U.S. Patent No. US2009 / 0079013A1.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOS transistor and a method of forming the same to form an interconnect layer between a dummy gate electrode structure and a gate electrode / source electrode on a cellrow trench isolation structure, Thereby forming a MOS transistor.

In order to solve the above problems, the technical solution of the present invention includes: providing a semiconductor substrate having an active region and a cellrow trench isolation structure surrounding the active region; Forming a gate electrode structure on a surface of the active region and forming a dummy gate electrode structure on a surface of the cellrow trench isolation structure; Forming a source region and a drain region in active regions on both sides of the gate electrode structure; Forming an interconnect layer on the surface of the source region, the surface of the drain region, and at least a portion of the top surface of the dummy gate electrode structure, wherein the interconnect layer of the surface of the source region is adjacent The interconnect layer of the top surface of the dummy gate electrode structure being interconnected with the interconnect layer of the top surface of the dummy gate electrode structure to form a first interconnect layer, To form a second interconnect layer.

The interconnection layer is preferably a metal layer, a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion.

Forming a first sidewall at a sidewall of the gate electrode structure and forming a second sidewall at a sidewall of the dummy gate electrode structure.

Before forming the interconnect layer, it is preferable to remove the second side wails on both sides of the dummy gate electrode structure.

Removing the second side wally adjacent one side of the source region or the drain region of the dummy gate electrode structure prior to forming the interconnect layer.

When the interconnection layer is a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion, the surface of the source region and the surface of the drain region, It is preferable to form an interconnect layer on the sidewall surface and at least a part of the upper surface adjacent to one side of the source region or the drain region of the dummy gate electrode structure.

When the interconnect layer is a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion, the surface of the source region, the surface of the drain region, It is preferable to form an interconnect layer on the sidewall surface and the upper surface of the dummy gate electrode structure.

Preferably, the dummy gate electrode structure is completely located on the surface of the cellrow trench isolation structure.

The thickness of the interconnect layer formed using the epitaxial process may vary depending on the thickness of the dummy gate electrode structure when the sidewall adjacent to one side of the source region or the drain region of the dummy gate electrode structure and the edge of the corresponding cellrow trench isolation structure are spaced apart from each other. The gap between the sidewall adjacent to one side of the source region or drain region of the gate electrode structure and the edge of the corresponding cellrow trench isolation structure.

It is preferable that the dummy gate electrode structure located on the surface of the cellrow trench isolation structure is connected to other MOS transistors with an interconnect structure.

It is preferable that a conductive plug is formed on the dummy gate electrode structure and the source region and the drain region are connected to the external circuit through the interconnect layer and the conductive plug.

Preferably, a portion of the dummy gate electrode structure is located on a surface of the cellrow trench isolation structure, and a portion is located on a surface of a corresponding active region.

The gate electrode structure and the dummy gate electrode structure are preferably formed simultaneously in the same forming process.

The first sidewall and the second sidewall are preferably formed simultaneously in the same forming process.

A semiconductor device comprising: a semiconductor substrate; An active region located within the semiconductor substrate; a cellrow trench isolation structure surrounding the active region located within the semiconductor substrate; A gate electrode structure located on a surface of the active region, a dummy gate electrode structure located on a surface of the cellrow trench isolation structure, A source region and a drain region located in active regions on both sides of the gate electrode structure; A first interconnect layer located on a top surface of the dummy gate electrode structure adjacent a surface and source region of the source region, a second interconnect layer located on a top surface of the dummy gate electrode structure adjacent the surface and drain regions of the drain region, Further comprising a MOS transistor including an interconnect layer.

The interconnection layer is preferably a metal layer, a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion.

Further comprising a second sidewill located at a side remote from a source region or a drain region of the dummy gate electrode structure, wherein a surface of the source region, a top surface of the dummy gate electrode structure adjacent the source region, It is preferable that the first interconnecting layer is formed on the sidewall surface close to the source region of the gate electrode.

It is preferable that a first interconnect layer is formed on the surface of the source region and on the top and sidewall surfaces of the dummy gate electrode structure adjacent to the source region.

Preferably, the dummy gate electrode structure is completely located on the surface of the cellrow trench isolation structure.

When the sidewalls adjacent to one side of the source region or the drain region of the dummy gate electrode structure and the edges of the corresponding cell row trench isolation structure are spaced at a certain distance, the thickness of the interconnection layer formed using the epitaxial process is smaller than the thickness of the dummy gate Is preferably larger than the spacing between the sidewall adjacent to one side of the source region or the drain region of the electrode structure and the edge of the corresponding cellrow trench isolation structure.

It is preferable that the dummy gate electrode structure located on the surface of the cellrow trench isolation structure is connected to other MOS transistors with an interconnect structure.

The conductive plug located on the dummy gate electrode structure preferably connects the source region and the drain region with an external circuit through the interconnect layer and the conductive plug.

Preferably, a portion of the dummy gate electrode structure is located on a surface of the cellrow trench isolation structure, and a portion is located on a surface of a corresponding active region.

Compared with the prior art, the present invention has the following advantages.

In an embodiment of the present invention, the surface of the cell trench isolation structure is formed into a dummy gate electrode structure, and a surface of the source region, a surface of the drain region, at least a part of the upper surface of the dummy gate structure, Region, and drain region are electrically connected to the dummy gate electrode structure. The exposed width of the source region and the drain region can be narrowed because the conductive plug is not formed directly on the surface of the source region and the drain region and the dummy gate electrode structure is located on the surface of the cellrow trench isolation structure, The area occupied by the finally formed MOS transistor is reduced and the integration degree of the chip is advantageously improved.

Further, when the dummy gate electrode structure is completely located on the surface of the cell trench isolation structure, when the dummy gate electrode structure located on the surface of the cell trench isolation structure is connected to other MOS transistors with an interconnect structure, Layer is added, which is advantageous for improving the wiring density and the wiring selectivity.

1 is a schematic structural view of a conventional MOS transistor.
2 to 10 are schematic cross-sectional views illustrating a process of forming a MOS transistor according to an embodiment of the present invention.

In the conventional technique, a conductive plug is generally formed on the surface of the source region and the drain region, and the source region and the drain region are connected to the external circuit by using the conductive plug. However, since the size of the conductive plug formed by the present process is relatively large due to the limitation of the semiconductor manufacturing process at present, the width of the conventional source region and the drain region is also relatively large and the reduction of the overall size of the MOS transistor There is a difficult problem.

Accordingly, the present invention provides a MOS transistor and a method of forming the same, and a dummy gate electrode structure is formed on a surface of a cell row trench isolation structure (STI) close to the source region or the drain region, Forming a first interconnect layer on the upper surface of the dummy gate electrode structure adjacent to the surface and drain regions of the source region and forming a second interconnect on the upper surface of the dummy gate electrode structure adjacent the surface and drain regions of the drain region, Layer is formed so as to form a conductive plug on the dummy gate electrode structure subsequently, or the dummy gate electrode structure is made to have an interconnect structure in which different MOS transistors are connected. Since the semiconductor structure is not formed on the surface of the cell trench isolation structure in the conventional process and the chip area is wasted, the dummy gate electrode structure is formed on the surface of the cell trench isolation structure in the embodiment of the present invention, The source region, the drain region and the dummy gate electrode structure are electrically connected by using the connection layer and the second mutual contact layer, and the source region and the drain region of the MOS transistor are connected to the external circuit by using the dummy gate electrode structure. It is not necessary to directly form the conductive plug on the surface of the source region or the drain region. Therefore, the width of the source region and the drain region can be reduced, which is advantageous in reducing the chip area occupied by the MOS transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. And can be similarly modified and modified. Therefore, the present invention is not limited to the specific embodiments disclosed below.

2 to 10 are schematic cross-sectional views illustrating a process of forming a MOS transistor according to an embodiment of the present invention.

2, a semiconductor substrate 100 is provided, and an active region 101 and a cell row trench isolation structure 102 surrounding the active region 101 are formed in the semiconductor substrate 100. Referring to FIG. do.

The semiconductor substrate 100 includes one of a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. In this embodiment, the semiconductor substrate 100 is a silicon substrate.

In this embodiment, a well region is first formed in the active region 101 using an ion implantation process, and then the semiconductor substrate 100 around the well region is etched to form a cellrow trench that surrounds the active region 101 And the cellrow trenches are filled with silicon oxide to form a cellrow trench isolation structure 102. In other embodiments, an extrinsic semiconductor substrate may be used directly as the active region. The formation of the active region, cellrow trench isolation structure, is well known to those skilled in the art and will not be described in detail here.

3, a gate electrode structure 110 is formed on a surface of the active region 101, a dummy gate electrode structure 120 is formed on a surface of the cellrow trench isolation structure 102, The structure 120 is completely located on the surface of the cellrow trench isolation structure 102.

A specific process for forming the gate electrode structure 110 and the dummy gate electrode structure 120 includes forming a gate dielectric material layer (not shown) on the surface of the semiconductor substrate 100, Forming a hard mask material layer (not shown) on the surface of the polycrystalline silicon material layer, forming a photoresist layer (not shown) on the surface of the hard mask material layer Exposing and developing the photoresist layer to form a photoresist pattern, using the photoresist pattern as a mask to etch the hard mask material layer, the polycrystalline silicon material layer, the gate dielectric material layer The gate electrode structure 110 located on the surface of the active region 101 and the gate electrode structure 110 located on the surface of the cellrow trench isolation structure 102 And forming a non-gate electrode structure 120. The gate electrode structure 110 includes a first gate dielectric layer 111 and a first gate electrode 112 located on the surface of the first gate dielectric layer 111, The first hard mask layer 113 is formed on the first hard mask layer 113. [ The dummy gate electrode structure 120 includes a second gate dielectric layer 121 and a second gate electrode 122 located on the surface of the second gate dielectric layer 121, And a second hard mask layer 123 on the upper surface.

In this embodiment, the gate electrode 110 and the dummy gate electrode structure 120 are formed using the same deposition and etching process, and the materials of the gate electrode structure 110 and the dummy gate electrode structure 120 The same, reducing the process steps and lowering the process cost. In another embodiment, the gate electrode structure and the dummy gate electrode structure may be respectively formed.

In another embodiment, etching is performed on the polycrystalline silicon material layer, the gate dielectric material layer using the patterned photoresist layer, without forming the first hard mask layer and the second hard mask layer, A dummy gate electrode structure may be formed.

The dummy gate electrode structure 120 is completely located on the surface of the cellrow trench isolation structure 102 and between the sidewall of the dummy gate electrode structure 120 and the edge of the cellrow trench isolation structure 102. In this embodiment, There is no direct contact between the dummy gate electrode structure 120 and the active region. The dummy gate electrode structure 120 and the active region are not in direct contact with each other when the dummy gate electrode structure 120 on the surface of the cellrow trench isolation structure 120 is used as an interconnect structure in a subsequent process, A punchthrough occurs between the second gate electrode 122 and the active region 101 of the second transistor 120 due to the second gate dielectric layer 121 to prevent a short circuit.

In another embodiment, the dummy gate electrode structure is located on the surface of the cellrow trench isolation structure, and the sidewall of the dummy gate electrode structure adjacent to one side of the gate electrode structure may be aligned with the edge of the cellrow trench isolation structure.

In other embodiments, the dummy gate electrode structure may be located partially on the surface of the cellrow trench isolation structure and partially on the surface of the source region or drain region close to the cellrow trench isolation structure. Since the size of the conductive plug formed through the present process is relatively large and the width of the dummy gate electrode structure required is relatively large when the conductive plug is formed in the dummy gate electrode structure in the subsequent process, the width of the required cell row trench isolation structure It is relatively large. When the dummy gate electrode structure is provided across the cellrow trench isolation structure and the surface of the source region or drain region adjacent thereto to reduce the width of the cell trench isolation structure and reduce the overall size of the MOS transistor, The width of the cell row trench isolation structure covered by the structure becomes smaller, and the total width of the required cell row trench isolation structure becomes smaller, so that the overall size of the MOS transistor can be reduced.

In this embodiment, the dummy gate electrode structure 120 is located only on the surface of the cell row trench isolation structure 102, which is parallel to the gate electrode structure 110. The dummy gate electrode structure may be formed on the surface of the cell row trench isolation structure perpendicular to the gate electrode structure when different MOS transistors are connected with the dummy gate electrode structure as an interconnect layer, And the gate electrode structure are not connected to each other.

Referring to FIG. 4, a first sidewall 115 is formed on a sidewall of the gate electrode structure 110, a second sidewall 125 is formed on a sidewall of the dummy gate electrode structure 120, A portion of the active region 101 is exposed between the first side wed 115 and the second side wed 125.

A specific process for forming the first side wed 115 and the second side wed 125 is as follows.

A dielectric layer (not shown) is formed on the surfaces of the semiconductor substrate 100, the cell trench isolation structure 102, the gate electrode structure 110 and the dummy gate electrode structure 120, The surface of the cell row trench isolation structure 102, the surface of the first hard mask layer 113 over the gate electrode structure 110 and the surface of the second hard mask layer (upper surface) of the dummy gate electrode structure 120 120 are etched back until a surface of the dummy gate electrode structure 120 is exposed to form a first sidewall 115 on the sidewall of the gate electrode structure 110 and a second sidewall 115 on the sidewall of the dummy gate electrode structure 120, Will 125 is formed. The dielectric layer is a laminated structure of one or more layers of a silicon oxide layer, a silicon nitride layer, and a silicon nitride oxide layer. Since the material of the dielectric layer is different from the material of the first hard mask layer and the second hard mask layer, when the dielectric layer is etched, the first hard mask layer and the second hard mask layer are used to form an etch stop layer, Thereby preventing the gate electrode structure from being damaged. It is only necessary to connect the source region and the drain region with the dummy gate electrode structure through the interconnection layer in the subsequent process so that a portion of the active region 101 exposed between the first side wil 115 and the second side wil 125 Or the width of the active region 101 between the first side wed 115 and the edge of the cell row trench isolation structure 120 closest thereto does not need to be very large and the width of the conductive plug It may be small. That is, smaller than the width of the conventional source region or the drain region, which is advantageous in reducing the overall size of the MOS transistor.

Referring to FIG. 5, a source region 130 and a drain region 140 are formed in the active region 101 exposed on both sides of the gate electrode structure 110.

In this embodiment, the gate electrode structure 110, the dummy gate electrode structure 120, the first sidewall 115, and the second sidewall 125 are used as masks, and the first sidewall 115, The P-type or N-type ion implantation is performed on the active region 101 exposed between the second side wails 125 and the annealing process is performed to form the source region 130 and the drain region 140.

In other embodiments, ion implantation is performed at a low concentration in the active region on both sides of the gate electrode structure prior to forming the first sidewill and the second sidewall to form the first sidewall and the second sidewall, Implanting ions at a high concentration in an active region exposed on both sides of the first side wirings and the second side wirings to form a source region and a drain region, and the low concentration ion implantation process is performed by hot carrier injection Effect and short channel effect can be reduced.

In another embodiment, etching is also performed on the active area exposed between the first sidewall and the second sidewall using the gate electrode structure, the dummy gate electrode structure, the first sidewall, the second sidewall as a mask To form a trench and to fill the trench with a silicon germanium material or a silicon carbide material using an epitaxy process to form a source region and a drain region. The silicon germanium material or silicon carbide material is in-situ doped with P-type or N-type impurity ions in an epitaxial process. In other embodiments, after forming the silicon germanium material or silicon carbide material, the silicon germanium material or the silicon carbide material may be doped with an impurity ion using an ion implantation process. When the source region and the drain region are formed using the silicon germanium material or the silicon carbide material, a stress action is generated with respect to the crystal lattice of the MOS transistor channel region. Therefore, the carrier movement speed of the channel region and the electrical performance of the MOS transistor are improved It is advantageous.

6, a mask layer 150 is formed on the surfaces of the semiconductor substrate 100, the gate electrode structure 110, the dummy gate electrode structure 120, and the first sidewall 115, The gate electrode structure 150 is formed on the surface of the source region 130, the surface of the drain region 140, a part of the upper surface of the dummy gate electrode structure 120, and the gate electrode structure 110 of the dummy gate electrode structure 120, 2 side wirings 125 adjacent to one side of the gate electrode structure 110 of the dummy gate electrode structure 120 are exposed using the mask layer 150 as a mask, 125 and the exposed portion of the second hard mask layer 123 located on the upper surface of the dummy gate electrode structure 120.

The process of removing the second side-walls 125 and the second hard mask layer 123 is a wet etching process.

In this embodiment, the interconnect layer formed in the subsequent process is formed using a selective epitaxy process, and the selective epitaxy process is performed only on the surface of the semiconductor material such as polycrystalline silicon, monocrystalline silicon, silicon germanium, And can not be formed on the surface of the dielectric layer such as silicon oxide or silicon nitride. In order to connect the interconnection layer formed on the dummy gate electrode structure and the interconnection layer formed on the surface of the source region or the drain region, a second side well (not shown) near one side of the gate electrode structure 110 of the dummy gate electrode structure 120 The interconnect layer of the surface of the dummy gate electrode structure 120, the sidewall surface of the dummy gate electrode structure 120, the surface of the source region 130 or the drain region 140 is electrically connected So that the source region 130 or the drain region 140 is electrically connected to the adjacent dummy gate electrode structure 120.

In another embodiment, the mask layer exposes the entire upper surface of the dummy gate electrode structure, removes the second hard mask layer, and then forms an interconnect layer on the entire upper surface of the dummy gate electrode structure, The surface may be flattened when the conductive plug is formed in the dummy gate electrode structure.

In another embodiment, the mask layer exposes the entire upper surface of the dummy gate electrode structure and the second side wirings on both sides, and after removing the second hard mask layer and the second side wirings on both sides, By forming interconnecting layers on the upper surface and the sidewall surfaces of both sides, the surface can be flattened when the conductive plug is formed in the dummy gate electrode structure in a subsequent step.

7, a surface of the source region 130 exposed by the mask layer 150, a surface of the drain region 140, a portion of the upper surface of the dummy gate electrode structure 120, An interconnect layer is formed on the sidewall surface adjacent to the source region 130 or the drain region 140 of the gate electrode structure 120.

In this embodiment, the material of the interconnect layer formed using the epitaxy process is a semiconductor material such as silicon, silicon germanium or silicon carbide doped with N-type or P-type impurity ions, and the N-type or P- Semiconductor materials such as doped silicon, silicon germanium or silicon carbide have good conductivity and relatively low on-resistance so that the source region 130 or the drain region 140 is electrically connected to the adjacent dummy gate electrode structure 120 . An interconnect layer on the surface of the source region 130, an interconnect layer on the sidewall surface near one side of the source region 130 of the dummy gate electrode structure 120 adjacent to the source region 130, The interconnect layer on the top surface of the dummy gate electrode structure 120 constituting the first interconnect layer 160 and the interconnect layer on the surface of the drain region 140, The interconnect layer of the sidewall surface adjacent to one side of the drain region 140 of the electrode structure 120 and the interconnect layer of the top surface of the dummy gate electrode structure 120 adjacent to the drain region 140 are formed by a second interconnect layer 170 are formed.

In this embodiment, the impurity ions are in-situ doped into the interconnect layer through an epitaxial process. In other embodiments, after forming the interconnect layer, an impurity ion is doped into the interconnect layer using an ion implantation process.

When the material of the interconnection layer is silicon germanium or silicon carbide, the interconnection layer formed on the surfaces of the source region and the drain region generates a stress acting on the semiconductor substrate, thereby improving the carrier moving speed of the MOS transistor channel region And is advantageous for improving the electrical performance of the MOS transistor.

The interconnect layer is formed on the surface of the exposed source region 130, the drain region 140 and the dummy gate electrode structure 120 using the mask layer 150 as a mask, The layer 150 is removed. In other embodiments, the mask layer may be removed first, and an interconnect layer may be formed on the exposed top surface and sidewall surfaces of the exposed source, drain, and dummy gate electrode structures. The upper surface of the gate electrode structure has a first hard mask layer in the region covered by the mask layer and the upper surface of the dummy gate electrode structure has the second hard mask layer in the region covered by the mask layer, An interconnect layer formed by an epitaxial process must be formed on the source region, the drain region, the upper portion of the dummy gate electrode structure, and the side wall surface.

In other embodiments, metal interconnect layers may be formed on the source, drain, and dummy gate electrode structures and on the sidewall surfaces using a sputtering process, a physical vapor deposition process, or a chemical vapor deposition process, And the dummy gate electrode structure adjacent thereto may be electrically connected. Wherein the second side wirings are not removed and the upper surface of the dummy gate electrode structure, the second side wirings surface adjacent to the gate electrode structure, and the source and drain regions on the surface of the source region and the drain region, An interconnect layer may be formed to electrically connect the source region and the drain region with the dummy gate electrode structure adjacent thereto.

Referring to FIG. 8, the mask layer 150 (see FIG. 7), the first hard mask layer 113 (see FIG. 7) and the second hard mask layer 123 (see FIG.

A specific process for removing the mask layer 150, the first hard mask layer 113, and the second hard mask layer 123 is a wet etching process or a dry etching process. Those skilled in the art will appreciate that different etching processes may be rationally selected depending on the material of the mask layer 150, the first hardmask layer 113 and the second hardmask layer 123 so that the mask layer, 2 hard mask layer, while at the same time avoiding damage to the interconnect layer and the first sidewall and the second sidewall. The materials of the different mask layers, the first hardmask layer and the second hardmask layer correspond to different etching processes, and therefore will not be described in detail here.

9, a metal silicide layer 180 is formed on the surfaces of the gate electrode structure 110, the dummy gate electrode structure 120, the first interconnect layer 160, and the second interconnect layer 170 do.

The material of the metal silicide layer 180 is nickel silicide, titanium silicide, or tungsten silicide. In this embodiment, the material of the metal silicide layer 180 is nickel silicide. The method for forming the metal silicide layer 180 includes forming a semiconductor substrate 100, a gate electrode structure 110, a dummy gate electrode structure 120, a first interconnect layer 160, a second interconnect layer 170 Forming a nickel metal layer (not shown) on the surface of the gate electrode structure 110, the dummy gate electrode structure 120, the first interconnect layer 160, and the second interconnect Reacting with the semiconductor material in contact with each other in the contact layer 170 to form a nickel silicide that forms the metal silicide layer 180, and removing the unreacted nickel metal layer using wet etching.

In this embodiment, a conductive plug is formed in the gate electrode structure 110 and the dummy gate electrode structure 120 in a subsequent process, and the interlayer interconnect layer is formed in the source region or the drain region of the MOS transistor The contact resistance can be reduced by forming the metal silicide layer 180 on the gate electrode structure 110 and the dummy gate electrode structure 120 to improve the electrical performance of the MOS transistor.

10, an interlayer dielectric layer 190 is formed on the surface of the semiconductor substrate 100, a conductive plug 195 penetrating the interlayer dielectric layer 190 is formed in the interlayer dielectric layer 190, The plug 195 is located on the surface of the metal silicide layer 180 on the gate electrode structure 110, the surface of the metal silicide layer 180 on the dummy gate electrode structure 12.

The conductive plug 195 connected to the source region 130 is located on the dummy gate electrode structure 120 adjacent to the source region 130 and the conductive plug 195 connected to the drain region 140 is connected to the drain region The source region 130 and the drain region 140 are formed directly on the dummy gate electrode structure 120 adjacent to the source region 130 and the drain region 140. Therefore, And the dummy gate electrode structure 120 is located on the surface of the cell row trench isolation structure 102, so that it does not occupy an additional chip area, so that the finally formed MOS transistor occupies The chip area is reduced.

In another embodiment, the source region or the drain region of different MOS transistors may be connected to each other by using the dummy gate electrode structure as an interconnect layer without forming a conductive plug on the dummy gate electrode structure, Which is advantageous for improving the wiring density and the wiring selectivity.

According to the above forming method, the embodiment of the present invention further provides a MOS transistor. 10, the MOS transistor includes a semiconductor substrate 100; An active region 101 located within the semiconductor substrate 100; a cellrow trench isolation structure 102 surrounding the active region 101 within the semiconductor substrate 100; A gate electrode structure 110 located on the surface of the active region 101; a dummy gate electrode structure 120 located on the surface of the cellrow trench isolation structure 102; A first sidewall 115 located on both sides of the gate electrode structure 110; A source region 130 and a drain region 140 located in the active region 101 on both sides of the gate electrode structure 110; A second side wedge 125 located at one side remote from the source region 130 or the drain region 140 of the dummy gate electrode structure; A first interconnect layer 160 located on a surface of the source region 130, a top surface of the dummy gate electrode structure 120 adjacent to the source region 130, and a sidewall surface proximate to one side of the source region 130; A second interconnect layer 170 located on the top surface of the drain region 140 and on the top surface of the dummy gate electrode structure 120 adjacent to the drain region 140 and on the side wall surface near one side of the drain region 140, .

The conductive plug 195 connected to the source region 130 is located on the dummy gate electrode structure 120 adjacent to the source region 130 and the conductive plug 195 connected to the drain region 140 is connected to the drain region 140 Since the conductive plugs are not formed directly on the surfaces of the source region 130 and the drain region 140 and the source region 130 and the drain region 140 are exposed And the dummy gate electrode structure 120 is located on the surface of the cell row trench isolation structure 102, so that it does not occupy an additional chip area, and the chip area occupied by the finally formed MOS transistor is So that it is advantageous to improve the integration degree of the chip.

Although the present invention has been disclosed by way of preferred embodiments, it is not intended to limit the present invention. It will be understood by those skilled in the art that changes may be made and equivalents may be made thereto by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it should be understood that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

100: semiconductor substrate
101: active area
102: Cellrow trench isolation structure
110: gate electrode structure
120: Dummy gate electrode structure
130: source region
140: drain region
160: first interconnection layer
170: second interconnect layer
195: Conductive plug

Claims (23)

Providing a semiconductor substrate in which an active region and a cellrow trench isolation structure surrounding the active region are formed;
Forming a gate electrode structure on a surface of the active region and forming a dummy gate electrode structure on a surface of the cellrow trench isolation structure;
Forming a source region and a drain region in active regions on both sides of the gate electrode structure; And
Forming an interconnect layer on a surface of the source region, a surface of the drain region, and at least a portion of an upper surface of the dummy gate electrode structure;
Lt; / RTI >
The interconnect layer at the surface of the source region is connected to the interconnect layer at the top surface of the dummy gate electrode structure adjacent to the source region to form a first interconnect layer, Forming a second interconnect layer to interconnect the interconnect layer of the upper surface of the dummy gate electrode structure adjacent the drain region,
Wherein the dummy gate electrode structure is completely located on the surface of the cellrow trench isolation structure,
When the sidewalls adjacent to one side of the source region or the drain region of the dummy gate electrode structure and the edges of the corresponding cell row trench isolation structure are spaced at a certain distance, the thickness of the interconnection layer formed using the epitaxial process is smaller than the thickness of the dummy gate Wherein a distance between the sidewalls adjacent to one side of the source region or the drain region of the electrode structure and the edge of the corresponding cellrow trench isolation structure is greater than the spacing between the sidewalls adjacent to one side of the source region or drain region of the electrode structure,
Lt; / RTI > The method according to claim 1,
Wherein the interconnect layer is a metal layer, a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion. The method according to claim 1,
Forming a first sidewall on a sidewall of the gate electrode structure and forming a second sidewall on a sidewall of the dummy gate electrode structure. The method of claim 3,
Removing the second side wails on either side of the dummy gate electrode structure prior to forming the interconnect layer. The method of claim 3,
Removing the second side wally adjacent one side of the source region or drain region of the dummy gate electrode structure prior to forming the interconnect layer. The method according to claim 4 or 5,
When the interconnection layer is a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion, the surface of the source region and the surface of the drain region A sidewall surface proximate to one side of the source region or drain region of the dummy gate electrode structure, and at least a portion of the top surface. 5. The method of claim 4,
When the interconnecting layer is a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion, the surface of the source region and the surface of the drain region And forming an interconnect layer on the sidewall surface and top surface of the dummy gate electrode structure. The method according to claim 1,
Wherein a dummy gate electrode structure located on a surface of the cellrow trench isolation structure is connected to another MOS transistor with an interconnection structure. The method according to claim 1,
Forming a conductive plug on the dummy gate electrode structure and connecting the source region and the drain region to an interconnecting layer and an external circuit through the conductive plug. The method according to claim 1,
Wherein a portion of the dummy gate electrode structure is located on a surface of the cellrow trench isolation structure and the other portion is located on a surface of a corresponding active region. The method according to claim 1,
Wherein the gate electrode structure and the dummy gate electrode structure are formed simultaneously in the same forming process. The method of claim 3,
Wherein the first side wirings and the second side wirings are formed simultaneously in the same forming process. A semiconductor substrate;
An active region located within the semiconductor substrate; a cellrow trench isolation structure located within the semiconductor substrate and surrounding the active region;
A gate electrode structure located on a surface of the active region, a dummy gate electrode structure located on a surface of the cellrow trench isolation structure,
A source region and a drain region located in active regions on both sides of the gate electrode structure; And
A first interconnect layer located on a top surface of the dummy gate electrode structure adjacent a surface and source region of the source region, a second interconnect layer located on a top surface of the dummy gate electrode structure adjacent the surface and drain regions of the drain region, An interconnect layer;
/ RTI >
The dummy gate electrode structure is completely located on the surface of the cellrow trench isolation structure,
When the sidewalls adjacent to one side of the source region or the drain region of the dummy gate electrode structure and the edges of the corresponding cell row trench isolation structure are spaced at a certain distance, the thickness of the interconnection layer formed using the epitaxial process is smaller than the thickness of the dummy gate Wherein a distance between the sidewalls adjacent to one side of the source region or the drain region of the electrode structure and the edge of the corresponding cellrow trench isolation structure is greater than the spacing between the sidewalls adjacent to one side of the source region or drain region of the electrode structure,
MOS transistor. 14. The method of claim 13,
Wherein the interconnect layer is a metal layer, a single crystal silicon layer doped with an impurity ion, a silicon germanium layer doped with an impurity ion, or a silicon carbide layer doped with an impurity ion. 14. The method of claim 13,
Further comprising a second sidewill located at a side remote from a source region or a drain region of the dummy gate electrode structure, wherein a surface of the source region, a top surface of a dummy gate electrode structure adjacent to the source region, Wherein a first interconnect layer is formed on the sidewall surface adjacent to the source region of the structure. 14. The method of claim 13,
Wherein a first interconnect layer is formed on the surface of the source region, on top of the dummy gate electrode structure adjacent to the source region, and on the sidewall surface. 14. The method of claim 13,
And the dummy gate electrode structure located on the surface of the cellrow trench isolation structure is connected to another MOS transistor as an interconnect structure. 14. The method of claim 13,
Wherein the conductive plug located on the dummy gate electrode structure connects the source region and the drain region with an interconnect layer and an external circuit through the conductive plug. 14. The method of claim 13,
Wherein a portion of the dummy gate electrode structure is located on a surface of the cellrow trench isolation structure and the other portion is located on a surface of a corresponding active region. delete delete delete delete
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