TWI527096B - Growth epi as interconnection layer on mos structure - Google Patents

Description

MOS transistor and method of forming same

The present invention relates to semiconductor technology, and more particularly to a MOS transistor having a small wafer area and a method of forming the same.

With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. According to the scaling down rule, when the overall size of the MOS transistor is reduced, the source, drain, and gate are also reduced. Dimensions of structures such as poles and conductive plugs. Please refer to FIG. 1 , which is a schematic structural diagram of a prior art MOS transistor, specifically including: a semiconductor substrate 10 , an active region 11 located in the semiconductor substrate 10 , and the semiconductor substrate 10 surrounding the semiconductor substrate 10 a shallow trench isolation structure 12 of the active region 11, a gate structure 20 on the surface of the active region 11, a source region 13 and a drain region 14 in the active region 11 on both sides of the gate structure 20, a first metal halide 30 located on the surface of the source region 13, a second metal halide 40 on the surface of the drain region 14, and a first conductive plug 35 on the surface of the first metal halide 30. A second conductive plug 45 on the surface of the second metal telluride 40 is described. Since the first conductive plug 35 is located on the source region 13, the second conductive plug 45 is located on the drain region 14, the source The width S1 of the region 13 and the drain region 14 is at least larger than the diameters of the first conductive plug 35 and the second conductive plug 45. However, due to the limitation of the semiconductor manufacturing process, the size of the conductive plug formed by the current process is large, so that the width of the existing source and drain regions is also large, which is disadvantageous for reducing the overall size of the MOS transistor.

For more information on MOS transistors and their formation, please refer to US Patent Publication No. US 2009/0079013 A1.

The problem to be solved by the present invention is to provide a MOS transistor and a method for forming the same, in which an interconnection layer is formed between a dummy gate structure and a gate/source on a shallow trench isolation structure to form a MOS transistor having a small wafer area. .

In order to solve the above problems, the technical solution of the present invention provides a method for forming a MOS transistor, comprising: providing a semiconductor substrate, forming an active region and a shallow trench isolation structure surrounding the active region in the semiconductor substrate Forming a gate structure on a surface of the active region, forming a dummy gate structure on a surface of the shallow trench isolation structure; forming a source region and a drain region in an active region on both sides of the gate structure; The source region surface, the drain region, and at least a portion of the top surface of the dummy gate structure form an interconnect layer, wherein the interconnect layer of the source region surface is connected to the interconnect layer of the dummy gate top surface adjacent to the source region Forming a first interconnect layer; the interconnect layer of the drain region surface and the interconnect layer of the dummy gate top surface adjacent to the drain region are connected to form a second interconnect layer.

Optionally, the interconnect layer is a metal layer, a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or a carbon doped with impurity ions. 矽 layer.

Optionally, the method further includes: forming a first sidewall spacer on a sidewall of the gate structure, and forming a second sidewall spacer on a sidewall of the dummy gate structure.

Optionally, the second sidewall spacers on both sides of the dummy gate structure are removed before the interconnection layer is formed.

Optionally, before the forming the interconnect layer, the second sidewall spacer of the dummy gate structure close to a side of the source region or the drain region is removed.

Optionally, when the interconnect layer is a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or a tantalum carbide layer doped with impurity ions, the source is used in the source The surface of the region, the surface of the drain region, the sidewall surface of the dummy gate structure adjacent to one side of the source region or the drain region, and at least a portion of the top surface form an interconnect layer.

Optionally, when the interconnect layer is a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or a tantalum carbide layer doped with impurity ions, an epitaxial process is used in the source region. The surface, the drain surface, the sidewall surface of the dummy gate structure, and the top surface form an interconnect layer.

Optionally, the dummy gate structure is completely located on the surface of the shallow trench isolation structure.

Optionally, when the sidewall of the dummy gate structure near the source region or the drain region has a certain spacing from the edge of the corresponding shallow trench isolation structure, the thickness of the interconnect layer formed by the epitaxial process is greater than the dummy gate structure. The spacing between the sidewalls on one side of the source or drain region and the edge of the corresponding shallow trench isolation structure.

Optionally, the dummy gate structure on the surface of the shallow trench isolation structure is Connect the interconnect structure to other MOS transistors.

Optionally, a conductive plug is formed on the dummy gate structure, so that the source region and the drain region are connected to the external circuit through the interconnect layer and the conductive plug.

Optionally, the dummy gate structure portion is located on a surface of the shallow trench isolation structure and partially on a surface of the corresponding active region.

Optionally, the gate structure and the dummy gate structure are formed synchronously in the same forming process.

Optionally, the first sidewall spacer and the second sidewall spacer are synchronously formed in the same forming process.

The technical solution of the present invention further provides a MOS transistor, comprising: a semiconductor substrate, an active region located in the semiconductor substrate, and a shallow trench isolation structure surrounding the active region in the semiconductor substrate a gate structure on a surface of the active region, a dummy gate structure on a surface of the shallow trench isolation structure; source and drain regions in an active region on both sides of the gate structure; A first interconnect layer of the source region surface and a top surface of the dummy gate structure adjacent to the source region, a second interconnect layer on the drain region surface and a top surface of the dummy gate structure adjacent to the drain region.

Optionally, the interconnect layer is a metal layer, a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or a tantalum carbide layer doped with impurity ions.

Optionally, the method further includes: a second sidewall spacer located on a side of the dummy gate structure away from the source region or the drain region, a surface of the source region, a top surface of the dummy gate structure adjacent to the source region, and a dummy gate structure A first interconnect layer is formed on a sidewall surface adjacent to the source region.

Optionally, a first interconnect layer is formed on a surface of the source region, a top surface of the dummy gate structure adjacent to the source region, and a sidewall surface.

Optionally, the dummy gate structure is completely located on the surface of the shallow trench isolation structure.

Optionally, when the sidewall of the dummy gate structure near the source region or the drain region has a certain spacing from the edge of the corresponding shallow trench isolation structure, the thickness of the interconnect layer formed by the epitaxial process is greater than the dummy gate structure is closer. The spacing between the sidewalls on one side of the source or drain region and the edge of the corresponding shallow trench isolation structure.

Optionally, the dummy gate structure on the surface of the shallow trench isolation structure is connected as an interconnect structure to other MOS transistors.

Optionally, the conductive plug on the dummy gate structure is such that the source and drain regions are connected to the external circuit through the interconnect layer and the conductive plug.

Optionally, the dummy gate structure portion is located on a surface of the shallow trench isolation structure and partially on a surface of the corresponding active region.

Compared with the prior art, the present invention has the following advantages: the embodiment of the present invention forms a dummy gate structure on the surface of the shallow trench isolation structure, and forms an interconnection layer on the surface of the source region, the surface of the drain region, and at least a portion of the top surface of the dummy gate structure. The source region and the drain region are electrically connected to the dummy gate structure. Since the conductive plug is not directly formed on the surface of the source region and the drain region, the width of the source region and the drain region may be narrow, and the dummy gate structure is located on the surface of the shallow trench isolation structure, and does not occupy additional The area of the wafer is such that the area of the wafer which is finally formed by the MOS transistor is small, which is advantageous for improving the degree of wafer integration.

Further, when the dummy gate structure is completely located on the surface of the shallow trench isolation structure, the dummy gate structure on the surface of the shallow trench isolation structure is connected as an interconnect structure to other MOS transistors, which is equivalent to adding a layer of mutual Layering helps to improve wiring density and wiring selectivity.

10‧‧‧Semiconductor substrate

11‧‧‧Active area

12‧‧‧Shallow trench isolation structure

13‧‧‧ source area

14‧‧‧Drained area

20‧‧‧Gate structure

30‧‧‧First metal telluride

35‧‧‧First conductive plug

40‧‧‧Second metal telluride

45‧‧‧Second conductive plug

100‧‧‧Semiconductor substrate

101‧‧‧Active area

102‧‧‧Shallow trench isolation structure

110‧‧‧Gate structure

111‧‧‧First gate dielectric layer

112‧‧‧First gate electrode

113‧‧‧First hard mask layer

115‧‧‧First side wall

120‧‧‧pseudo gate structure

121‧‧‧Second gate dielectric layer

122‧‧‧second gate electrode

123‧‧‧Second hard mask layer

125‧‧‧Second side wall

130‧‧‧ source area

140‧‧‧Drained area

150‧‧‧ mask layer

160‧‧‧First interconnect layer

170‧‧‧Second interconnect layer

180‧‧‧metal telluride layer

190‧‧‧Interlayer dielectric layer

195‧‧‧conductive plug

S1‧‧‧ Width of the drain zone 14

1 is a schematic structural view of a prior art MOS transistor; and FIGS. 2 to 10 are schematic cross-sectional structural views showing a process of forming a MOS transistor according to an embodiment of the present invention.

In the prior art, a conductive plug is usually formed on the surface of the source and drain regions, and the source and drain regions are connected to the external circuit by the conductive plug. However, due to the limitation of the current semiconductor manufacturing process, the current size of the conductive plug formed by the process is large, so that the width of the existing source and drain regions is also large, which is disadvantageous for reducing the overall size of the MOS transistor.

Accordingly, the present invention provides a MOS transistor and a method of forming the same, in which a dummy gate structure is formed on a surface of a shallow trench isolation structure close to a source region or a drain region, and a surface adjacent to the source region and a dummy adjacent to the source region are formed. Forming a first interconnect layer on a top surface of the gate structure, forming a second interconnect layer on the surface of the drain region and a top surface of the dummy gate structure adjacent to the drain region, and subsequently forming a conductive plug on the dummy gate structure, or The dummy gate structure acts as an interconnect structure connecting different MOS transistors. Since the surface of the shallow trench isolation structure in the prior art does not form a semiconductor structure, the area of the wafer is wasted, and the embodiment of the present invention is shallow. The surface of the trench isolation structure forms a dummy gate structure, and the source region and the drain region are electrically connected to the dummy gate structure by using the first interconnect layer and the second interconnect layer, and the source region and the drain region of the MOS transistor are electrically connected by using the dummy gate structure. Connected to an external circuit. Since it is not necessary to form a conductive plug directly on the surface of the source or drain region, the width of the source region and the drain region can be reduced, which is advantageous for reducing the wafer area occupied by the MOS transistor.

The above described objects, features and advantages of the present invention will become more apparent from the aspects of the invention.

Specific details are set forth in the following description in order to provide a thorough understanding of the invention. However, the present invention can be implemented in various other ways than those described herein, and those skilled in the art can make similar promotion without departing from the scope of the present invention. The invention is therefore not limited by the specific embodiments disclosed below.

The embodiment of the present invention firstly provides a method for forming a MOS transistor. Referring to FIG. 2 to FIG. 10, FIG. 2 is a schematic cross-sectional structural view showing a process of forming a MOS transistor according to an embodiment of the present invention.

Specifically, referring to FIG. 2, a semiconductor substrate 100 is provided in which an active region 101 and a shallow trench isolation structure 102 surrounding the active region 101 are formed.

The semiconductor substrate 100 includes one of a germanium substrate, a germanium substrate, a germanium substrate, a tantalum carbide substrate, an insulator upper germanium substrate, and an insulator upper germanium substrate. In the present embodiment, the semiconductor substrate 100 is a germanium substrate.

In this embodiment, a well region is first formed in the active region 101 by an ion implantation process, and the semiconductor substrate 100 around the well region is etched. A shallow trench surrounding the active region 101 is filled, and the shallow trench is filled with full yttrium oxide to form a shallow trench isolation structure 102. In other embodiments, an extrinsic semiconductor substrate can also be utilized directly as the active region. Since the active region and the shallow trench isolation structure are well known to those skilled in the art, they will not be described in detail herein.

Referring to FIG. 3, a gate structure 110 is formed on the surface of the active region 101, and a dummy gate structure 120 is formed on the surface of the shallow trench isolation structure 102. The dummy gate structure 120 is completely located in the shallow trench isolation structure. 102 surface.

A specific process of forming the gate structure 110 and the dummy gate structure 120 includes: forming a gate dielectric material layer (not shown) on the surface of the semiconductor substrate 100, and forming a polysilicon material layer on the surface of the gate dielectric material layer (not a hard mask material layer (not shown) is formed on the surface of the polysilicon material layer, and a photoresist layer (not shown) is formed on the surface of the hard mask material layer for the photoresist layer And performing exposure development to form a photoresist pattern, and etching the hard mask material layer, the polysilicon material layer, and the gate dielectric material layer to form the active region 101 by using the photoresist pattern as a mask. A gate structure 110 of the surface and a dummy gate structure 120 on the surface of the shallow trench isolation structure 102. The gate structure 110 includes a first gate dielectric layer 111 and a first gate electrode 112 on a surface of the first gate dielectric layer 111. The top surface of the gate structure 110 further has a first hard mask layer 113. The dummy gate structure 120 includes a second gate dielectric layer 121 and a second gate electrode 122 on a surface of the second gate dielectric layer 121. The top surface of the dummy gate structure 120 further has a second hard mask layer 123.

In the present embodiment, the gate structure 110 and the dummy gate structure 120 are formed by the same deposition and etching process. The gate structure 110 and the dummy gate structure 120 have the same material, which saves process steps and reduces process cost. In other embodiments, the gate structure and the dummy gate structure may also be formed separately.

In other embodiments, the first hard mask layer and the second hard mask layer may not be formed, and the polysilicon material layer and the gate dielectric material layer are etched by using a patterned photoresist layer to form a gate structure and Pseudo gate structure.

In this embodiment, the dummy gate structure 120 is completely located on the surface of the shallow trench isolation structure 102, and a certain distance between the sidewall of the dummy gate structure 120 and the edge of the shallow trench isolation structure 102 is The dummy gate structure 120 is not in direct contact with the active region. When the dummy gate structure 120 of the surface of the shallow trench isolation structure 102 is subsequently utilized as an interconnect structure, the dummy gate structure 120 is not in direct contact with the active region, and the second gate electrode 122 of the dummy gate structure 120 is prevented from being active. A short circuit may occur between the regions 101 due to breakdown of the second gate dielectric layer 121.

In other embodiments, the dummy gate structure may also be located on the surface of the shallow trench isolation structure, and the dummy gate structure sidewalls on one side of the gate structure are aligned with the edges of the shallow trench isolation structure.

In other embodiments, the dummy gate structure may also be partially located on the surface of the shallow trench isolation structure, and partially located near the source or drain surface of the shallow trench isolation structure. Since the size of the conductive plug formed by the current process is large, when the conductive plug is subsequently formed on the dummy gate structure, the width of the dummy gate structure required is also large, and the width of the shallow trench isolation structure required is also Larger. In order to reduce the width of the shallow trench isolation structure, thereby reducing the MOS transistor The overall size of the dummy gate structure spanning the shallow trench isolation structure and the adjacent source or drain surface surface, so that the width of the shallow trench isolation structure covered by the dummy gate structure is reduced, so that The overall width of the shallow trench isolation structure required is also small, thereby reducing the overall size of the MOS transistor.

In the present embodiment, the dummy gate structure 120 is only located on the surface of the shallow trench isolation structure 102 parallel to the gate structure 110. When the dummy gate structure is used as an interconnect structure for connecting different MOS transistors, the dummy gate structure may also be formed on a surface of a shallow trench isolation structure perpendicular to the gate structure, and the dummy gate structure Not connected to the gate structure.

Referring to FIG. 4, a first sidewall spacer 115 is formed on a sidewall of the gate structure 110, and a second sidewall spacer 125 is formed on a sidewall of the dummy gate structure 120. The first sidewall spacer 115 and the second sidewall spacer 125 are formed. A portion of the active region 101 is exposed.

The specific process of forming the first sidewall spacer 115 and the second sidewall spacer 125 is: forming a dielectric layer on the surface of the semiconductor substrate 100, the shallow trench isolation structure 102, the gate structure 110, and the dummy gate structure 120 (not shown) The dielectric layer is etched back until the surface of the semiconductor substrate 100, the surface of the shallow trench isolation structure 102, the surface of the first hard mask layer 113 at the top of the gate structure 110, and the dummy gate structure are exposed. A surface of the second hard mask layer 123 at the top of the 120, a first sidewall spacer 115 is formed on the sidewall of the gate structure 110, and a second sidewall spacer 125 is formed on the sidewall of the dummy gate structure 120. The dielectric layer is a stacked structure of one or more layers of a ruthenium oxide layer, a tantalum nitride layer, and a ruthenium oxynitride layer. The material of the dielectric layer is different from the material of the first hard mask layer and the second hard mask layer, so that the first layer is used when etching the dielectric layer A hard mask layer and a second hard mask layer serve as an etch stop layer to avoid damage to the gate structure. Since the source region and the drain region need to be connected to the dummy gate structure through the interconnect layer, the width of the portion of the active region 101 is exposed between the first sidewall spacer 115 and the second sidewall spacer 125, or the first The width of the active region 101 between the side wall 115 and the edge of the closest shallow trench isolation structure 102 need not be too large, and may be much smaller than the diameter of the conductive plug, ie, much smaller than the existing source region or The width of the drain region is beneficial to reduce the overall size of the MOS transistor.

Referring to FIG. 5, a source region 130 and a drain region 140 are formed in the active region 101 exposed on both sides of the gate structure 110.

In the embodiment, the gate structure 110, the dummy gate structure 120, the first sidewall spacer 115, and the second sidewall spacer 125 are used as a mask, and between the first sidewall spacer 115 and the second sidewall spacer 125 The exposed active region 101 is subjected to P-type or N-type ion implantation, and is annealed to form a source region 130 and a drain region 140.

In other embodiments, lightly doping ion implantation may be performed in an active region on both sides of the gate structure before forming the first sidewall spacer and the second spacer sidewall, in forming the first side. After the wall and the second sidewall, the heavily doped ion implantation is performed in the active regions exposed on both sides of the first sidewall and the second sidewall to form a source region and a drain region, and the lightly doped ions The implantation process can reduce the hot carrier injection effect and short channel effect of the MOS transistor.

In other embodiments, the gate structure, the dummy gate structure, the first sidewall spacer, and the second sidewall spacer may be used as a mask, and the exposed between the first sidewall spacer and the second sidewall spacer may be The source region is etched to form a trench and is in the trench The filled material or the tantalum carbide material is filled by an epitaxial process to form source and drain regions. The tantalum material or tantalum carbide material is doped in situ with P-type or N-type impurity ions in an epitaxial process. In other embodiments, after the tantalum material or the tantalum carbide material may be formed, the germanium material or the tantalum carbide material is doped with impurity ions by an ion implantation process. Forming the source region and the drain region by using the germanium material or the tantalum carbide material may stress the lattice of the MOS transistor channel region, thereby improving the mobility of carriers in the channel region and improving the electrical conductivity of the MOS transistor. performance.

Referring to FIG. 6, a mask layer 150 is formed on the surface of the semiconductor substrate 100, the gate structure 110, the dummy gate structure 120, and the first sidewall 115. The mask layer 150 exposes the surface and drain regions of the source region 130. a 140 surface, a portion of the top surface of the dummy gate structure 120 and the dummy gate structure 120 are adjacent to the second sidewall spacer 125 on the side of the gate structure 110 (please refer to FIG. 5 ), and the mask layer 150 is used as a mask to remove the The dummy gate structure 120 is adjacent to the second spacer 125 on the side of the gate structure 110 and the partially exposed second hard mask layer 123 on the top surface of the dummy gate structure 120.

The process of removing the second spacer 125 and the second hard mask layer 123 is a wet etching process.

In this embodiment, since the subsequently formed interconnect layer is formed by a selective epitaxial process, the selective epitaxial process can only be formed on the surface of a semiconductor material such as polycrystalline germanium, single crystal germanium, germanium, tantalum carbide, etc., and cannot be in the form of germanium oxide. The surface of the dielectric layer such as tantalum nitride is formed. In order to connect the interconnect layer formed on the dummy gate structure to the interconnect layer formed on the source or drain surface, the dummy gate structure 120 needs to be removed from the second spacer 125 on the side of the gate structure 110. The interconnect layer on the top surface of the dummy gate structure 120, the sidewall surface of the dummy gate structure 120, the surface of the source region 130 or the drain region 140 is electrically connected such that the source region 130 or the drain region 140 and the adjacent dummy gate structure 120 Electrical connection.

In other embodiments, the mask layer may also expose all of the top surface of the dummy gate structure. After the second hard mask layer is removed, an interconnect layer is formed on all top surfaces of the dummy gate structure. The surface is subsequently flattened when the conductive plug is formed on the dummy gate structure.

In other embodiments, the mask layer may also expose all of the top surface of the dummy gate structure and the second sidewall spacers on both sides, after removing the second hard mask layer and the second sidewall spacers on both sides, An interconnect layer is formed on a top surface of the dummy gate structure and sidewall surfaces on both sides such that a surface is flattened when a conductive plug is subsequently formed on the dummy gate structure.

Referring to FIG. 7, the surface of the source region 130, the surface of the drain region 140, a portion of the top surface of the dummy gate structure 120, and the sidewall of the dummy gate structure 120 near the source region 130 or the drain region 140 are exposed in the mask layer 150 by an epitaxial process. The surface forms an interconnect layer.

In this embodiment, the material of the interconnect layer formed by the epitaxial process is a semiconductor material such as germanium, antimony or tantalum carbide doped with N-type or P-type impurity ions, and the doping is N-type or P-type. The semiconductor material such as tantalum, niobium or niobium carbide of the type impurity ions has good conductivity and low on-resistance, so that the source region 130 or the drain region 140 is electrically connected to the adjacent dummy gate structure 120. The interconnect layer on the surface of the source region 130, the dummy gate structure 120 adjacent to the source region 130, and the interconnect layer on the sidewall surface of the source region 130 and the top surface of the dummy gate structure 120 adjacent to the source region 130 Interconnect layer The first interconnect layer 160, the interconnect layer on the surface of the drain region 140, the dummy gate structure 120 adjacent to the drain region 140, and the interconnect layer adjacent to the sidewall surface of the drain region 140 and the dummy gate adjacent to the drain region 140 The interconnect layer of the top surface of structure 120 constitutes second interconnect layer 170.

In this embodiment, the impurity ions are doped in-situ in the interconnect layer by an epitaxial process. In other embodiments, after the interconnect layer is formed, impurity ions are doped in the interconnect layer using an ion implantation process.

When the material of the interconnect layer is tantalum or tantalum carbide, the interconnect layer formed on the surface of the source and drain regions may stress the semiconductor substrate, and the carriers of the channel region of the MOS transistor may be improved. The migration rate is beneficial to improve the electrical performance of the MOS transistor.

In this embodiment, the mask layer 150 is used as a mask, and an interconnect layer is formed on the exposed source region 130, the drain region 140, and the surface of the dummy gate structure 120. After the interconnect layer is formed, the removal layer is removed. The mask layer 150 is described. In other embodiments, the mask layer may also be removed first, and an interconnect layer is formed on the exposed source region, drain region, top surface of the dummy gate structure, and sidewall surface. Since the top surface of the gate structure is covered by the mask layer has a first hard mask layer, the area of the top surface of the dummy gate structure covered by the mask layer has a second hard mask layer, and the interconnect layer formed by the epitaxial process It can also be formed only on the source and drain regions and the top and sidewall surfaces of the dummy gate structure.

In other embodiments, a metal interconnect layer may be formed on the source region, the drain region, and the dummy gate top and sidewall surfaces by a sputtering process, a physical vapor deposition process, or a chemical vapor deposition process, such that the source The region, the drain region and the dummy gate structure adjacent thereto are electrically connected. When the material of the interconnect layer is gold In time, the second sidewall spacer may not be removed, and a metal interconnection layer may be formed on a top surface of the dummy gate structure, a second sidewall spacer surface adjacent to the gate structure, and a surface of the source region and the drain region. The source region, the drain region, and the dummy gate structure adjacent thereto are electrically connected.

Referring to FIG. 8, the mask layer 150 (please refer to FIG. 7), the first hard mask layer 113 (please refer to FIG. 7), and the second hard mask layer 123 (refer to FIG. 7) are removed.

A specific process for removing the mask layer 150, the first hard mask layer 113, and the second hard mask layer 123 is a wet etching process or a dry etching process. A person skilled in the art can reasonably select different etching processes according to the materials of the mask layer 150, the first hard mask layer 113 and the second hard mask layer 123, so that the mask layer and the first hard mask are removed. Simultaneously with the film layer and the second hard mask layer, the interconnect layer and the first spacer and the second spacer are not damaged. Since the materials of the different mask layers, the first hard mask layer and the second hard mask layer correspond to different etching processes, they will not be described in detail herein.

Referring to FIG. 9, a metal telluride layer 180 is formed on the surface of the gate structure 110, the dummy gate structure 120, the first interconnect layer 160, and the second interconnect layer 170.

The material of the metal telluride layer 180 is nickel telluride, titanium germanide or tungsten germanide. In the embodiment, the material of the metal telluride layer 180 is nickel germanide. The method of forming the metal telluride layer 180 includes: forming a nickel metal layer on the surface of the semiconductor substrate 100, the gate structure 110, the dummy gate structure 120, the first interconnect layer 160, and the second interconnect layer 170 (not As shown in the figure, the nickel metal layer and the gate structure 110, pseudo by an annealing process The gate structure 120, the first interconnect layer 160, the second interconnect layer 170 contact semiconductor material reacts to form a nickel germanide, the nickel germanide is a metal telluride layer 180, and the wet etching process is used to remove unreacted Nickel metal layer.

In this embodiment, since a conductive plug is formed on the gate structure 110 and the dummy gate structure 120, the interlayer interconnection layer and the source or drain region of the MOS transistor are used by the conductive plug. Connection, by forming a metal telluride layer 180 on the gate structure 110 and the dummy gate structure 120, the contact resistance can be lowered, and the electrical performance of the MOS transistor can be improved.

Referring to FIG. 10, an interlayer dielectric layer 190 is formed on the surface of the semiconductor substrate 100, and a conductive plug 195 penetrating the interlayer dielectric layer 190 is formed in the interlayer dielectric layer 190, and the conductive plug 195 is located at the gate. The surface of the metal telluride layer 180 on the structure 110 and the surface of the metal telluride layer 180 on the dummy gate structure 120.

Since the conductive plug 195 connected to the source region 130 is located on the dummy gate structure 120 adjacent to the source region 130, the conductive plug 195 connected to the drain region 140 is located on the dummy gate structure 120 adjacent to the drain region 140. The conductive plug is not directly formed on the surface of the source region 130 and the drain region 140, so that the width of the source region 130 and the drain region 140 may be narrow, and the dummy gate structure 120 is located in the shallow trench isolation structure 102. The surface does not occupy an extra wafer area, so that the wafer area occupied by the final MOS transistor is small.

In other embodiments, the conductive plug may not be formed on the dummy gate structure, and the dummy gate structure is used as the interconnect layer to connect the source or drain regions of different MOS transistors, which is equivalent to adding a layer of mutual Layered, favorable Improve wiring density and wiring selectivity.

According to the above formation method, an embodiment of the present invention further provides a MOS transistor. Referring to FIG. 10, the MOS transistor includes: a semiconductor substrate 100, and an active region 101 located in the semiconductor substrate 100. a shallow trench isolation structure 102 surrounding the active region 101 in the semiconductor substrate 100; a gate structure 110 on the surface of the active region 101, and a dummy gate structure on the surface of the shallow trench isolation structure 102 a first sidewall spacer 115 on both sides of the gate structure 110; a source region 130 and a drain region 140 in the active region 101 on both sides of the gate structure 110; and located in the dummy gate structure 120 away from a second spacer 125 on one side of the source region 130 or the drain region 140; a first surface on the surface of the source region 130, a top surface of the dummy gate structure 120 adjacent to the source region 130, and a sidewall surface near the source region 130 side The interconnect layer 160 is located on the surface of the drain region 140, the top surface of the dummy gate structure 120 adjacent to the drain region 140, and the second interconnect layer 170 near the sidewall surface of the drain region 140 side.

Since the conductive plug 195 connected to the source region 130 is located on the dummy gate structure 120 adjacent to the source region 130, the conductive plug 195 connected to the drain region 140 is located on the dummy gate structure 120 adjacent to the drain region 140. The conductive plug is not directly formed on the surface of the source region 130 and the drain region 140, so that the width of the source region 130 and the drain region 140 may be narrow, and the dummy gate structure 120 is located in the shallow trench isolation structure 102. The surface does not occupy an extra wafer area, so that the final MOS transistor occupies a small area of the wafer, which is advantageous for improving the wafer integration.

Although the present invention has been disclosed as a preferred embodiment, it is not In order to limit the present invention, any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. The contents of the technical solutions, any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are all within the scope of protection of the technical solutions of the present invention.

100‧‧‧Semiconductor substrate

101‧‧‧Active area

102‧‧‧Shallow trench isolation structure

110‧‧‧Gate structure

115‧‧‧First side wall

120‧‧‧pseudo gate structure

125‧‧‧Second side wall

130‧‧‧ source area

140‧‧‧Drained area

160‧‧‧First interconnect layer

170‧‧‧Second interconnect layer

180‧‧‧metal telluride layer

190‧‧‧Interlayer dielectric layer

195‧‧‧conductive plug

Claims (20)

A method of forming a MOS transistor, comprising: providing a semiconductor substrate, forming an active region and a shallow trench isolation structure surrounding the active region in the semiconductor substrate; Forming a gate structure on the surface, forming a dummy gate structure on the surface of the shallow trench isolation structure; forming a source region and a drain region in an active region on both sides of the gate structure; on the surface of the source region and the surface of the drain region At least a portion of the top surface of the dummy gate structure forms an interconnect layer, wherein the interconnect layer of the source region surface and the interconnect layer of the dummy gate top surface adjacent to the source region are connected to form a first interconnect layer The interconnect layer of the drain surface and the interconnect layer of the dummy gate top surface adjacent to the drain region are connected to form a second interconnect layer; wherein the first sidewall is formed on the sidewall of the gate structure, Forming a second sidewall in the sidewall of the dummy gate structure; wherein the second sidewalls on both sides of the dummy gate structure are removed prior to forming the interconnect layer. The method of forming a MOS transistor according to claim 1, wherein the interconnect layer is a metal layer, a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or doped A layer of tantalum carbide with impurity ions. A method of forming a MOS transistor according to claim 1, characterized in that the second spacer wall of the dummy gate structure close to the source region or the drain region is removed before the interconnection layer is formed. A method of forming a MOS transistor according to claim 1 or 3, Characterized in that when the interconnect layer is a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or a tantalum carbide layer doped with impurity ions, the source is used in the source The surface of the region, the surface of the drain region, the sidewall surface of the dummy gate structure adjacent to one side of the source region or the drain region, and at least a portion of the top surface form an interconnect layer. The method of forming a MOS transistor according to claim 1, wherein the interconnect layer is a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or doped with impurity ions. When the tantalum carbide layer is formed, an interconnection layer is formed on the surface of the source region, the surface of the drain region, the sidewall surface of the dummy gate structure, and the top surface by an epitaxial process. A method of forming a MOS transistor according to claim 1, wherein the dummy gate structure is completely located on a surface of the shallow trench isolation structure. The method for forming a MOS transistor according to claim 6, wherein when the side wall of the dummy gate structure near the source region or the drain region has a certain distance from the edge of the corresponding shallow trench isolation structure, The thickness of the interconnect layer formed by the epitaxial process is greater than the pitch between the sidewall of the dummy gate structure near the source or drain side and the edge of the corresponding shallow trench isolation structure. The method of forming a MOS transistor according to claim 6, wherein the dummy gate structure on the surface of the shallow trench isolation structure is connected as an interconnection structure to other MOS transistors. The method of forming a MOS transistor according to claim 1, wherein a conductive plug is formed on the dummy gate structure such that the source region and the drain region are connected to the external circuit through the interconnect layer and the conductive plug. A method of forming a MOS transistor according to claim 1, The dummy gate structure portion is located on the surface of the shallow trench isolation structure and partially on the surface of the corresponding active region. A method of forming a MOS transistor according to claim 1, wherein the gate structure and the dummy gate structure are simultaneously formed in the same formation process. A method of forming a MOS transistor according to claim 1, wherein the first spacer and the second spacer are simultaneously formed in the same forming process. A MOS transistor, comprising: a semiconductor substrate, an active region in the semiconductor substrate, a shallow trench isolation structure surrounding the active region in the semiconductor substrate; a gate structure on a surface of the active region, a dummy gate structure on a surface of the shallow trench isolation structure; source and drain regions in an active region on both sides of the gate structure; on a surface of the source region a first interconnect layer on a top surface of the dummy gate structure adjacent to the source region, a second interconnect layer on a surface of the drain region and a top surface of the dummy gate structure adjacent to the drain region; wherein the dummy gate structure It is completely on the surface of the shallow trench isolation structure. The MOS transistor according to claim 13, wherein the interconnect layer is a metal layer, a single crystal germanium layer doped with impurity ions, a germanium layer doped with impurity ions, or doped with impurity ions. The layer of tantalum carbide. The MOS transistor according to claim 13, further comprising: a second spacer wall located on a side of the dummy gate structure away from the source region or the drain region, adjacent to the source region on the surface of the source region A top surface of the dummy gate structure and a sidewall surface of the dummy gate structure adjacent to the source region are formed with a first interconnect layer. The MOS transistor according to claim 13, wherein a first interconnect layer is formed on a surface of the source region, a top portion of the dummy gate structure adjacent to the source region, and a sidewall surface. The MOS transistor according to claim 13, wherein when the sidewall of the dummy gate structure close to the source region or the drain region has a certain distance from the edge of the corresponding shallow trench isolation structure, the epitaxial process is used. The thickness of the interconnect layer is greater than the spacing between the sidewalls of the dummy gate structure near the source or drain side and the corresponding shallow trench isolation structure edges. The MOS transistor according to claim 13, wherein the dummy gate structure on the surface of the shallow trench isolation structure is connected as an interconnection structure to other MOS transistors. The MOS transistor according to claim 13, characterized in that the conductive plug on the dummy gate structure is such that the source region and the drain region are connected to the external circuit through the interconnect layer and the conductive plug. The MOS transistor according to claim 13, wherein the dummy gate structure portion is located on a surface of the shallow trench isolation structure and partially on a surface of the corresponding active region.