CN117832090A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a first fin part, and the first fin part comprises an isolation region; forming a first dielectric layer and a first grid structure on a substrate; forming a mask structure on the first dielectric layer, wherein the mask structure comprises a grinding stop layer and a mask layer; removing the first grid structure by taking the mask structure as a mask, and forming an isolation opening in the first dielectric layer; forming an initial isolation structure in the isolation opening and on the mask structure; and flattening the initial isolation structure until the grinding stop layer is exposed to form an isolation structure. The polishing stop layer is less consumed in the planarization process, and the surface of the first dielectric layer is flat after the polishing stop layer is removed. When the second dielectric layer is continuously formed on the first dielectric layer, the thickness of each part of the second dielectric layer can be kept consistent, and the height of the conductive plug connected with the first source-drain doped layer can be ensured to reach a preset height, so that the performance of the semiconductor structure is improved.

Description

Method for forming semiconductor structure

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.

Background

With the increase in the integration level of semiconductor devices, the critical dimensions of transistors are continually shrinking. However, as the transistor size decreases sharply, the gate first dielectric layer thickness and the operating voltage cannot be changed accordingly, which increases the difficulty in suppressing the short channel effect and increases the channel leakage current of the transistor.

The gates of Fin Field effect transistors (Fin Field-Effect Transistor, finFETs) are in a fork-like 3D architecture resembling a fish Fin. The channel of the FinFET protrudes out of the surface of the substrate to form a first fin portion, and the grid electrode covers the top surface and the side wall of the first fin portion, so that inversion layers are formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the first fin portion. This design can increase the control of the gate over the channel region, thereby well suppressing the short channel effect of the transistor. However, fin field effect transistors still have short channel effects.

In addition, to further reduce the effect of short channel effects on the semiconductor device, channel leakage current is reduced. The field of semiconductor technology introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the first fin parts at two sides of the grid structure; and forming a first source-drain doped region in the groove through an epitaxial growth process.

In order to prevent the first source and drain doped regions of different transistors from being connected to each other, an isolation layer needs to be formed in the first fin portion, and in order to reduce the area of the isolation layer, the integration level of the formed semiconductor structure is improved. The prior art incorporates SDB (Single Diffusion Break) technology.

However, the existing methods still have problems in forming semiconductor structures.

Disclosure of Invention

The invention solves the technical problem of providing a method for forming a semiconductor structure to improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a first fin part, the first fin part comprises a plurality of device regions and at least one isolation region, the device regions are arranged along a first direction, and the isolation region is positioned between adjacent device regions; forming a first dielectric layer and a first gate structure on the substrate, wherein the first gate structure spans the first fin part, the first gate structure is positioned on the isolation region, and the first dielectric layer covers the side wall of the first gate structure; forming a mask structure on the first dielectric layer, wherein a mask opening exposing the top surface of the first gate structure is formed in the mask structure, and the mask structure comprises a grinding stop layer and a mask layer positioned on the grinding stop layer; removing part of the grinding stop layer by using the mask structure as a mask and adopting a first etching process to form a blocking opening in the mask structure, wherein the blocking opening is exposed by the mask opening; forming a barrier layer within the barrier opening; after the barrier layer is formed, the mask structure is used as a mask, a second etching process is adopted to remove the first grid structure and part of the first fin portion covered by the first grid structure, and isolation openings are formed in the first dielectric layer and the first fin portion; forming an initial isolation structure within the isolation opening and over the mask structure; and flattening the initial isolation structure until the grinding stop layer is exposed, so as to form the isolation structure.

Optionally, the first etching process includes: wet etching process.

Optionally, the second etching process includes: wet etching process.

Optionally, the material of the polishing stop layer includes: tantalum nitride.

Optionally, the material of the mask layer includes: silicon oxide or silicon nitride.

Optionally, the material of the barrier layer includes: silicon nitride.

Optionally, the forming process of the barrier layer includes: atomic layer deposition process.

Optionally, in the process of forming the first dielectric layer and the first gate structure, the method further includes: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the first fin parts, the second gate structures are positioned on the device region, and the first dielectric layer covers the side walls of the second gate structures.

Optionally, before forming the first gate structure and the second gate structure, the method further includes: and forming a plurality of first source-drain doped layers in the first fin part, wherein the first source-drain doped layers are positioned between the adjacent first gate structure and the second gate structure or between the adjacent second gate structures.

Optionally, before forming the first source-drain doped layer, the method further includes: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure spans the first fin part, and the first dummy gate structure is positioned on the isolation region; and forming a plurality of second dummy gate structures on the substrate, wherein the second dummy gate structures cross the first fin parts, and the second dummy gate structures are positioned on the device region.

Optionally, the method for forming the first source-drain doped layer includes: etching the first fin portion by taking the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of first source drain openings in the first fin portion; and forming the first source-drain doping layer in the first source-drain opening.

Optionally, the forming method of the first gate structure and the plurality of second gate structures includes: removing the first dummy gate structure, and forming a first gate opening in the first dielectric layer; forming the first gate structure within the first gate opening; removing the second pseudo gate structure and forming a second gate opening in the first dielectric layer; the second gate structure is formed within the second gate opening.

Optionally, the material of the isolation structure includes silicon nitride.

Optionally, after forming the isolation structure, the method further includes: removing the polishing stop layer; forming a second dielectric layer on the first dielectric layer; and forming conductive plugs in the first dielectric layer and the second dielectric layer, wherein the conductive plugs are connected with the first source-drain doped layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the forming method of the technical scheme of the invention, by additionally forming the polishing stop layer, when the initial isolation structure is subjected to planarization treatment, the material of the polishing stop layer has a better polishing stop effect compared with the material of the initial isolation structure, the consumption of the polishing stop layer is less, and the surface of the first dielectric layer is flatter after the polishing stop layer is removed. When the second dielectric layer is formed on the first dielectric layer continuously, the thickness of the second dielectric layer can be kept consistent, and the height of the conductive plug connected with the first source-drain doped layer can reach a preset height, so that the performance of the finally formed semiconductor structure is improved.

In addition, in the subsequent process of removing the first gate structure, the adopted wet etching process has a relatively low etching selection of tungsten and titanium nitride, so that in order to avoid excessive loss of the grinding stop layer in the process of removing the first gate structure, a part of the grinding stop layer is removed by adopting the first etching process, a blocking opening is formed in the mask structure, and a blocking layer is formed in the blocking opening, so that the grinding stop layer can be blocked and protected, and excessive loss of the grinding stop layer in the subsequent process of removing the first gate structure is avoided.

Drawings

Fig. 1 to 3 are schematic structural views of a semiconductor structure;

fig. 4 to 21 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background, the prior art methods still have problems in forming semiconductor structures. The following will make a detailed description with reference to the accompanying drawings.

Fig. 1 to 3 are schematic structural views of a semiconductor structure.

Referring to fig. 1, the method includes: providing a substrate 100, wherein the substrate 100 is provided with a first fin portion 101, the first fin portion 101 comprises a first device region A1, a second device region A2 and a first isolation region B1 which are arranged along a first direction X, and the first isolation region B1 is positioned between adjacent first device region A1 and second device region A2; forming a first dielectric layer 102, a first gate structure 103 and a plurality of second gate structures 104 on the substrate 100, wherein the first gate structure 103 spans across the first fin 101 and is located on the first isolation region B1, the plurality of second gate structures 104 span across the first fin 101 and are located on the first device region A1 and the second device region A2, respectively, and the first dielectric layer 102 covers sidewalls of the first gate structure 103 and the second gate structure 104; a mask structure 105 is formed on the first dielectric layer 102, and a mask opening 106 exposing a top surface of the first gate structure 103 is formed in the mask structure 105.

Referring to fig. 2, the mask structure 105 is used as a mask, a wet etching process is used to remove the first gate structure 103 and a portion of the first fin portion 101 covered by the first gate structure 103, and isolation openings 107 are formed in the first dielectric layer 102 and the first fin portion 101.

Referring to fig. 3, an initial isolation structure (not shown) is formed in the isolation opening 107 and on the mask structure 105; the initial isolation structures are planarized until the top surface of the mask structure 105 is exposed, forming isolation structures 108.

In this embodiment, by forming the isolation structure 108, a problem of shorting between the first source-drain doped layers (not labeled) formed in the adjacent first fin portions 101 can be effectively prevented, thereby achieving an isolation effect.

In the above structure, the material of the mask structure 105 is a material that fills the cutting trench during the gate cutting process (not shown), and the material of the mask structure 105 is silicon oxide. The material of the initial isolation structure is silicon nitride, and when the initial isolation structure is planarized by a chemical mechanical polishing process, the mask structure 105 will serve as a polishing stop layer. However, since the polishing options for silicon oxide and silicon nitride are relatively close, silicon oxide is consumed simultaneously as a polishing stop layer for silicon nitride by a certain amount, which in turn results in a reduction in the thickness of the mask structure 105 that remains. In a subsequent process, a second dielectric layer (not shown) of the same material is deposited on the mask structure 105, and conductive plugs (not shown) are formed in the second dielectric layer, the mask structure 105 and the first dielectric layer 102, wherein the conductive plugs are connected to the first source/drain doped layers. Due to the reduced thickness of the mask structure 105, the overall thickness of the second dielectric layer and the mask structure 105 is smaller, and thus the height of the formed conductive plug is also smaller. When the conductive plugs have smaller heights, disconnection with the conductive layers formed later is easy to occur, and the performance of the finally formed semiconductor structure is further affected.

On the basis, the invention provides a method for forming a semiconductor structure, by additionally forming a polishing stop layer, when the initial isolation structure is subjected to planarization treatment, the material of the polishing stop layer has a better polishing stop effect compared with the material of the initial isolation structure, the consumption of the polishing stop layer is less, and the surface of the first dielectric layer is flatter after the polishing stop layer is removed. When the second dielectric layer is formed on the first dielectric layer continuously, the thickness of the second dielectric layer can be kept consistent, and the height of the conductive plug connected with the first source-drain doped layer can reach a preset height, so that the performance of the finally formed semiconductor structure is improved.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 4 to 21 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view taken along line A-A in fig. 4, fig. 4 is a top view of fig. 5, a substrate 200 is provided, the substrate 200 has a first fin 201 thereon, the first fin 201 includes a plurality of device regions arranged along a first direction X and at least one isolation region, and the isolation region is located between adjacent device regions.

In this embodiment, the plurality of device regions includes: a first device region A1 and a second device region A2; the at least one isolation region comprises: a first isolation region B1, where the first isolation region B1 is located between the first device region A1 and the second device region A2, and the first fin 101 extends from above the first device region A1 to above the second device region A2 and spans the isolation region B1.

In this embodiment, the substrate 200 includes a first region I, a second region II, and a third region III arranged along a second direction Y, the second region II being located between the first region I and the third region III, the first direction X being perpendicular to the second direction Y. The substrate 200 further has a second fin 202 thereon, the first fin 201 is located on the first region I, and the second fin 202 is located on the third region III.

In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.

In this embodiment, the material of the first fin 201 is silicon; in other embodiments, the material of the first fin may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

In this embodiment, the material of the second fin 202 is silicon; in other embodiments, the material of the first fin may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

Referring to fig. 6, the view directions of fig. 6 and fig. 5 are identical, an isolation layer 203 is formed on the substrate 200, the isolation layer 203 covers a portion of the sidewall of the first fin 201, and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201.

In this embodiment, the isolation layer 203 also covers a portion of the sidewall of the second fin 202, and the top surface of the isolation layer 203 is lower than the top surface of the second fin 202.

In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; and etching to remove part of the initial isolation layer to form the isolation layer 203.

The material of the isolation layer 203 is an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 203 is silicon oxide.

Referring to fig. 7, the view directions of fig. 7 and fig. 4 are consistent, a first dummy gate structure 204 is formed on the substrate 200, the first dummy gate structure 204 spans the first fin 201, and the first dummy gate structure 204 is located on the isolation region; a plurality of second dummy gate structures 205 are formed on the substrate 200, the second dummy gate structures 205 straddling the first fin 201, the second dummy gate structures 205 being located on the device region.

In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 also cross the second fin 202, respectively.

In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously by using a global process. The first dummy gate structure 204 is located on the first isolation region B1, and the plurality of second dummy gate structures 205 are located on the first device region A1 and the second device region A2, respectively.

In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 each include: a dummy gate first dielectric layer, and a dummy gate layer (not labeled) on the dummy gate first dielectric layer.

In this embodiment, the material of the first dielectric layer of the dummy gate is silicon oxide; in other embodiments, the dummy gate first dielectric layer material may also be silicon oxynitride.

In this embodiment, the dummy gate layer is made of polysilicon.

With continued reference to fig. 7, after forming the first dummy gate structure 204 and the second dummy gate structure 205, the method further includes: side walls (not shown) are formed on the side walls of the first dummy gate structure 204 and the second dummy gate structure 205, respectively.

In this embodiment, the material of the side wall is silicon nitride.

Referring to fig. 8, the first fin 201 is etched by using the first dummy gate structure 204 and the second dummy gate structure 205 as masks, and a plurality of first source-drain openings (not labeled) are formed in the first fin 201; the first source-drain doped layer 206 is formed within the first source-drain opening.

In this embodiment, in the process of forming the first source-drain doped layer 206, the method further includes: etching the second fin portion 202 by using the first dummy gate structure 204 and the second dummy gate structure 205 as masks, and forming a plurality of second source-drain openings (not labeled) in the second fin portion 202; the second source-drain doped layer 207 is formed within the second source-drain opening.

In this embodiment, the method for forming the first source-drain doped layer 206 in the first source-drain opening includes: forming a first epitaxial layer (not shown) in the first source drain opening by adopting an epitaxial growth process; the first source-drain doped layer 206 is formed by doping first source-drain ions into the epitaxial layer using an in-situ doping process during the formation of the first epitaxial layer.

In this embodiment, the method for forming the second source-drain doped layer 207 in the second source-drain opening includes: forming a second epitaxial layer (not shown) in the first source-drain opening by adopting an epitaxial growth process; and doping second source and drain ions into the epitaxial layer by adopting an in-situ doping process in the process of forming the second epitaxial layer to form the second source and drain doped layer 207.

In this embodiment, the electrical types of the first source-drain ion and the second source-drain ion are opposite, the first source-drain ion adopts N-type ion, and the second source-drain ion adopts P-type ion. In other embodiments, the first source-drain ions may also use P-type ions, and the second source-drain ions use N-type ions.

Referring to fig. 9, after the first source-drain doped layer 206 and the second source-drain doped layer 207 are formed, a first dielectric layer 208 is formed on the substrate 200, and the first dielectric layer 208 covers sidewalls of the first dummy gate structure 204 and the second dummy gate structure 205.

In this embodiment, the method for forming the first dielectric layer 208 includes: forming an initial first dielectric layer (not shown) on the substrate 200, wherein the initial first dielectric layer covers the first dummy gate structure 204 and the second dummy gate structure 205; the initial first dielectric layer is planarized until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, forming the first dielectric layer 208.

In this embodiment, the material of the first dielectric layer 208 is silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

Referring to fig. 10, the first dummy gate structure 204 is removed, and a first gate opening (not labeled) is formed in the first dielectric layer 208; forming the first gate structure 209 within the first gate opening; removing the second dummy gate structure 205, and forming a second gate opening (not labeled) in the first dielectric layer 208; the second gate structure 210 is formed within the second gate opening.

In this embodiment, the first gate structure 209 and the second gate structure 210 are formed simultaneously using a global process. The first gate structure 209 is located on the first isolation region B1, and the plurality of second gate structures 210 are located on the first device region A1 and the second device region A2, respectively.

In this embodiment, the first gate structure 209 and the second gate structure 210 each include: a gate first dielectric layer, a work function layer on the gate first dielectric layer, and a gate layer (not labeled) on the work function layer.

In this embodiment, the material of the gate first dielectric layer includes a high K dielectric material.

The material of the gate layer comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, tungsten is used as the material of the gate layer.

Referring to fig. 11 to 13, fig. 12 is a schematic cross-sectional view taken along line B-B in fig. 11, fig. 13 is a schematic cross-sectional view taken along line C-C in fig. 11, a polish stop layer 211 is formed on the first dielectric layer 208, and a first mask layer 212 is disposed on the polish stop layer 211, wherein the polish stop layer 211 and the first mask layer 212 have a patterned opening 213 therein exposing portions of the first dielectric layer 208, the first gate structure 209, and the second gate structure 210, the patterned opening 213 extends along the first direction X, and the patterned opening 213 is disposed on the second region II.

In this embodiment, the material of the polishing stop layer 211 is titanium nitride.

In this embodiment, the material of the first mask layer 212 is silicon oxide; in other embodiments, the material of the first mask layer may also be silicon nitride.

Referring to fig. 14, the view directions of fig. 14 and fig. 12 are the same, the polish stop layer 211 and the first mask layer 212 are used as masks, the first dielectric layer 208, the first gate structure 209 and the second gate structure 210 are etched, and a cutting trench 214 is formed on the second region II, where the cutting trench 214 penetrates through the first gate structure 209 and the second gate structure 210 along the first direction X, respectively.

In this embodiment, the cutting trench 214 is used to cut the first gate structure 209 that spans the first fin 201 and the second fin 202, and the second gate structure 210 that spans the first fin 201 and the second fin 202, respectively.

It should be noted that, during the process of etching the first dielectric layer 208, the first gate structure 209, and the second gate structure 210, the first mask layer 212 may be consumed simultaneously.

Referring to fig. 15, a partition material layer 215 is formed in the cutting groove 214 and on the polish stop layer 211.

In this embodiment, the partition material layer 215 on the polish stop layer 211 is a mask layer, and the polish stop layer 211 and the mask layer form a mask structure for subsequently removing the first gate structure 209 on the first region I.

Referring to fig. 16, the view directions of fig. 16 and fig. 13 are consistent, and a mask opening 216 exposing the top surface of the first gate structure 209 is formed in the mask structure; and taking the mask structure as a mask, removing part of the grinding stop layer 211 by adopting a first etching process, forming a blocking opening 217 in the mask structure, and exposing the blocking opening 217 through the mask opening 216.

In this embodiment, since the wet etching process used in the subsequent removal of the first gate structure 209 is used to etch tungsten and titanium nitride with a relatively low selectivity, in order to avoid excessive loss of the polish stop layer 211 during the removal of the first gate structure 209, the first etching process is used to remove a portion of the polish stop layer 211, and a blocking opening 217 is formed in the mask structure, and then a blocking layer is formed in the blocking opening 217, so that the polish stop layer 211 can be blocked and protected, and excessive loss of the polish stop layer 211 caused during the subsequent removal of the first gate structure 209 is avoided.

In this embodiment, the first etching process uses a wet etching process.

Referring to fig. 17, a barrier layer 218 is formed in the barrier opening 217.

In this embodiment, the barrier layer 218 is formed by an atomic layer deposition process.

In this embodiment, the material of the blocking layer 218 is silicon nitride.

Referring to fig. 18, after the barrier layer 218 is formed, the first gate structure 209 and a portion of the first fin 201 covered by the first gate structure 209 are removed by using the mask structure as a mask, and isolation openings 219 are formed in the first dielectric layer 208 and the first fin 201.

In this embodiment, the second etching process uses a wet etching process.

Note that, in this embodiment, the first mask layer 212 is also consumed completely in the process of removing the first gate structure 209 and a portion of the first fin 201.

Referring to fig. 19, an initial isolation structure 220 is formed within the isolation opening 219 and over the mask structure.

In this embodiment, the initial isolation structure 220 is formed by a chemical vapor deposition process.

In this embodiment, the material of the initial isolation structure 220 is silicon nitride.

Referring to fig. 20, the initial isolation structure 220 is planarized until the polish stop layer 211 is exposed, so as to form an isolation structure 221.

In this embodiment, the planarization process is performed on the initial isolation structure 220 by using a chemical mechanical polishing process.

Referring to fig. 21, after the isolation structures 221 are formed, the polish stop layer 211 is removed; forming a second dielectric layer 222 on the first dielectric layer 208; a conductive plug 223 is formed in the first dielectric layer 208 and the second dielectric layer 222, and the conductive plug 223 is connected to the first source-drain doped layer 206.

In this embodiment, by additionally forming the polish stop layer 211, when the planarization process is performed on the initial isolation structure 221, the material of the polish stop layer 211 has a better polish stop effect than the material of the initial isolation structure 221, the consumption of the polish stop layer 211 is less, and the surface of the first dielectric layer 208 is also flatter after the polish stop layer 211 is removed. When the second dielectric layer 222 is continuously formed on the first dielectric layer 208, it can be ensured that the thickness of the second dielectric layer 222 is consistent throughout, and the height of the conductive plug 223 connected with the first source-drain doped layer 206 reaches a predetermined height, so as to improve the performance of the finally formed semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a first fin part, the first fin part comprises a plurality of device regions and at least one isolation region, the device regions are arranged along a first direction, and the isolation region is positioned between adjacent device regions;

forming a first dielectric layer and a first gate structure on the substrate, wherein the first gate structure spans the first fin part, the first gate structure is positioned on the isolation region, and the first dielectric layer covers the side wall of the first gate structure;

forming a mask structure on the first dielectric layer, wherein a mask opening exposing the top surface of the first gate structure is formed in the mask structure, and the mask structure comprises a grinding stop layer and a mask layer positioned on the grinding stop layer;

removing part of the grinding stop layer by using the mask structure as a mask and adopting a first etching process to form a blocking opening in the mask structure, wherein the blocking opening is exposed by the mask opening;

forming a barrier layer within the barrier opening;

after the barrier layer is formed, the mask structure is used as a mask, a second etching process is adopted to remove the first grid structure and part of the first fin portion covered by the first grid structure, and isolation openings are formed in the first dielectric layer and the first fin portion;

forming an initial isolation structure within the isolation opening and over the mask structure;

and flattening the initial isolation structure until the grinding stop layer is exposed, so as to form the isolation structure.

2. The method of forming a semiconductor structure of claim 1, wherein the first etching process comprises: wet etching process.

3. The method of forming a semiconductor structure of claim 1, wherein the second etching process comprises: wet etching process.

4. The method of forming a semiconductor structure of claim 1, wherein the material of the polish stop layer comprises: tantalum nitride.

5. The method of forming a semiconductor structure of claim 1, wherein the material of the mask layer comprises: silicon oxide or silicon nitride.

6. The method of forming a semiconductor structure of claim 1, wherein the material of the barrier layer comprises: silicon nitride.

7. The method of forming a semiconductor structure of claim 1, wherein the process of forming the barrier layer comprises: atomic layer deposition process.

8. The method of forming a semiconductor structure of claim 1, wherein the material of the isolation structure comprises silicon nitride.

9. The method of forming a semiconductor structure of claim 1, further comprising, during forming the first dielectric layer and the first gate structure: and forming a plurality of second gate structures on the substrate, wherein the second gate structures cross the first fin parts, the second gate structures are positioned on the device region, and the first dielectric layer covers the side walls of the second gate structures.

10. The method of forming a semiconductor structure of claim 9, further comprising, prior to forming the first gate structure and the second gate structure: and forming a plurality of first source-drain doped layers in the first fin part, wherein the first source-drain doped layers are positioned between the adjacent first gate structure and the second gate structure or between the adjacent second gate structures.

11. The method of forming a semiconductor structure of claim 10, further comprising, after forming the isolation structure: removing the polishing stop layer; forming a second dielectric layer on the first dielectric layer; and forming conductive plugs in the first dielectric layer and the second dielectric layer, wherein the conductive plugs are connected with the first source-drain doped layer.

12. The method of forming a semiconductor structure of claim 10, further comprising, prior to forming the first source drain doped layer: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure spans the first fin part, and the first dummy gate structure is positioned on the isolation region; and forming a plurality of second dummy gate structures on the substrate, wherein the second dummy gate structures cross the first fin parts, and the second dummy gate structures are positioned on the device region.

13. The method of forming a semiconductor structure of claim 12, wherein the method of forming a first source drain doped layer comprises: etching the first fin portion by taking the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of first source drain openings in the first fin portion; and forming the first source-drain doping layer in the first source-drain opening.

14. The method of forming a semiconductor structure of claim 12, wherein the method of forming the first gate structure and the plurality of second gate structures comprises: removing the first dummy gate structure, and forming a first gate opening in the first dielectric layer; forming the first gate structure within the first gate opening; removing the second pseudo gate structure and forming a second gate opening in the first dielectric layer; the second gate structure is formed within the second gate opening.