CN115881618A - Manufacturing method of semiconductor structure and semiconductor structure - Google Patents
Manufacturing method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN115881618A CN115881618A CN202111144913.7A CN202111144913A CN115881618A CN 115881618 A CN115881618 A CN 115881618A CN 202111144913 A CN202111144913 A CN 202111144913A CN 115881618 A CN115881618 A CN 115881618A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 159
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000002360 preparation method Methods 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 23
- 239000010410 layer Substances 0.000 description 246
- 239000011241 protective layer Substances 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 9
- 230000001590 oxidative effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- -1 region Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a first substrate and a second prepared substrate, wherein the first substrate comprises a buried oxide layer and a first oxide layer, the second prepared substrate comprises a first substrate and a trap rich layer which are sequentially overlapped, and the trap rich layer comprises a body structure and at least one prepared groove positioned in the body structure; forming a second oxide layer on the exposed surface of the trap rich layer, and forming a groove by the residual preparation groove to obtain a second substrate; and bonding the first substrate and the second substrate by taking the first oxide layer and the second oxide layer on the preset surface as bonding interfaces to obtain a bonding structure, wherein the preset surface is the surface of the body structure far away from the first substrate. The scheme not only solves the problem of large parasitic capacitance of the SOI wafer in the prior art, but also ensures that the performance of the wafer structure is stable.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
The conventional SOI wafer is shown in fig. 1: the SOI wafer comprises an SOI silicon layer 102, an insulating silicon oxide layer 101, and a silicon substrate layer 100 stacked in this order. The insulating silicon oxide layer in the conventional SOI wafer structure is a complete layer, and larger parasitic capacitance is generated, so that the application of the conventional SOI wafer structure in the high-frequency field is limited.
Therefore, a method for reducing the parasitic capacitance of the SOI wafer is needed.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a method for fabricating a semiconductor structure and a semiconductor structure, so as to solve the problem of large parasitic capacitance of an SOI wafer in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a semiconductor structure, including: providing a first substrate and a second preparation substrate, wherein the first substrate comprises a buried oxide layer and a first oxide layer, the second preparation substrate comprises a first substrate and a trap rich layer which are sequentially stacked, and the trap rich layer comprises a body structure and at least one preparation groove in the body structure; forming a second oxide layer on the exposed surface of the trap-rich layer, and forming a groove in the residual preparation groove to obtain a second substrate; and bonding the first base and the second base by taking the first oxidation layer and the second oxidation layer on the preset surface as bonding interfaces to obtain a bonding structure, wherein the preset surface is the surface, far away from the first substrate, of the body structure.
Optionally, providing a second preparation substrate comprising: providing a first substrate; sequentially forming a prepared trap rich layer and a graphical mask layer on the exposed surface of the first substrate; etching the prepared trap-rich layer by taking the graphical mask layer as a mask so as to form at least one prepared groove; and removing the patterned mask layer to obtain the second preparation substrate.
Optionally, forming a preliminary trap rich layer on the exposed surface of the first substrate comprises: forming an amorphous silicon film on the exposed surface of the first substrate; and annealing the amorphous silicon thin film to obtain the prepared trap rich layer.
Optionally, forming a second oxide layer on the exposed surface of the trap rich layer, and forming a groove in the remaining preliminary groove to obtain a second substrate, including: forming a second preliminary oxide layer on the exposed surface of the trap rich layer in a space with a protective gas, wherein the protective gas comprises an inert gas, so as to obtain at least one groove; and carrying out chemical mechanical polishing on the second preliminary substrate with the second preliminary oxide layer so as to remove part of the second preliminary oxide layer on the preset surface, wherein the rest of the second preliminary oxide layer forms the second oxide layer, and the second substrate is obtained.
Optionally, with the first oxide layer and the second oxide layer on the predetermined surface as bonding interfaces, bonding the first substrate and the second substrate to obtain a bonding structure, including: bonding the first substrate and the second substrate by taking the first oxide layer and the second oxide layer on the preset surface as the bonding interface to obtain a prepared bonding structure; and removing at least part of the buried oxide layer of the preliminary bonding structure to obtain the bonding structure.
Optionally, the groove depth of the groove ranges from 200nm to 2um.
Optionally, the thickness of the second oxide layer on the predetermined surface ranges from 1nm to 50nm.
According to another aspect of the present application, there is provided a semiconductor structure fabricated by any of the methods described herein.
According to yet another aspect of the present application, there is also provided a semiconductor structure comprising: the bonding structure comprises a first base and a second base, wherein the first base comprises a buried oxide layer and a first oxide layer which are overlapped, the second base comprises a first substrate, a trap rich layer and a second oxide layer, the trap rich layer is located on the surface of the first substrate, the second oxide layer is located on the surface of the trap rich layer far away from the first substrate, the trap rich layer comprises a body structure and at least one preparation groove located in the body structure, the first oxide layer and the second oxide layer on a preset surface are bonding interfaces of the bonding structure, and the preset surface is the surface of the body structure far away from the first substrate.
Optionally, the material of the trap rich layer includes at least one of polysilicon and SiGe, and the material of the first oxide layer and the material of the second oxide layer both include silicon dioxide.
According to the technical scheme, in the manufacturing method of the semiconductor structure, firstly, a first substrate and a second preliminary substrate which comprise a buried oxide layer and a first oxide layer are provided, wherein the second preliminary substrate comprises a first substrate and a trap rich layer which are sequentially overlapped, the trap rich layer comprises a body structure and at least one preliminary groove in the body structure, then a second oxide layer is formed on the exposed surface of the trap rich layer, the rest preliminary grooves form grooves to obtain the second substrate, and finally the first substrate and the second substrate are bonded by taking the first oxide layer and the second oxide layer on a preset surface as bonding interfaces to obtain the bonding structure. In the scheme, the second oxide layer is formed on the exposed surface of the trap rich layer, namely, the protective layers are formed on the bottom and the side wall of the preparation groove, the protective layers can prevent water and oxygen in the groove from oxidizing the inside of the groove, the first oxide layer and the second oxide layer on the preset surface are used as bonding interfaces, the first substrate and the second substrate are bonded, the bonding structure is obtained, and the stability of the performance of the bonding structure is guaranteed. Compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 illustrates a wafer plan cross-sectional view in the prior art;
FIG. 2 illustrates a flow diagram of a method of fabricating a semiconductor structure according to an embodiment of the present application;
fig. 3 to 9 respectively show schematic views of semiconductor structures formed after various process steps according to a method for manufacturing a semiconductor structure of an embodiment of the present application;
fig. 10 shows a schematic diagram of a high frequency device made of a semiconductor structure of the present application.
Wherein the figures include the following reference numerals:
100. a silicon substrate layer; 101. an insulating silicon oxide layer; 102. an SOI silicon layer; 103. a first substrate; 104. preparing a trap rich layer; 105. patterning the mask layer; 106. preparing a groove; 107. a second oxide layer; 108. a trap rich layer; 109. a groove; 110. oxidizing the buried layer; 111. a first oxide layer; 200. a back electrode; 201. a source electrode; 202. a gate electrode; 203. a drain electrode; 204. a drift region.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, in order to solve the above problems, the present application provides a method for fabricating a semiconductor structure and a semiconductor structure.
In an exemplary embodiment of the present application, a method of fabricating a semiconductor structure is provided. Fig. 2 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application, the method of fabricating the semiconductor structure including, as shown in fig. 2:
step S101, providing a first substrate and a second preliminary substrate, where the first substrate includes a buried oxide layer and a first oxide layer, the second preliminary substrate includes a first substrate and a trap rich layer stacked in sequence, and the trap rich layer includes a body structure and at least one preliminary groove in the body structure;
step S102, forming a second oxide layer on the exposed surface of the trap rich layer, and forming a groove by the residual preparation groove to obtain a second substrate;
step S103 bonds the first base and the second base with the first oxide layer and the second oxide layer on a predetermined surface as a bonding interface, and obtains a bonded structure, where the predetermined surface is a surface of the bulk structure away from the first substrate.
In the method for manufacturing the semiconductor structure, first, a first substrate including a buried oxide layer and a first oxide layer and a second preliminary substrate are provided, wherein the second preliminary substrate includes a first substrate and a trap rich layer stacked in sequence, the trap rich layer includes a body structure and at least one preliminary groove located in the body structure, then, a second oxide layer is formed on an exposed surface of the trap rich layer, the remaining preliminary grooves form grooves to obtain the second substrate, and finally, the first substrate and the second substrate are bonded by using the first oxide layer and the second oxide layer on a predetermined surface as bonding interfaces to obtain the bonding structure. In the scheme, the second oxide layer is formed on the exposed surface of the trap rich layer, namely, the protective layer is formed on the bottom and the side wall of the preliminary groove, the protective layer can prevent the water oxygen in the groove from oxidizing the inside of the groove, the first oxide layer and the second oxide layer on the preset surface are used as bonding interfaces, the first substrate and the second substrate are bonded, the bonding structure is obtained, and the stability of the performance of the bonding structure is guaranteed. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
In the practical application process, the number of the grooves is not limited, and in the specific use process, the number of the grooves, the positions of the grooves and the sizes of the grooves can be set according to the actual manufacturing process or the circuit design requirement.
In one embodiment of the present application, as shown in fig. 3, 4, 5 and 6, providing the second preliminary substrate includes: providing a first substrate 103; sequentially forming a prepared trap rich layer 104 and a patterned mask layer 105 on the exposed surface of the first substrate 103; etching the preliminary trap rich layer 104 by using the patterned mask layer 105 as a mask to form at least one preliminary groove 106, and forming the trap rich layer 108 by using the remaining preliminary trap rich layer 104; the patterned mask layer 105 is removed to obtain the second preliminary substrate. Specifically, in the scheme, the patterned mask layer 105 is used as a mask to etch the preliminary trap rich layer 104 to form at least one preliminary groove 106, so that the parasitic capacitance of the subsequently obtained bonding structure is further ensured to be small, the second preliminary substrate is ensured to be obtained easily and simply, and the manufacturing process of the second predetermined substrate is ensured to be simple.
In a specific embodiment of the present application, the first substrate may be a high resistance substrate, and may also be a low resistance substrate, and of course, the first substrate is not limited to the high resistance substrate and the low resistance substrate, and may also be another substrate. The patterned mask layer may be a photoresist layer, but of course, it may also be other materials.
In practical applications, the position of the preliminary groove may be determined according to the requirements of an actual device or circuit, and the position of the preliminary groove is not limited in this application. The method for etching the preliminary trap rich layer to form at least one preliminary groove may be dry etching, wet etching, or mixed dry and wet etching, but is not limited to dry etching, wet etching, or mixed dry and wet etching, and may be other grooving methods. Secondly, the depth of the preliminary groove may be determined according to the design requirements of the device or the circuit.
In practical applications, the preliminary trap rich layer may include any feasible material in the prior art, such as polysilicon, siC, siGe, etc., and those skilled in the art can flexibly select the material of the preliminary trap rich layer according to actual needs. In order to ensure that the manufacturing process of the preliminary trap rich layer is simple and further ensure that the preliminary trap rich layer is easily obtained, in a specific embodiment of the present application, the material of the preliminary trap rich layer is polysilicon, and the forming the preliminary trap rich layer on the exposed surface of the first substrate includes: forming an amorphous silicon film on the exposed surface of the first substrate; and annealing the amorphous silicon thin film to obtain the prepared trap rich layer.
Specifically, the prepared trap-rich layer has a large number of interface states, the interface states are carrier traps, and the carrier traps can capture carriers, so that the carriers are prevented from generating substrate crosstalk, and the good performance of the device is further ensured.
In another embodiment of the present application, as shown in fig. 7, a second oxide layer 107 is formed on the exposed surface of the trap rich layer 108, and the remaining preliminary grooves form grooves 109, so as to obtain a second substrate, including: forming a second preliminary oxide layer on the exposed surface of said trap rich layer 108 in a space with a protective gas, resulting in at least one of said recesses 109, said protective gas comprising an inert gas; the second preliminary substrate on which the second preliminary oxide layer is formed is subjected to chemical mechanical polishing to remove a portion of the second preliminary oxide layer on the predetermined surface, and the remaining second preliminary oxide layer forms the second oxide layer 107, thereby obtaining the second substrate. In the scheme, in the space with the protective gas, the second preliminary oxide layer is formed on the exposed surface of the trap rich layer 108 to obtain at least one groove 109, so that it is further ensured that no water oxygen remains between the trap rich layer 108 and the groove 109, further oxidation of the water oxygen in the groove 109 to the inside of the groove is avoided, the second preliminary substrate with the second preliminary oxide layer is subsequently subjected to chemical mechanical polishing, and a part of the second preliminary oxide layer on the predetermined surface is removed, so that the surface of the second preliminary oxide layer is ensured to be smooth, and further the subsequent bonding process is facilitated.
In a specific embodiment of the present application, an oxide material may be deposited on an exposed surface of the trap rich layer, or the trap rich layer may be thermally oxidized, so that the trap rich layer on the surface forms the second preliminary oxide layer. In addition, in the present application, the manner of removing the portion of the second preliminary oxide layer on the predetermined surface is not limited to the above chemical mechanical polishing, and the portion of the second preliminary oxide layer on the predetermined surface may be removed by other methods such as physical or physical and chemical combination.
In practical applications, the protective gas may be an inert gas, but is not limited to the inert gas, and may be other gases, i.e., gases that do not react with the trap rich layer.
As shown in fig. 8 and 9, in another embodiment of the present invention, a bonding structure is obtained by bonding the first substrate and the second substrate using the first oxide layer 111 and the second oxide layer 107 on a predetermined surface as a bonding interface, and includes: bonding the first substrate and the second substrate with the first oxide layer 111 and the second oxide layer 107 on the predetermined surface as the bonding interface to obtain a preliminary bonding structure; and removing at least a part of the buried oxide layer 110 of the preliminary bonding structure to obtain the bonding structure.
In a specific embodiment of the present application, the materials of the first oxide layer and the second oxide layer may be the same, and of course, the materials of the first oxide layer and the second oxide layer may also be different. Under the condition that the materials of the first oxide layer and the second oxide layer are the same, the manufacturing process can be further ensured to be easy.
In another specific embodiment of the present application, a portion of the buried oxide layer of the preliminary bonding structure may be removed by a physical or a physical-chemical combination method.
In order to achieve both a smaller parasitic capacitance and a better structural stability, in an embodiment of the present application, as shown in fig. 8, a groove depth L of the groove is in a range of 200nm to 2um. This further ensures that the parasitic capacitance of the entire bonding structure is small. Of course, the groove depth of the groove is not limited to the above numerical range, and those skilled in the art may design the groove with a deeper groove depth to further reduce the parasitic capacitance.
According to another specific embodiment of the present application, as shown in fig. 8, there may be two or more grooves, and the body structure between two adjacent grooves serves as a supporting pillar, so as to ensure that the structural stability of the whole bonding structure is good.
In another embodiment of the present application, the thickness of the second oxide layer on the predetermined surface is in a range of 1nm to 50nm, and the first substrate and the second substrate are bonded using the first oxide layer and the second oxide layer on the predetermined surface as a bonding interface, so that the bonding effect is ensured to be good.
In another exemplary embodiment of the present application, a semiconductor structure is provided, which is manufactured by any one of the above methods.
The semiconductor structure is obtained by any one of the methods for manufacturing a semiconductor structure, wherein the method for manufacturing a semiconductor comprises the steps of firstly, providing a first substrate and a second preliminary substrate, wherein the first substrate and the second preliminary substrate comprise a buried oxide layer and a first oxide layer, the first substrate and the second preliminary substrate are sequentially stacked, the trap-rich layer comprises a body structure and at least one preliminary groove located in the body structure, then, forming a second oxide layer on an exposed surface of the trap-rich layer, forming grooves in the rest preliminary grooves to obtain the second substrate, and finally, bonding the first substrate and the second substrate by using the first oxide layer and the second oxide layer on a preset surface as bonding interfaces to obtain the bonding structure. In the scheme, the second oxide layer is formed on the exposed surface of the trap rich layer, namely, the protective layer is formed on the bottom and the side wall of the preliminary groove, the protective layer can prevent the water oxygen in the groove from oxidizing the inside of the groove, the first oxide layer and the second oxide layer on the preset surface are used as bonding interfaces, the first substrate and the second substrate are bonded, the bonding structure is obtained, and the stability of the performance of the bonding structure is guaranteed. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
In yet another exemplary embodiment of the present application, there is also provided a semiconductor structure, including: the bonding structure comprises a first base and a second base, wherein the first base comprises a buried oxide layer and a first oxide layer which are overlapped, the second base comprises a first substrate, a trap rich layer and a second oxide layer, the trap rich layer is positioned on the surface of the first substrate, the second oxide layer is positioned on the surface, far away from the first substrate, of the trap rich layer, the trap rich layer comprises a body structure and at least one preliminary groove positioned in the body structure, the first oxide layer and the second oxide layer on a preset surface are bonding interfaces of the bonding structure, and the preset surface is the surface, far away from the first substrate, of the body structure.
The semiconductor structure includes a bonding structure, the bonding structure includes a first base and a second base, the first base includes a buried oxide layer and a first oxide layer stacked, the second base includes a first substrate, a trap rich layer and a second oxide layer, the trap rich layer is located on a surface of the first substrate, the second oxide layer is located on a surface of the trap rich layer far away from the first substrate, the trap rich layer includes a body structure and at least one preliminary groove located in the body structure, the first oxide layer and the second oxide layer on a predetermined surface are bonding interfaces of the bonding structure, and the predetermined surface is a surface of the body structure far away from the first substrate. In this embodiment, the second oxide layer is located on a surface of the trap rich layer away from the first substrate, the trap rich layer includes at least one preliminary groove located in the body structure, that is, a protective layer is formed on a bottom and a sidewall of the preliminary groove, the protective layer can prevent oxidation of water and oxygen in the groove to an inside of the groove, and then the first oxide layer and the second oxide layer on the predetermined surface are used as a bonding interface to bond the first base and the second base, so as to obtain a bonding structure, thereby ensuring that the performance of the bonding structure is stable. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
In an embodiment of the present invention, the material of the trap rich layer includes at least one of polysilicon and SiGe, and the material of the first oxide layer and the material of the second oxide layer both include silicon dioxide. Of course, the material of the trap rich layer is not limited to the above-mentioned polysilicon and SiGe, and may be any other material that is feasible in the prior art, and the material of the first oxide layer and the second oxide layer is not limited to the above-mentioned silicon dioxide. In a more specific embodiment of the present invention, the trap rich layer is a polysilicon layer or a SiGe layer, and the first oxide layer and the second oxide layer are silicon dioxide layers.
In a specific embodiment, the semiconductor structure can be applied to the design and manufacture of high frequency devices, as shown in fig. 10. A back electrode 200, a source electrode 201, a gate electrode 202 and a drain electrode 203 are formed on the bonding structure of the present application, a drift region 204 is formed between the gate electrode 202 and the drain electrode 203, the groove 109 (i.e., a cavity) is arranged below the drift region 204 and the drain electrode 203 according to the requirements of the device, and due to the existence of the cavity below the drift region 204 and the drain electrode 203, the lightly doped drain structure junction of the laterally diffused metal oxide semiconductor is deeply contacted to the oxide layer on the cavity wall, so that the source-drain capacitance is reduced, the parasitic capacitance is reduced, the total output capacitance of the circuit can be significantly reduced, and the high-frequency performance and efficiency of the laterally diffused metal oxide semiconductor are improved.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) The method for manufacturing the semiconductor structure includes the steps of firstly, providing a first substrate and a second preliminary substrate, wherein the first substrate and the second preliminary substrate comprise a buried oxide layer and a first oxide layer, the first substrate and the second preliminary substrate are sequentially stacked, the trap rich layer comprises a body structure and at least one preliminary groove located in the body structure, then, forming a second oxide layer on an exposed surface of the trap rich layer, forming grooves in the rest preliminary grooves to obtain the second substrate, and finally, bonding the first substrate and the second substrate by using the first oxide layer and the second oxide layer on a preset surface as bonding interfaces to obtain the bonding structure. In the scheme, the second oxide layer is formed on the exposed surface of the trap rich layer, namely, the protective layers are formed on the bottom and the side wall of the preliminary groove, the protective layers can prevent water and oxygen in the groove from oxidizing the inside of the groove, the first oxide layer and the second oxide layer on the preset surface are used as bonding interfaces, the first substrate and the second substrate are bonded, the bonding structure is obtained, and the stability of the performance of the bonding structure is guaranteed. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
2) The semiconductor structure is obtained by adopting any one semiconductor structure manufacturing method, wherein in the semiconductor manufacturing method, firstly, a first substrate and a second preliminary substrate which comprise a buried oxide layer and a first oxide layer are provided, wherein the second preliminary substrate comprises a first substrate and a trap rich layer which are sequentially stacked, the trap rich layer comprises a body structure and at least one preliminary groove which is positioned in the body structure, then, a second oxide layer is formed on the exposed surface of the trap rich layer, the rest of the preliminary grooves form grooves to obtain a second substrate, and finally, the first substrate and the second substrate are bonded by taking the first oxide layer and the second oxide layer on a preset surface as bonding interfaces to obtain a bonding structure. In the scheme, the second oxide layer is formed on the exposed surface of the trap rich layer, namely, the protective layers are formed on the bottom and the side wall of the preliminary groove, the protective layers can prevent water and oxygen in the groove from oxidizing the inside of the groove, the first oxide layer and the second oxide layer on the preset surface are used as bonding interfaces, the first substrate and the second substrate are bonded, the bonding structure is obtained, and the stability of the performance of the bonding structure is guaranteed. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
3) The semiconductor structure comprises a bonding structure, wherein the bonding structure comprises a first base and a second base, the first base comprises a buried oxide layer and a first oxide layer which are stacked, the second base comprises a first substrate, a trap rich layer and a second oxide layer, the trap rich layer is located on the surface of the first substrate, the second oxide layer is located on the surface of the trap rich layer far away from the first substrate, the trap rich layer comprises a body structure and at least one preparation groove located in the body structure, the first oxide layer and the second oxide layer on a preset surface are bonding interfaces of the bonding structure, and the preset surface is the surface of the body structure far away from the first substrate. In this embodiment, the second oxide layer is located on a surface of the trap rich layer away from the first substrate, the trap rich layer includes at least one preliminary groove located in the body structure, that is, a protective layer is formed on a bottom and a sidewall of the preliminary groove, the protective layer can prevent oxidation of water and oxygen in the groove to an inside of the groove, and then the first oxide layer and the second oxide layer on the predetermined surface are used as a bonding interface to bond the first base and the second base, so as to obtain a bonding structure, thereby ensuring that the performance of the bonding structure is stable. And compared with the prior art that the insulating silicon oxide layer of the SOI wafer is a complete layer, the bonding structure comprises the groove, so that the parasitic capacitance of the bonding structure is ensured to be smaller, and the problem that the parasitic capacitance of the SOI wafer is larger in the prior art is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a first substrate and a second preparation substrate, wherein the first substrate comprises a buried oxide layer and a first oxide layer, the second preparation substrate comprises a first substrate and a trap rich layer which are sequentially stacked, and the trap rich layer comprises a body structure and at least one preparation groove in the body structure;
forming a second oxide layer on the exposed surface of the trap-rich layer, and forming a groove in the residual preparation groove to obtain a second substrate;
and bonding the first substrate and the second substrate by taking the first oxide layer and the second oxide layer on the predetermined surface as bonding interfaces to obtain a bonding structure, wherein the predetermined surface is the surface of the body structure far away from the first substrate.
2. The method of claim 1, wherein providing a second preliminary substrate comprises:
providing a first substrate;
sequentially forming a prepared trap rich layer and a graphical mask layer on the exposed surface of the first substrate;
etching the prepared trap-rich layer by taking the graphical mask layer as a mask so as to form at least one prepared groove;
and removing the patterned mask layer to obtain the second preparation substrate.
3. The method of claim 2, wherein forming a preliminary trap rich layer on an exposed surface of the first substrate comprises:
forming an amorphous silicon film on the exposed surface of the first substrate;
and annealing the amorphous silicon thin film to obtain the prepared trap rich layer.
4. The method of claim 1, wherein forming a second oxide layer on exposed surfaces of the trap rich layer and the remaining preliminary grooves form grooves, resulting in a second substrate comprising:
forming a second preliminary oxidation layer on the exposed surface of the trap rich layer in a space with a protective gas to obtain at least one groove, wherein the protective gas comprises an inert gas;
and carrying out chemical mechanical polishing on the second preparation substrate with the second preparation oxidation layer so as to remove part of the second preparation oxidation layer on the preset surface, wherein the rest of the second preparation oxidation layer forms the second oxidation layer, and the second substrate is obtained.
5. The method of claim 1, wherein bonding the first substrate and the second substrate with the first oxide layer and the second oxide layer on a predetermined surface as a bonding interface to obtain a bonded structure comprises:
bonding the first substrate and the second substrate by taking the first oxidation layer and the second oxidation layer on the preset surface as bonding interfaces to obtain a prepared bonding structure;
and removing at least part of the buried oxide layer of the preliminary bonding structure to obtain the bonding structure.
6. The method according to any one of claims 1 to 5, wherein the grooves have a groove depth in the range of 200nm to 2um.
7. The method according to any one of claims 1 to 5, wherein the thickness of the second oxide layer on the predetermined surface is in a range of 1nm to 50nm.
8. A semiconductor structure, wherein the semiconductor structure is fabricated by the method of any one of claims 1 to 7.
9. A semiconductor structure, comprising:
the bonding structure comprises a first base and a second base, wherein the first base comprises a buried oxide layer and a first oxide layer which are overlapped, the second base comprises a first substrate, a trap rich layer and a second oxide layer, the trap rich layer is located on the surface of the first substrate, the second oxide layer is located on the surface of the trap rich layer far away from the first substrate, the trap rich layer comprises a body structure and at least one preparation groove located in the body structure, the first oxide layer and the second oxide layer on a preset surface are bonding interfaces of the bonding structure, and the preset surface is the surface of the body structure far away from the first substrate.
10. The semiconductor structure of claim 9, wherein the material of the trap rich layer comprises at least one of polysilicon and SiGe, and the material of the first oxide layer and the second oxide layer each comprises silicon dioxide.
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