TW513755B - Manufacture method of semiconductor device with self-aligned inter-well isolation - Google Patents

Abstract

This invention provides a manufacture method of semiconductor device with self-aligned inter-well isolation, which includes the following steps: forming an embedded insulation layer and a semiconductor layer on a semiconductor substrate; growing a pad oxide layer on the semiconductor layer; forming a hard-mask layer on the pad oxide layer; forming an inter-well isolation region and an intra-well isolation region on the hard-mask layer, the pad oxide layer and part of the semiconductor layer; forming a shielding layer on the hard-mask layer to expose the inter-well isolation region; removing the semiconductor layer in the inter-well isolation region in a self-aligned manner; removing the shielding layer; and forming a insulation layer to fill the inter-well isolation region and the intra-well isolation region.

Description

513755 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with self-aligned interwell isolation. At present, in the field of integrated circuit process technology, a technology having a silicon on insulator (SOI) on an insulator is being widely used. It is to form a transistor on a semiconductor material covered on an insulating layer. This technology is becoming more and more important in the field of integrated circuit development. Compared to fabricating integrated circuit elements on a thin SOI layer, compared with fabricating the same IC element in a thicker silicon structure, lower parasitic capacitance and larger channel current can be obtained, so its speed is faster. Furthermore, field-effect transistors, such as metal-oxide half-field-effect transistors (MOSFETs), located on the silicon layer of the SiO structure, have more advantages than the MOSFETs fabricated on the traditional Shixi substrate, including: Resistance to short-channel effects, steeper subthreshold slopes, increased current drive, higher package density, reduced parasitic capacitance, and simple process steps. In addition, recent advances in the quality of silicon layers, buried oxides, and yields of SOI have made it possible to manufacture very large integrated circuit elements below 0.1 micron. Since the SO I structure effectively reduces the parasitic element ’and increases the tolerance of the structural abutment interface collapse, the SOI technology is suitable for high-efficiency and high-density integrated circuits.

Choi et al. In U.S. Patent No. 5,899, 7 1 2nMethod for _ fabricating silicon-on-insulator device π, discloses a partial isolation technique for intra-wel 1. Koh et al., US Patent 5,985,733 " Semiconductor device having a T-shaped field oxide layer and a method for

0503-6150TWF; TSMC2000-0940,0941; ycchen.ptd Page 5 513755 V. Description of the invention (2) Fabricating the same ", revealing an inter-well T-type field oxide layer isolation technology. Lee et al. The "Performance Improvements in High-Density DRAM Application using 0.15 β \ Ά Body-Contacted SOI Technology" published by the 2000 IEEE International SOI Conference, Oct · 200 0 ρρ · 76-77, proposed 0.15 / zm dynamic randomization Partial isolation technology for accessing memory. H i gash i and others in

Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2 0 0 0 pp 376-377, "Ultra-Low Standby Current in ^ SOI-CMOS LSI Circuits by Using Body-Bias-Control Technology" , Proposed a dual-zone oxidation isolation technology for a 16-bit CPU (0.35 // m). Please refer to Figures 1 A to 1 D, which shows a cross-sectional view of the process of a conventional manufacturing method. As shown in Figure 1A, A semiconductor substrate 10 has a buried insulating layer 12 and a semiconductor layer 14 with silicon (SOI) on the insulator as a starting material. Then, a pad oxide is grown on the semiconductor layer 4 After layer 16, a silicon nitride layer 8 is deposited on the pad oxide layer 6. Then, as shown in FIG. 1B, a lithography and surname process is performed to define the nitrogen < fossil evening layer 18 and the pad The oxide layer 16 is used to form the interwell isolation area 2000 and the intrawell isolation area 22. Furthermore, as shown in FIG. 1C, a regional oxidation process is performed on the semiconductor substrate 10 so that the interwell isolation area 20 and Semiconductor layer in the well isolation region 22

0503-6150TW; TSMC2000-0940, 0941; ycchen.ptd Page 6 513755 V. Description of the invention (3) 1 4 is oxidized to form a silicon oxide layer 24 to form a continuous insulating layer with the buried insulating layer 12. Finally, as shown in FIG. 1D, the silicon nitride layer 18 is removed. The SO I integrated circuit element process uses an area oxidation method to form an insulation layer to isolate the N well area, the P well area, and the well area. If the well is partially isolated, the well body (wel Ι-body) can be biased with the body. (B〇dy bias) is connected to each other, and the full isolation between the wells can eliminate the interaction between the wells, such as locking for discussion = lk n〇ise), etc., resulting in a reduced parasitic capacitance of the soi integrated circuit. advantage. To achieve full isolation between wells and partial isolation within the wells, if an eight-step formation of an interwell and an inner insulation layer, namely a single still knife r- ,. is done to form a command zone between the wells, a increase the number of masks and process steps And misalignment can occur. In order to solve the complexity of the manufacturing process, in order to solve the above problems, the semiconductor element of the self-aligned metal source / drain electrode of the present invention provides a method with a self-aligned metal source / electrode instead of the traditional stone chip replacement method. It utilizes temperature and reduces parasitic resistance. " Miscellaneous sources and electrodes to reduce activity. Therefore, the present invention provides a method for manufacturing a self-contained device, which includes the following steps: aligning a semiconducting layer between wells to form a buried insulating layer and a semiconductor layer; A semiconductor layer is formed on the semiconductor substrate; on the pad oxide layer, the semiconductor layer is grown into an oxygen pad layer, the pad oxide layer, and a part of the conductive hard mask layer; the hard mask is isolated in a well. Layer; on this hard cover curtain layer] layer to form an inter-well isolation zone and inter-isolation zone; self-align to reduce two% to form a shielding layer and expose the semiconductor layer in the well a-m open space hidden charm area ;

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V. Description of the invention (4) * Remove the shielding layer; and form an insulating layer to fill the isolation zone in the well. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to present, preferred embodiments are described below, and in accordance with the accompanying drawings, detailed descriptions are as follows. Process cross-sectional view of known manufacturing method. Figures 2A-2E are cross-sectional views showing the manufacturing process of a semiconductor device with self-aligned interwell isolation in Embodiment 1 of the present invention.丨 3A-3D are cross-sectional views showing a process of a semiconductor device with self-alignment and isolation according to Embodiment 2 of the present invention. Symbols indicate 10, 60 ~ substrate; 14, 64 ~ semiconductor layer; 18, 68 ~ silicon nitride layer; 22, 72, 82 ~ in-well isolation 24, 76 '86 '88 ~ oxidation 1 2, 6 2 ~ buried Insulating layer; 16, 66 ~ hafnium oxide layer; 20, 70, 80 ~ well separation area; 7 4, 8 4 ~ photoresist layer; layer. Embodiment 1 The present invention provides a manufacturing method with self-aligned interwell isolation: a method. It utilizes self-alignment to simultaneously complete the separation and part isolation in the well. First of all, please "refer to Figure 2A" on a semiconductor substrate 60-buried

V. Description of the invention (5) The Tibetan insulating layer 62 and a semiconductor layer 64 are taken as an example. A wafer of Ben Shenshi Xi (S Ϊ Ϊ) is used as an example. It is obtained by using an insulator with MOX or SmartCut0 technology. . The material material can be implanted with oxygen. The semiconductor layer (layer) is generally thick but not limited to this. The buried insulating layer is generally Λ 疋 -Fi 1 grown on the abundance conductor layer 64 to form a pad oxide layer 66 'if used-a hard cover curtain layer 68, such as the oxide layer 66 on the f oxide layer 8, but This is not the case: The deposition process deposits a silicon nitride. The lithography and etching process is performed to define the nitrogen layer ^ layer 68, pad oxide layer 66, and a portion of the semiconductor layer 64 to form an interwell (^ ter-well) isolation zone 70 and intra_we (isolation) micro.

Git includes the conventional exposure and development technology. The exposure technology includes the optical 2 J exposure technology. The etching process may use an isotropic wet etching process, a non-specific dry etching process, or a reactive ion etching (RIE) process, but it is not limited thereto. ~ Its person, as shown in FIG. 2C, the lithographic process is performed on the semiconductor substrate 60 = meaning a masking layer 74, such as a photoresist layer 74, so that the interwell isolation region 70 is exposed. : ’Self-alignment using the last name engraving process to remove semi-conductors on the well isolation zone 70 卞 2 64. The lithography program includes the conventional exposure and development technology, the exposure technology ": 11 optical stepper exposure technology. The etching process may use an isotropic wet etching process, an isotropic dry etching process, or a reactive ion etching process, but it is not limited thereto. Then, as shown in FIG. 2D, after removing the photoresist layer 74, a

513755

Next, remove the oxide layer. The portion on the substrate 60, such as the marginal layers 76, 7 2 and 76 covering the inter-well isolation area 70 and the in-well isolation area 72, is located in the middle, leaving a space, for example, when chemical mechanical research is performed. Final wet etch fragmentation 6 8. On the upper semiconductor structure and a pair of intrinsic semiconductor layers, as shown in FIG. 2E, the nitrided layer 68 is removed, and the nitride can be removed by using hydrofluoric acid or hot phosphoric acid as an etchant for one pass. After the described embodiment, a conventional integrated circuit procedure can still be performed to form a transistor element on the bottom. The transistor element includes a gate junction source / drain diffusion region. The first embodiment of the invention uses self-alignment to remove the interwell isolation area, and then deposits the insulating interwell insulation layer on the interwell isolation area and the interwell isolation area at the same time to achieve the buried insulation layer and the in-well insulation layer does not have the insulation layer. Full isolation between wells and partial separation within the wells Example 2 First, according to Figure 2A, the process steps and procedures of the same embodiment 1 are performed, and the same reference numerals are components with the same function. << Then, as shown in FIG. 3A, a lithography and etching process is performed to define a nitrided oxide layer 68 and a pad oxide layer 66 to form an interwell isolation region 80 and an intrawell isolation region 82. The lithography process includes the conventional exposure and development technology, and the exposure technology includes the optical stepper exposure technology. Isotropic wet etching

I is an anisotropic dry etching process or a reactive ion etching process, but it is not limited. Secondly, the upper righteousness is covered by a traditional exposure technique using self-alignment Qiaoyouzuo and Indium. As shown in FIG. 3B, a lithography process is used on the semiconductor substrate 60 to shield the layer 84, such as a photoresist layer 84, to isolate the exposed wells from each other. A heavy ion performs a pre-amorphous doping process on the semiconductor layer 64 of the inter-well isolation region 80. Among them, the heavy ions used, antimony, argon, arsenic or oxygen are selected. The lithography process includes general development technology, and the exposure technology includes an optical stepper exposure technology. As shown in FIG. 3C, a region on the semiconductor substrate 60 is implemented. The process makes the semiconductor layer 64 of the interwell isolation region 80. It is oxidized to oxidation = 86 and forms a continuous insulating layer with the buried insulating layer 62. At the same time, the semiconductor layer 64 of the well isolation region 82 is also oxidized to a silicon oxide layer 88. Finally, as shown in FIG. 3D, the silicon nitride layer 68 is removed, and an isotropic wet etching process may be performed using hydrofluoric acid or hot phosphoric acid as an etchant to remove the silicon silicon layer 68. After the above embodiments, a conventional integrated circuit program can be implemented to form a transistor element on a "conductor substrate. The transistor element includes a gate structure and a pair of source / drain diffusion regions. Embodiment 2 of the present invention Use of a heavy ion to implement the interwell isolation region_ A preliminary, amorphous doping process to promote the growth of interwell oxidation layer, when performing the regional oxidation step, you can adjust the process related parameters, such as temperature, time, atmosphere, etc. So that the inter-well oxide layer can reach the buried insulation layer and the intra-well oxide layer will not reach the buried insulation layer, and complete isolation between wells and in-well

513755 5. Description of the invention (8) Partial isolation. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

^ lS / 55 VI. Patent Application Scope • A method for manufacturing a semiconductor device with self-aligned interwell isolation, including the following steps: ^ forming a buried insulating layer and a semiconductor layer on a semiconductor substrate; growing on the semiconductor layer a A pad oxide layer; forming a hard cover curtain layer on the pad oxide layer; 17H hard cover curtain layer, the pad oxide layer and a part of the semiconductor layer to form a well isolation region and a well isolation region; Forming a shielding layer on the hard cover curtain layer and exposing the interwell isolation region; self-alignment to remove the semiconductor layer in the interwell isolation region; removing the shielding layer; and forming an insulating layer to fill the interwell isolation region And the isolation zone within the well. 2. The method according to item 1 of the scope of patent application, further comprising removing the hard cover curtain layer. 3. The method according to item 1 of the patent application scope, further comprising forming a transistor element on the semiconductor substrate, the transistor element including a gate structure and a pair of source / drain diffusion regions. 4. The method as described in item 1 of the scope of patent application, wherein the step of forming an inter-well isolation zone and an intra-well isolation zone on the hard mask layer, the pad oxide layer, and part of the date conductor layer is performed by micro Shadow and etching process. 5. The method according to item 1 of the scope of patent application, wherein the hard cover is a nitrided layer; 6. The method according to item 丨 in the scope of patent application, wherein the insulating layer is a silicon oxide layer. 7 · —Manufacturing of a semiconductor device with self-aligned interwell isolation 0503-6150TWF; TSMC2000-0940,0941; ycchen.ptd No. 13: Gong-VI. Patent application method, including the following steps: forming a buried insulating layer and a -semiconductor layer on a plutonium substrate; and the + conductor layer Grow a pad oxide layer; form a hard mask layer on the pad oxide layer; inside the well: Ϊ: the mask layer and the hafnium oxide layer are formed-a well isolation region and-formed on the hard mask layer A masking layer and exposing the interwell isolation region; performing a self-aligned pre-amorphous doping process on the semiconductor layer of the interwell isolation region using heavy ions; and performing an area oxidation process on the semiconductor substrate, The semiconductor layer at the edge of the four isolation regions is oxidized to form a continuous insulating layer with the buried insulating layer. 8. The method according to item 7 of the declared patent scope, further comprising removing the hard cover curtain layer. 9. The method according to item 7 of the patent application scope, further comprising forming a transistor element on the semiconductor substrate, the transistor element including a gate structure and a pair of source / electrode diffusion regions. 10. The method according to item 7 of the scope of patent application, wherein the steps of forming an inter-well isolation zone and an intra-well isolation zone on the hard mask layer and the pad oxide layer are performed by lithography and etching processes. ^ Among them, the weight 11. The method described in item 7 of the scope of the patent application. The ions are selected from germanium, indium, antimony, osmium i, Shishen or oxygen. Among them, the hard 12. The method described in item 7 of the scope of the patent application. The mask layer is a silicon nitride layer. 0503-6150TWF; TSMC2000-0940, 0941; ycchen.ptd Page 14