JPS60241261A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the reduction of chip size by reducing the occupation area of a collector pull-up opening by a method wherein a semiconductor region is formed on the side surface of an isolated region formed on the side of the element active region, and is then used as the collector pull-up opening. CONSTITUTION:After a buried layer 2, an epitaxial layer 4, an oxide film 5a, and a nitride film 9 are formed on a substrate 1, U-grooves 31 reaching the substrate 1 through the buried layer 2 are formed, and the element active region 12 is formed therebetween. Next, a channel stopper layer 33 is formed at the bottom of the groove; then, an oxide film 34 is formed inside the groove, and a diffused layer 36 reaching the buried layer 2 is formed on the side wall of the groove. The groove 31 is filled with poly Si 37, and an oxide film 38 is formed on the surface; thereafter, a collector lead-out electrode 17 is formed on the diffused layer 36. Afterwards, the base and emitter regions of a bipolar transistor are formed in the element active region 12.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and to the process of semiconductor integrated circuits. related to technology.

[Background Art] The general formation method and structure of elements such as bipolar transistors in conventional bipolar integrated circuits are described in 9, for example, Nikkei Electronics September 28, 1981 issue (N
o, 274) p. 122, etc. FIG. 1 shows an example of the structure of such a known bipolar transistor.

This type of integrated circuit can be manufactured as follows.

That is, first, a semiconductor substrate 1 made of P-type crystalline silicon is prepared, an oxide film is formed on the semiconductor substrate 1, and then holes are formed at appropriate positions in the oxide film to serve as a buried diffusion pattern. Next, using this oxide film as a mask, an N-type impurity such as arsenic or antimony is thermally diffused to partially form an N++-containing layer 2 on the surface of the semiconductor substrate 1.

After removing the oxide film, a P-type diffusion layer 3 for a channel stopper is formed, and an N-type epitaxial layer 4 is formed thereon by vapor phase growth.
Next, an oxide film (Si
02) and form a nitride film (Si3N4) 6 Then,
The oxide film and nitride film are selectively removed by photoetching, and using this as a mask, a relatively thick oxide film 5 for isolation is formed in that portion.

After that, the nitride film is removed.

Then, masking with a nitride film or the like again, an N+ type scattering layer 6 is formed by selective thermal diffusion treatment of an N type impurity such as phosphorus on the part that will become the pull-up port of the collector region, and an N- type epitaxial layer 4 is formed on the N- type epitaxial layer 4. Similarly, by forming a P type base region 7 by selective thermal diffusion treatment and then forming an N medium emitter region 8 within this P type base region 7 by selective thermal diffusion treatment, an NPN as shown in FIG. type bipolar transistor was formed.

By the way, in bipolar integrated circuits using vertical bipolar transistors such as those mentioned above, in order to improve the degree of integration, techniques for reducing element dimensions, such as the SST (super self-alignment transistor) structure, have been developed. There is. However, these new technologies have been developed with a focus on reducing the size of the emitter region and the surrounding base region. In other words, according to the structure and process of a bipolar transistor as shown in FIG. 1, when an attempt is made to reduce the size of the N+ type scattering layer 6 that serves as the collector pull-up port, the bird's peak of the isolation oxide film 5 extends from both sides. A thick oxide film is formed on the surface of the region that becomes the collector pull-up port. Therefore, with the conventional technology, there is a limit to reducing the size of the collector pull-up port (6), and as shown in FIG.
The ratio of the area occupied by the transistor to the area occupied by the entire transistor is extremely large, reaching approximately 50% when the oxide film isolation region between the base and collector is added.

However, when considering the size of the collector pull-up port from the viewpoint of current density, etc., it was found that it is sufficient for the collector pull-up port (6) to have an area approximately the same as the area occupied by the emitter region 8.

Therefore, in the conventional transistor structure as shown in FIG. N0 buried layer 2
As a result, the parasitic capacitance between the collector and the substrate increases, which causes a reduction in the operating speed of the transistor.

The inventor of the present invention has revealed that there are the above-mentioned problems.

[Object of the Invention] An object of the present invention is to reduce the area occupied by a semiconductor region as an electrode extraction region in a semiconductor device such as a vertical bipolar transistor, thereby reducing the device size and increasing the degree of integration of an integrated circuit. The object of the present invention is to improve the operating speed of the constructed circuit by reducing the parasitic capacitance between the element active region and the substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, in the process of bipolar integrated circuits, before forming an oxide film for element isolation, the surface area where the isolation oxide film is to be formed is scraped off, and then electrodes are placed around the periphery of the element active region using an insulating film as a mask. By doping impurities to form a semiconductor region for leading out electrodes, and then performing thermal oxidation to form an oxide film for isolation and forming such a semiconductor region, the area occupied by the semiconductor region for leading out electrodes can be reduced. This aims to achieve the above objectives of reducing the parasitic capacitance between the element region and the substrate by reducing the area of the N+ buried layer, increasing the degree of integration of bipolar integrated circuits, and increasing the speed of the circuit. .

The present invention will be described in detail below along with examples.

[Example 1] Figures 3 to 12 show an example in which the present invention is applied to a bipolar integrated circuit in which elements are isolated by a field oxide film formed by isoplanar technology. are shown in order of manufacturing process.

In this embodiment, an integrated circuit is formed by the following method.

First, a semiconductor substrate 1 is prepared which is made of a thin plate of P-type crystalline silicon and whose main surface is aligned with the (100) crystal plane. Next, although not particularly limited, an oxide film is formed on the semiconductor substrate 1 by the same method as the known isoplanar technology, and then holes with holes (turns) for buried diffusion are drilled at appropriate positions in the oxide film. Using this oxide film as a mask, an N-type impurity such as arsenic or antimony is thermally diffused into the semiconductor substrate 1 to partially form an N''' buried layer 2, and after hardening, the oxide film is removed (step 1). Figure 3).

Next, as shown in Figure 4, the channel stock horn (P
After forming the medium-sized diffusion layer 3, an N-type silicon epitaxial layer 11 layer 4 is grown thereon by rectangular vapor phase epitaxy, and an oxide film (Si
02) 5a and a nitride film (Si3N4) 9 are formed. .

Next, a silicon oxide film (Si02) 10 is deposited on the nitride film 9 on the main surface of the substrate 1 to serve as an etching mask for forming contact holes later. Thereafter, a photoresist for use as an etching mask is applied onto this oxide film 1o, and this is selectively exposed and developed.

As a result, as shown in FIG. 5, a photoresist 11 is left on the oxide film 10 with a pattern corresponding to an element active region in which an element such as a transistor is to be formed.

Next, the oxide film 10 is selectively removed by wet etching using the photoresist 11 as a mask. In this case, as shown in FIG.
The etching conditions are appropriately set so that undercutting of the oxide film 10 occurs under the oxide film 10. Thereafter, the nitride film 9 and oxide film 5a on the main surface of the substrate are selectively removed by directional dry etching using the photoresist 11 as a mask.

Next, after removing the photoresist 11, using the nitride film 9 and oxide film 5a as masks, an anisotropic etching solution that selectively etches silico, such as a hydrazine etching solution, is used as will be described later. The main surface of the silicon substrate in the area where the isolation oxide film is to be formed is shaved. As a result, a trapezoidal element active region 12 is formed on the N++-containing layer 2, as shown in FIG. Said sixth
The oxide film 10 that has been processed as shown in the figure is not removed in this etching, and therefore remains on the nitride film 9 that serves as a mask on the surface of the element active region 12.

In this embodiment, it is desired that the etching of the silicon substrate does not proceed substantially below the nitride film 9 and oxide film 5a serving as a mask during the etching. That is, it is desired that substantially no undercut occurs. The hydrazine etching solution described above allows etching with virtually no undercut. Note that anisotropic etching such as hydrazine etching, for example,
VLSI Process Data Handbook”, 1984, 4
It is introduced on pages 438 to 440, published by Science Forum, dated May 15th.

From the above state, by applying photoresist again on the substrate, exposing it to light, and developing it, as shown in FIG. Make sure that the photoresist 13 remains. Thereafter, using the photoresist 13 as an ion implantation mask, an N-type impurity such as arsenic is implanted into the device active region 12.
is introduced onto the surface by ion implantation. As a result, the photoresist 13 and the periphery and inclined side surfaces of the surface of the element active region 12 that are not covered with the oxide film 10 are
An ion implantation layer 14 is formed (FIG. 8).

Note that in order to prevent contamination of the silicon surface during ion implantation, a thin oxide film is formed in advance on the side surface of the element active region 12 before ion implantation, as before the formation of the photoresist 13, and a thin oxide film is formed through this oxide film. The ion implantation layer 14 may be formed by performing ion implantation. Also,
In addition to ion implantation, N-type impurities may be introduced by deposition diffusion. FIGS. 14 and 15 show cross sections when N-type impurities are introduced by deposition diffusion.

FIG. 14 shows a state in which, after the step shown in FIG. 7, a thermal oxide film 5b is formed on the exposed semiconductor surface, and a photoresist film 13 as an etching mask is selectively formed on the surface. There is.

FIG. 15 shows that the thermal oxide film 5b is selectively removed using the photoresist film 13 as a mask, then the photoresist film 13 is removed, and then the remaining thermal oxide film 5b and the previously formed nitride film are removed. 9 shows a state in which an N++ layer 14 with a high impurity concentration is formed on the surface of the element active region by a deposition diffusion method using the oxide film 5a as an impurity introduction mask.

After the state shown in FIG. 8, after removing the photoresist 13, the silicon substrate is oxidized by thermal oxidation in, for example, a high-pressure oxidizing atmosphere using the nitride film 9 as a selective oxidation mask, as shown in FIG. A thick field oxide film 5 is grown on the main surface. In this selective oxidation, oxidation proceeds not only in the thickness direction of the substrate but also in the lateral direction. During the growth of this oxide film 5, the N-type impurity is pushed to the boundary (side surface) of the oxide film 5 due to its segregation action. Therefore, the N-type impurity in the ion implantation layer 14 is moved and concentrated,
As shown in FIG. 9, a very thin N+ type scattering layer 16 is formed under the oxide film 5 from the bird's peak to the bird's head, that is, at the boundary between the oxide film 5 and the trapezoidal element active region 12. In other words, in this embodiment, when silicon containing N-type impurities is oxidized, N-type impurities are formed in the oxide film due to the difference in segregation coefficient between the oxide film and silicon. Because the impurities are pushed out to the silicon side without being taken in, N-type impurities are successively pushed and concentrated by the interface of the oxide film (in this invention, this is referred to as segregation effect). A thin N-type diffusion layer 16 is formed at the periphery of the element active region 12, and this is used as a collector pull-up port (electrode extraction region).

After the state shown in FIG. 9, using the oxide film 10 previously formed on the element active region 12 as a mask, the underlying nitride film 9 and oxide film 5a are removed, and the area around the element active region 12 is removed. The surface of the ring-shaped N-type diffusion layer 16 is exposed in submicron units. Next, after removing the oxide film 10, a polysilicon layer or a metal silicide (compound of silicon and metal) layer doped with a high concentration of N-type impurities is formed on the entire surface, and then this is patterned by photoetching. By doing so, an electrode lead layer 17 is formed as shown in FIG.

After that, a base region and an emitter region are formed on the surface of the device active region 12 inside the ring-shaped collector lead-out electrode 17 by a process similar to the process of the bipolar transistor that has already been proposed, and the device size is extremely small. A bipolar transistor can be configured.

An example of the process for forming the base region and emitter region in this embodiment will be briefly explained as follows.

That is, although not particularly limited, after the state shown in FIG.
For example, the oxide film 18 is formed by oxidizing the surface of the electrode lead layer 17. Thereafter, using the electrode lead layer 17 and the field oxide film 5 on which the oxide film 18 is formed as an ion implantation mask, P-type impurities are introduced and diffused into the surface of the element active region by ion implantation. This forms a P-type base region 7. Then, nitride film 9 and oxide film 5a on the surface of base region 7 are selectively removed to form a contact ball. Thereafter, P-type polysilicon is deposited and selectively removed by photoetching to form the base lead electrode 19. Next, an insulating film 20 such as an oxide film is formed thereon, and the nitride film 9 and oxide film 5a formed on the surface of the part where the emitter is to be formed are selectively removed, and then the N A polysilicon layer doped with type impurities is deposited to serve as an emitter electrode 21. By heat treatment after forming the electrode 21, impurities in the emitter electrode 21 are thermally diffused to the surface of the base region 7. As a result, an N-type emitter region 8 is formed within the base region 7 (FIG. 11).

Thereafter, as shown in FIG. 12, a glabellar insulating film 22 such as a PSG film is formed on the entire surface by CVD or the like, and then the electrode lead layer 17 and the base lead electrode 19 are coated on this interlayer insulating film 22. and a contact hole for the emitter electrode 21 is formed. Next, aluminum is deposited over the entire surface and then patterned by photoetching to form aluminum electrodes 23a to 23c. Thereafter, a final passivation film 24 is formed thereon to complete the process.

According to the above embodiment, a very thin high impurity concentration layer is formed around the trapezoidal device active region 12 in which the base region 7 and emitter region 8 are formed, and reaches the N+ buried layer 2. The N-type diffusion layer 16 serves as an electrode lead-out region, that is, a collector pull-up port in the case of a transistor. Therefore, compared to the bipolar transistor with the structure shown in Figure 1, the device dimensions are significantly reduced due to the narrower collector outlet and the elimination of the isolation region (oxide film) between the base and collector. As a result, the degree of integration of the bipolar integrated circuit is improved, the chip size is reduced, and costs can be reduced.

Furthermore, according to the above embodiment, the area of the collector (N+ buried layer 2) can be reduced by the amount that the element dimensions are reduced, so the parasitic capacitance between the collector and the substrate is reduced, and the operation of the transistor is reduced. Speed will also be improved.

In the above embodiment, the N-type diffusion layer 16, which serves as a collector pull-up port, is formed in a ring shape around the element active region 12, but in FIG. 8, only one side of the element active region 12 is exposed. By setting the pattern of the photoresist 13 so that the photoresist 13 is exposed, and implanting N-type impurities while covering other parts with the photoresist, an N-type diffusion layer 16 is formed on only one side of the base region 7 to serve as a collector pull-up port. It is also possible to form By configuring like this,
Furthermore, the area occupied by the collector pull-up port can be reduced and the degree of integration can be improved.

Further, as in the embodiment, the nitride film 9 on the surface of the element active region 12 is etched in advance by side etching to make it more than this.
The method of forming the oxide film 1o with a small circumference is advantageous in that the electrode extraction region 16 is exposed accurately and reliably before forming the electrode 17, but this oxide film 10 is not necessarily provided and may be omitted. It is possible.

Furthermore, in the above embodiment, the base region 7 is formed by ion implantation after forming the collector pull-up port (16) and the collector lead-out electrode 17, but the SST structure as shown in FIG. 13 is formed by the following method. A transistor may be configured. That is, as shown in FIG. 10, an electrode lead layer 17 is formed, and an oxide film 18 is formed on its surface.

Contact holes are formed in the nitride film 9 and oxide film 5a on the surface of the element active region 12. After that, P is placed on the main surface of the substrate.
Deposit a mold polysilicon electrode (19). Next, a P-type external base region 7a is formed by impurity diffusion from this polysilicon electrode (step 9). Thereafter, P-type impurities are introduced into the surface of the element active region 12 by ion implantation, thereby forming the intrinsic base region 7b.

After forming a thermal oxide film 20 on the surface of polysilicon electrode 19, nitride film 9 and oxide film 5a are etched away using thermal oxide film 20 as a mask.

Next, an N-type polysilicon electrode 20 is formed, and this electrode 2
An emitter region 8 is formed by diffusion of N-type impurities from 0 to 10.

Alternatively, after forming the polysilicon electrode 19, forming the external base region 7a and the thermal oxide film 20, the nitride film 9 and the oxide film 5a can be formed using the thermal oxide film as a mask in the same manner as above.
Select and remove. Next, an emitter electrode 21 made of a polysilicon layer is formed.

After forming the emitter electrode 21 and before forming the emitter region 8, a P-type impurity is ion-implanted into the surface of the element active region 12 via the emitter electrode 21, and is diffused to form the intrinsic base region 7b. . Thereafter, N-type impurity ions are implanted into the emitter electrode 20 and diffused to form the emitter region 8.

In this way, after forming the collector pull-up port (16) and the collector lead-out electrode 17, a graft-based transistor can be formed on the element active region 12 by various methods that have already been proposed.

[Embodiment 2] FIGS. 16 to 20 show an example in the order of manufacturing steps in which the present invention is applied to a bipolar integrated circuit in which elements are separated by a U-groove isolation method. ing.

First, as shown in FIG. 16, an N+ buried layer 2 is formed on a semiconductor substrate 1, an N- type epitaxial layer 4 is formed thereon, and an oxide film 5a and a nitride film 9 are formed on the surface thereof.

Thereafter, the oxide film 5a and nitride film 9 in the portion where the isolation region is to be formed are removed, and using this as a mask, a groove 31a is formed by hydrazine etching or the like as shown in FIG. The N1 layer 32 is formed by ion implantation or diffusion of type impurities. Thereafter, by directional dry etching, a deep U groove 31 that penetrates the N+ buried layer 2 and reaches the P type substrate 1 is formed.
Device active regions 12 made of N-type epitaxial layers 4 separated by grooves 31 are formed, resulting in the state shown in FIG. 18.

In autumn, a P-type impurity such as boron is ion-implanted into the bottom of the U-groove 31 to form a P-type channel stopper layer 33 as shown in FIG. 19, and then the exposed surface is thermally oxidized. As a result, as shown in FIG. 17, an oxide film 34 is formed inside the U-groove 31, and as the oxide film 34 grows, the N-type impurity doped on the side walls of the U-groove is removed. It is not pushed and concentrated by the oxide film and reaches the N+ buried layer 2, forming an N type diffusion layer 36.

In this embodiment, this N-type diffusion layer 36 is used as a collector pull-up port.

After the state shown in FIG. 19, the U-groove 31 is filled with polysilicon by depositing relatively thick polysilicon over the entire substrate by the CVD method6, and the surface of the polysilicon layer is flattened. To achieve this, this polysilicon layer is dry etched. This etching is performed so that polysilicon 37 remains within U-groove 31. Next, polysilicon 3 in the U groove is thermally oxidized.
An oxide film 38 is formed on the surface of 7. A contact hole 39 is formed in the upper part of the N-type diffusion layer 36 by photoetching.
An N-type diffusion layer 36 is formed by depositing polysilicon thereon and patterning it.
A collector lead electrode 17 is formed in contact with the (second
Figure 0).

Thereafter, although not shown, a base region and an emitter region of a bipolar transistor are formed in the element active region 12 separated by the U-groove isolation region 30. The method of forming it is the same as that of the first embodiment, so the explanation will be omitted.

According to this embodiment, in a bipolar integrated circuit in which elements are separated by the U-groove isolation method, the narrow collector pull-up port (
36), it is possible to reduce element dimensions and chip size. Furthermore, it becomes possible to reduce the element size, reduce the parasitic capacitance between the collector and the substrate, and improve the operating speed of the transistor.

Note that in this second embodiment as well, similarly to the oxide film 10 of the first embodiment, a film for forming contact holes in a self-aligned manner can also be used. That is,
In this case, an oxide film 10 and a photoresist pattern 11 similar to those shown in FIG. 5 are formed on the nitride film 9 on the element active region j2 shown in FIG. 16 by the CVD method. Next, the oxide film 1
After creating an undercut in 0, the nitride film 9 and oxide film 5a are selectively removed by anisotropic dry etching. Next, as shown in FIGS. 17 and 18, the groove 31a and the U groove 3
form 1.

Next, as in FIG. 19, an oxide film 34 is formed in the trench 31,
Polysilicon 37 is filled into the U groove and an oxide film 3 is formed on its surface.
8, a contact hole 39 for the collector pull-up port (36) is formed in a self-aligned manner using the undercut oxide film 10 as a mask.

Furthermore, in the above embodiment, the formation of the N' layer 32 before the formation of the oxide film 34 on the inside of the U-groove may be performed by various methods other than the method of the embodiment6.
A phosphorus glass is deposited inside the ig, and it is annealed, and an N intermediate layer 32 is formed by diffusion of phosphorus from the phosphorus glass during the annealing, and then the phosphorus glass is removed and an oxide film 34 is grown. Alternatively, the N-type diffusion layer 36 may be formed using the same method.

Note that if the isolation oxide film is not provided between the base and collector as in the above embodiment, there is a risk that the withstand voltage of the +- transistor will drop a little, but
Since the internal elements do not require such a high breakdown voltage, it is sufficient that there is no isolation oxide film between the base and the collector as in the embodiment. Moreover, the process of the above embodiment can be combined with the conventional bipolar process, so for input/output circuit elements that require high breakdown voltage, an isolation oxide film is provided between the base and collector, and internal elements are Regarding this, the structure of the embodiment may be applied.

[Example 3] FIG. 21 and FIG. 22 show a cross section of a semiconductor substrate of another example.

Although this embodiment is not particularly limited, it is considered to be suitable for configuring any circuit by the master slice method. The surface of a semiconductor substrate can be roughly divided into two parts. One is a circuit element formation area where a plurality of circuit elements are formed to enable the formation of a unit circuit, and the remaining one is a wiring for interconnecting the plurality of unit circuits to be formed. This is a wiring formation area where layers are formed. In the case of a large-scale integrated circuit, a plurality of circuit element forming regions are set on the surface of a semiconductor substrate in a matrix arrangement. The surface of the semiconductor substrate between the circuit element formation regions is used as a wiring formation region.

According to this embodiment, in the circuit element forming region, the element active regions to be separated from each other are
separated by a U-groove similar to

The wiring formation region is set on a field oxide film formed by selective oxidation technology.

FIG. 21 shows a state in which a relatively thick field oxide film 5 is formed. The manufacturing process until the field oxide film 5 is formed is, for example, as follows.

First, a semiconductor substrate 1 made of P-type silicon is prepared, and an N+-type buried layer 2 and a P-type channel stopper layer 3 are formed on its surface. Next, an N- type silicon epitaxial layer 4 is formed on the surface of the semiconductor substrate 1, and a silicon oxide film 5a and a silicon nitride film 9 are formed on the surface of the epitaxial layer 4. Nitride film 9 and oxide film 5a are selectively etched away so as to expose a portion of epitaxial layer 4 that is to be a wiring formation region. Remaining nitride film 9 and oxide film 5
The surface of the epitaxial layer 4 is etched using a as an etching mask. Thereafter, the epitaxial layer 4 is selectively oxidized using the nitride film 9 and oxide film 5a as an oxidation-resistant mask.

This results in a cross-sectional structure as shown in FIG. 21.

FIG. 22 shows that after the structure shown in FIG. 21, a U-groove 31, an N-type diffusion layer 36, and an oxide film 3 are formed through the same manufacturing process as in Example 2.
4 shows a cross section of the semiconductor substrate in a state where 4 is formed.

The manufacturing steps after FIG. 22 are the same as in the second embodiment.

In this embodiment, various circuit elements in a unit circuit formation region are connected to each other via a wiring layer made of a vapor-deposited aluminum layer. The unit circuits are connected to each other via a wiring layer made of a vapor-deposited aluminum layer extending over the field oxide film 5.

According to this embodiment, the unit circuit forming area can be made sufficiently small for the same reason as in the second embodiment. The wiring layer for interconnecting unit circuits is
Since it extends over a large thickness of field oxide 5, it has a relatively small stray capacitance.

[Effect (1) In the process of bipolar transistors, before forming an oxide film for element isolation, the main surface of the substrate in the area where the oxide film is to be formed is scraped, and then the active region of the element is removed using an insulating film as a mask. After doping the periphery of the active region with an impurity that forms the collector pull-up port, thermal oxidation is performed to form an isolation oxide film. By forming a diffusion layer that serves as a collector pull-up port with a narrow width, the area occupied by the collector pull-up port is reduced, and the degree of integration of the bipolar integrated circuit is improved.

(2) In the process of bipolar transistors, before forming an oxide film for element isolation, the main surface of the substrate in the area where the oxide film is to be formed is scraped, and then the periphery of the element active region is etched using an insulating film as a mask. After doping with impurities to form the collector pull-up port, we performed thermal oxidation to form an isolation oxide film, so the segregation effect accompanying the formation of this oxide film creates a relatively wide area around the active region. A diffusion layer that serves as a narrow collector pull-up opening is formed, which reduces the area of the N0 buried layer that serves as the collector region, reducing the parasitic capacitance between the collector and the substrate, increasing the operating speed of the transistor. It has the effect of being

(3) In the process of bipolar transistors, before forming an oxide film for element isolation, the main surface of the substrate in the area where the oxide film is to be formed is scraped, and then the periphery of the element active region is etched using an insulating film as a mask. In the process of doping impurities that form the collector pull-up port and then performing thermal oxidation to form an isolation oxide film, side etching is used on the insulating film that serves as a mask when forming the isolation region. An insulating film (oxide film) smaller in circumference than this is formed in advance, and after the collector pull-up port is formed, this insulating film (
Since the contact hole for the collector pull-up port is formed in a self-aligned manner using the oxide film (oxide film) as a mask, the collector lead-out electrode can be reliably brought into contact with the narrow collector pull-up port. .

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the structure of the U-groove isolation region in the embodiment described above is not limited to that of the embodiment, but may be one in which a nitride film is formed inside the oxide film 34.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar integrated circuits, which is the field of application that formed the background of the invention, but the application is not limited thereto. , it can also be used when forming a bipolar transistor together with a MOS transistor on the same substrate.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of the structure of a conventional bipolar transistor, FIG. 2 is an explanatory plan view thereof, and FIGS. FIG. 13 is a cross-sectional view showing an example of its application, and FIGS. 16 to 20 are cross-sectional views showing the first embodiment in the order of manufacturing steps when applied to a circuit. 21 and 22 are cross-sectional views showing the third embodiment of the present invention in the order of the manufacturing steps. 1... Semiconductor substrate, 2... N+ buried layer, 3...
... Channel stopper layer, 4... Epitaxial layer, 5a... Oxide film, 5... Isolation oxide film, 6
゜16.36...N-type diffusion layer (collector pull-up port)
7...Base region, 8...Emitter region, 9...
...Nitride film, 10..Oxide film, 11..Photoresist pattern, 12..Element active region, 13..
... Photoresist pattern, 14 ... Ion implantation layer, 17 ... Collector extraction electrode, 18 ...
Contact hole, 19...Base extraction electrode, 2
0... Insulating film (oxide film), 21... Emitter electrode, 22... Interlayer insulating film, 23a to 23c...
Aluminum electrode, 3o...U groove separation area, 31...
U groove, 32...N middle layer, 33...channel stopper layer, 34...oxide film, 37...polysilicon, 38...oxide film, 39...contact hole . Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 2 / Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 / Figure 161 ¥1 Figure 17 Figure 18 Figure 19 Figure 20,, 7'?

Claims (1)

[Claims] 1. An element active region made of a semiconductor layer is provided on a semiconductor substrate via a buried layer of a conductivity type different from that of the semiconductor substrate, and a side surface of the element active region is provided with a layer in contact with the element active region. an isolation region is provided on at least a portion of a side surface of the element active region, extending from the main surface of the element active region to the buried layer;
A semiconductor device comprising: a semiconductor region having the same conductivity type as the element active region and having a higher impurity concentration than the element active region. 2. The semiconductor device according to claim 1, wherein an electrode layer is formed on the semiconductor region and in contact with the semiconductor region. 3. The semiconductor device according to claim 1 or 2, wherein the isolation region is formed so as to be in contact with a side surface of the buried layer and to reach the semiconductor substrate. 4. The isolation region is an isolation region formed by digging a trench in the main surface of the semiconductor substrate to form an oxide film, and filling the inside with a dielectric material. semiconductor devices. 5. In the device active region, the device active region is used as a collector region, a first semiconductor region formed on the surface of the device active region and having a conductivity type opposite to that of the device active region is used as a base region, and the first semiconductor region is provided as a base region. 2. The semiconductor device according to claim 1, wherein a transistor is formed having, as an emitter region, a second semiconductor region having a conductivity type opposite to that of the first semiconductor region formed in the first semiconductor region. 6. Forming a buried layer of a conductivity type different from that of the semiconductor substrate on a semiconductor substrate, forming an epitaxial layer thereon, and then selectively removing the epitaxial layer, thereby forming a base made of the epitaxial layer. After forming a device active region in the shape of a shape and introducing impurities into at least a part of the periphery of the device active region, thermal oxidation is performed to form a device active region around the device active region, and also to form a device active region in the periphery of the device active region. A method of manufacturing a semiconductor device, comprising: forming a semiconductor region extending from the main surface of the element active region to the buried layer. 7. When selectively removing the epitaxial layer, a second mask that does not cover at least a portion of the first mask is formed on the first mask formed on the surface of the epitaxial layer that is not to be removed; 7. The method of manufacturing a semiconductor device according to claim 6, wherein a contact hole for the semiconductor region is formed by using a second mask.