JPS63308963A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be integrated at a still higher level, by forming source and drain electrodes in a previously isolated element- forming region in a self-aligned manner, forming a gate electrode also in a self-aligned manner and extracting the source and drain electrodes by means of a doped polycrystalline silicon film. CONSTITUTION:Since a source region 1, a drain region 2 and a gate electrode 3 are formed in a transistor region isolated by an insulating film, in a self- aligned manner, they are allowed to have a fineness less than a minimum processable size. The source and drain regions are led out by a polycrystalline silicon film 5 and connected to an interconnecting layer 6 on the insulating film 4. Accordingly, it is possible to prevent problems such as defective contact which would be caused by punch-through of aluminum into the source and drain due to direct contact of the aluminum interconnection with the source and drain. Further, the area of the contact region having a small dimension along the length of the channel can be extended long along the width of the channel, Accordingly, even higher integration of the device can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a MOS (metal-oxide semiconductor) suitable for large-scale implementation.
al○xide Semiconductor)
The present invention relates to a structure of a semiconductor device having a field effect transistor and a method of manufacturing the same.

[Conventional technology]

In recent years, with advances in microfabrication technology, LSIs are becoming more highly integrated and faster. In particular, LSIs using so-called MO3 field effect transistors have been developed as suitable for large-scale integration because their manufacturing process is relatively easy.

3(a)-(d) are cross-sectional views showing the manufacturing process of a typical n-channel MO8 field effect transistor.

First, as shown in FIG. 3(a), an underlying Sio2 film 31, Si3N, and pancreas 32 are sequentially formed on a semiconductor substrate 38.
Using known photolithography and dry etching techniques, S'', N,
II Samurai 32 remains. Next, after boron (B) ions are implanted to form a channel stopper 33, a thick SiO□ film 4 for element isolation is formed by thermal oxidation.

Next, after removing the 5iaN film 32 and the Sio film 31 by etching, a gate oxide film (Sin2 film) 7 is formed by thermal oxidation and channel ion implantation is performed as shown in FIG. (not shown).

Next, a polycrystalline silicon film is deposited, phosphorus (P) ions are added to the polycrystalline silicon film, and then repatterned by photolithography and dry etching techniques.
c) Form the gate electrode 3 as shown in the figure. Then,
Using this gate electrode 3 as a mask, arsenic (As) ions are implanted to form a source region 1 and a drain region 2.

Finally, as shown in (d) figure, PSG for interlayer insulation
After depositing the (phosphorous glass) film 34, one source/drain contact hole is made, aluminum (8n) is deposited by sputtering, and this is patterned to form the n wiring 35, and the M, O8 field effect Complete the transistor.

In such a conventional manufacturing process, the source/drain regions are formed in a self-aligned manner with respect to the gate electrode.
This is advantageous for miniaturization. (As for the literature related to the prior art, there is MOS LSI Manufacturing Technology by Kakusho and Minato, Nikkei McGraw-Hill (1985), Chapter 2, Total Process, page 30.) [Problems to be solved by the invention] However, in the future, It is difficult to say that there is a reliable outlook that this high level of integration will continue.

For example, the channel length of the MO8ffi field effect transistor mentioned above is determined by the minimum processing size of the gate determined by the resolution limit of photolithography, and is 0.5
- No reliable prospects have been obtained for the following photolithography techniques. Furthermore, with the miniaturization of M wiring, there are many process difficulties such as increased contact resistance, decreased reliability, surface flattening, and difficulty in filling contact holes.

In particular, the various problems mentioned above regarding An interconnection are caused by the conventional manufacturing method, which overemphasizes the advantage of the ion implantation method in that the gate electrode is first formed, and then the source and drain can be formed in a self-aligned manner. This indicates that the final electrode wiring step has become a problem in the process.

Furthermore, the MO8 field effect transistor itself has a structure in which the contact region must be wider than necessary for device operation in order to form source and drain contacts.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-mentioned conventional problems and facilitate high integration of -N.

[Means for solving problems]

The above purpose is to form a source/drain electrode in a self-aligned manner in a pre-separated element formation region, and to create a structure in which a gate electrode can be formed in a self-aligned manner to these electrodes. This is achieved by creating a structure drawn from a doped polycrystalline silicon film.

That is, 1 the semiconductor device of the present invention includes a semiconductor substrate, a wiring layer formed on the semiconductor substrate via an insulating film, and a wiring layer provided through the wiring layer and the insulating film so that the semiconductor substrate is exposed. a polycrystalline silicon film left on the side wall of the aperture, a gate insulating film formed on the surface of the semiconductor substrate exposed between the polycrystalline silicon film, and the polycrystalline silicon film formed on the semiconductor substrate surface exposed between the polycrystalline silicon film and A special feature characterized by comprising a gate electrode formed in a gap between crystalline silicon films via an insulating film, and source/drain regions formed on the surface of the semiconductor substrate on both sides of the gate electrode. , the method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate, and a step of forming an insulating film on the insulating film.
a step of forming an opening for a transistor type J-type through the insulating film and the conductive layer so as to expose the semiconductor substrate by etching the insulating film and the conductive layer; and a polycrystalline silicon film containing impurities. a step of leaving the polycrystalline silicon film only on the side wall of the opening by anisotropic etching, a step of processing the conductive layer into a predetermined pattern, and a step of depositing the semiconductor substrate and the polycrystalline silicon film. A step of forming an oxide film and a source/drain region on the surface of the film, and a step of filling an electrode material into the gap between the polycrystalline silicon films through the oxide film to form a gate electrode. Features.

[Effect]

Conventionally, source/drain regions were formed by forming a gate electrode with the minimum processing size determined by the resolution limit of photolithography and introducing impurities using this gate electrode as a mask. Forming transistors has been difficult. In contrast, in the present invention, the source/drain region and the gate electrode are self-aligned within the opening for forming a transistor that is penetrated through the insulating film and wiring layer on the semiconductor substrate and separated by the insulating film. It can be provided as follows. Therefore, by forming the opening portion to have the minimum processing size, the transistor can be formed to the minimum processing size or less.

Further, the source/drain electrodes are led out by a polycrystalline silicon film left on the side wall of the opening and connected to the wiring layer on the insulating film. Therefore, unlike the prior art, there is no fear of poor contact such as penetration of Au into the source/drain due to old wiring that directly contacts the source/drain.

Furthermore, the area of the contact region, which is small in the channel length direction, can be increased by making it longer in the channel width direction.

Further, the wiring layer on the #4Ae film can be etched according to the wiring pattern before forming the transistor (source/drain, gate oxide film, gate electrode wA), and the process can be simplified.

Furthermore, since the gate electrode can be formed last, it is possible to use An, which has a low melting point, as the gate electrode material, and the buried structure is also effective in flattening the device plane.

〔Example〕

Example 〕.

FIG. 1 is a sectional view showing an MO3fft field effect transistor according to a first embodiment of the present invention.

In the figure, 8 is a semiconductor substrate, 4 is an insulating film, 6 is a wiring layer, 5 is a polycrystalline silicon film left on the side wall of an opening for forming a transistor provided in the insulating film 4 and the wiring layer 6, 1 2 is a source region, 2 is a drain region, 7 is a gate oxide film, 70 is an oxide film provided on the surface of the polycrystalline silicon film 5, and 3 is a gate electrode.

In such a structure, the source region 1, drain region 2, and gate electrode 3 are formed in a self-aligned manner in the I-transistor region separated by the insulating film 4.
Miniaturization below the minimum processing size is possible. Further, the source/drain electrodes are drawn out through the polycrystalline silicon film 5 and connected to the wiring WJ6 on the insulating film 4. Therefore, unlike the prior art, there is no fear of poor contact such as penetration of the wire into the source/drain due to the A11 wiring directly contacting the source/drain. In addition, the area of the contact region, which is small in the channel length direction, is
It can be made wider by lengthening the channel in the width direction. Further, the wiring layer 6 on the insulating film 4 can be etched according to the wiring pattern before forming the transistor (source/drain, gate oxide film, gate electrode), thereby simplifying the process. moreover,
Since the gate electrode can be formed last, it is possible to use a material with a low melting point, and since it is a buried structure, it is also effective in flattening the device plane.

Next, FIGS. 2(a) to 2(e) show cross-sectional views of steps for realizing the structure shown in FIG. 1.

First, as shown in Figure (a), an insulating film 4 and a conductive WI 6 made of an electrode material are sequentially formed on a semiconductor substrate 8.

Next, as shown in the figure (b), the insulating film 4 and the conductive layer 6
A penetrating opening 21 is provided in the transistor formation region so that the semiconductor substrate 8 is exposed. Next, a polycrystalline silicon film doped with impurities is deposited over the entire surface, and polycrystalline silicon film 5 is left only on the sidewalls of the openings 21 by anisotropic etching. Thereafter, the conductive layer 6 is processed according to a wiring pattern using photolithography and dry etching techniques to form a wiring layer.

Next, as shown in FIG. 3(d), an oxide film 70 is formed on the surfaces of the gate oxide film 7 and the polycrystalline silicon layer 5 by thermal oxidation. At this time, the impurities contained in the polycrystalline silicon film 5 are diffused to form the source region 1 and the drain region 2.

Finally, as shown in FIG. 3(e), an electrode material such as a metal oxide is buried in the gap between the polycrystalline silicon films 5 with an insulating film 70 interposed therebetween to form a gate I-electrode 3.

Example 2 Next, using FIGS. 4(a) to (e), an n-channel MO8
An example of forming a field effect transistor will be described.

First, as shown in FIG.
After forming a p+ channel stopper by implanting at an implantation energy of 25 keν, thermal oxidation is performed to form a thermal oxide film (Sin2 film) 42 with a thickness of approximately 500 nm, and then TiS x 2 is deposited by the CDV method. A (titanium silicide) film 43 was deposited to a thickness of 500 nm, and a polycrystalline silicon film 44 was deposited to a thickness of 20 nm.

Subsequently, as shown in (b), thermally oxidized IJ'242,
An opening 45 having a width of 47 m and a length of 1.3 m is formed in the 1-transistor formation region of the TiSi□ film 43 and the polycrystalline silicon film 44 by photolithography and dry etching techniques so that the silicon substrate 40 is exposed.

Next, as shown in figure (c), a polycrystalline silicon film is deposited again to a thickness of 200 nm, and then removed by an anisotropic etching method, such as reactive ion etching (RIE), to open holes. A polycrystalline silicon film 46 was left only on the side wall portion of the portion 45. Note that the polycrystalline silicon films 44 and 46 used here are all doped with As at a high concentration.

Next, after patterning the polycrystalline silicon film 44 and the TiSi film 43 according to the wiring pattern,
Dose amount 1×10′3-2, implantation energy 125
B+ ion implantation was performed under the conditions of keν, and further,
Heat treatment was performed at 900° C. for 110 minutes in a steam atmosphere to form a gate oxide film 47 with a thickness of 20n+x, as shown in FIG. Through this treatment, As contained in the polycrystalline silicon film 46 is diffused to the surface of the silicon substrate 40, and the shallow junction source region 4 with a depth of 0.14 mm or less is diffused into the surface of the silicon substrate 40.
8. At the same time as the drain region 49 is formed, the surface of the polycrystalline silicon film 44, 46 is oxidized to a thickness of about 50 nn.
Sin, [70 was formed.

Finally, after depositing An on the entire surface by CVD (chemical vapor deposition), it is planarized using photoresist 1- and etched back to form an embedded and planarized Au layer, as shown in the figure (e). A gate electrode 50 was formed. Note that at this time, it is also possible to process M by ordinary photolithography and dry etching techniques to form a gate electrode wiring.

Through the above process, with a minimum processing size of 1.5-
It was possible to form an MO8 field effect transistor with a channel length of 1 mm or less. In addition, this embodiment also has the same effects as described in the first embodiment.

Embodiment 3 FIG. 5 is a sectional view of a transistor according to a third embodiment of the present invention. This example demonstrates the present invention in an LDD (Lightly Doped I-Drain).
An example in which a MOS field effect transistor having a drain) structure is formed will be described. In the figure, the same reference numerals as in FIG. 4 indicate the same parts. In the figure,
51 is a polycrystalline silicon film doped with phosphorus (P) for forming a low concentration drain, and 52 is a low concentration drain.

The basic process flow is the same as the actual process shown in FIG. 4, but after the step in FIG. 4(c), P-doped polycrystalline silicon 51 is deposited and anisotropically etched again. By adding additional steps, a DD structure can be formed. Note that the low concentration drain 52 is formed simultaneously with the source region 48 and the drain region 49 when forming the Glue oxide film 47 by thermal oxidation.

Embodiment 4 FIG. 6 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
This figure shows a so-called bipolar CMO8 structure in which an OS'R field effect transistor and a bipolar transistor which can be formed by a similar self-alignment process are formed on the same chip.

In the figure, 61 is an n-channel M, O'S field effect transistor, 62 is a p-channel MO8 field effect transistor, 63 is a bipolar transistor, 68 is a p-type substrate, 64 is a p+ type buried layer, and 65 is an n+ type buried layer. , 67
69 is a p-type well, 69 is an n-type well, and 66 is a polycrystalline silicon film.

After forming an n1-type buried layer 65 and a p+-type buried layer 64 on a P-type substrate, epitaxial growth is performed and further impurity doping is performed to form an n-type well 69 and a p-type well 6.
7 was formed. Below, MO8 field effect transistor 61
．． The method of forming 62 is the same as in the first embodiment. In the bipolar transistor 63, the base electrode is drawn out using a polycrystalline silicon film 66, and the emitter is formed by oxidizing the surface of the polycrystalline silicon film 66 and removing the oxide film that was simultaneously formed on the substrate surface. It was formed by using a crystalline silicon emitter.

According to this structure, both bipolar and CMO8 transistors can be formed by the same self-alignment process, and it is possible to form fine T and SI with a small number of steps.

Example 5 FIG. 7(a) is a plan view of an inverter according to a fifth example of the present invention manufactured using the same process as shown in FIG. ), and (c) is a circuit diagram of the inverter.

In the figure, 43 is a wiring layer made of T x 812 film;
46 is a polycrystalline silicon film, 71 is an M wiring layer, 72 is a contact hole, 81 is a load MOS transistor, and 82 is a driver MOS transistor.

In this embodiment, the wiring between the drain of the load MOS transistor 81 and the source of the driver MOS transistor 82 can be done using the T i S i film 43 before forming the gate electrode of the MO3 field effect transistor. The distance between transistors could be reduced. Further, only one contact hole 72 for the AI wiring 71 is required, making it possible to simplify the process.

〔Effect of the invention〕

According to the present invention, a MO5ffi field effect transistor having a channel length smaller than the minimum feature size can be formed by a self-aligned process. Further, since the wiring patterning step can be performed before forming the 1-transistor, the process can be simplified.

Also, the source train'? Since rii is drawn out by the polycrystalline silicon film and connected to the wiring layer on the insulating film, it is possible to prevent contact failures such as penetration of AI into the source I-twin as in the prior art. Furthermore, since the gate electrode can be formed last, it is possible to use AQ, and the buried structure is also effective in flattening the device plane. Thus, the effects of the present invention are significant.

[Brief explanation of the drawing]

1 is a sectional view of an MO3 field effect transistor according to a first embodiment of the present invention, FIGS. 2(a) to 2(C) are process sectional views showing a method for manufacturing the transistor of FIG. Figure (a
) to (d) are cross-sectional views showing the manufacturing process of a typical conventional M,O3 field effect transistor;
-(e) are process cross-sectional views showing a method for manufacturing a MO8I transistor according to a second embodiment of the present invention, and FIG. 5 is a cross-sectional view of an LDD I transistor according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and FIGS. 7(a) to (c) are a plan view and a cross-sectional view of an inverter according to a fifth embodiment of the present invention, respectively. It is a circuit diagram. 1... Source region 2... Drain region 3... Gate electrode 4... l(!l) Edge film 5... Polycrystalline silicon film 6... Wiring layer 7... Gate oxide film 8 ...Semiconductor substrate 70...Surface oxide film of polycrystalline silicon film Patent attorney Junnosuke Nakamura 1-1 Figure 5 Figure 52 It\Thick 7 Redo Ishinohi Q 2 Figure 21 ^1 7) Spear 3

Claims (1)

[Claims] 1. A semiconductor substrate, a wiring layer formed on the semiconductor substrate via an insulating film, and a wiring layer provided through the wiring layer and the insulating film so that the semiconductor substrate is exposed. a polycrystalline silicon film left on the side wall of the opening, a gate insulating film formed on the surface of the semiconductor substrate between the polycrystalline silicon film, and the polycrystalline silicon film. 1. A semiconductor device comprising: a gate electrode formed in a cavity with an insulating film interposed therebetween; and source/drain regions formed on the surface of the semiconductor substrate on both sides of the gate electrode. 2. forming an insulating film on the semiconductor substrate; forming a conductive layer on the insulating film; and etching the insulating film and the conductive layer to expose the semiconductor substrate. a step of forming a penetrating opening, a step of depositing a polycrystalline silicon film and leaving the polycrystalline silicon film only on the sidewall of the opening by anisotropic etching, and forming the conductive layer in a predetermined pattern. a step of forming an oxide film and source/drain regions on the surfaces of the semiconductor substrate and the polycrystalline silicon film;
A method for manufacturing a semiconductor device, comprising the step of filling an electrode material into a gap between the polycrystalline silicon films through the oxide film to form a gate electrode.