JP2924947B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Metal Ox
by ide Semiconductor) structure relates to a method of manufacturing a semiconductor equipment, in particular, MOSFET (Field Effect Transisto
To improve the short channel effect upon miniaturization of r), the semiconductor equipment that shallower junction depth of the source and drain respectively of the diffusion layer, and to reduce parasitic resistance and parasitic capacitance
And a method for producing the same.

[0002]

2. Description of the Related Art Generally, in order to improve a short channel effect which is a problem in miniaturization of a MOSFET (in particular, remarkable at a gate length of 0.3 μm or less), the diffusion of the source and the drain must be improved. There are methods such as reducing the junction depth of the layer, particularly the diffusion layer near the gate end, and reducing the thickness of the depletion layer extending from the drain.

For example, as a method of reducing the junction depth of a diffusion layer, there is a low energy ion implantation method. This means that an implantation energy of 1 is applied to the source and drain formation regions.
0 keV and the impurity dose is 1 × 1
This is a method in which impurity ions are introduced at a dose as low as about 0 ¹³ / cm ² , and the depth of the implanted impurities can be reduced to about several tens of nanometers.

As another means for reducing the junction depth of a diffusion layer, there is a method using a solid layer diffusion method (for example, M.I.
Ono et al. “SUB-50 NM GATE LENGTH N-MOSFETS WITH 1
0NMPHOSPHORUS SOURCE AND DORAIN JUNCTIONS ”, IEDM
93, 119, (1993)).

According to this method, an insulating film containing impurities (for example, boron silicate glass or phosphorus silicate glass) is first formed on the silicon surface in the source and drain formation regions, and then impurities in the insulating film are introduced into the silicon by heat treatment. Spread. This makes it possible to reduce the depth of the diffusion layer from about 10 nanometers to 40 nanometers, and to obtain a shallower diffusion layer than the ion implantation method.

However, in any of the above methods, the junction depth of the diffusion layer can be reduced, but the resistance increases and the device characteristics deteriorate. This is because the impurity concentration decreases from the surface to the inside in any of the methods, and the degree of the decrease is substantially determined by the heat treatment. For this reason, if a portion where the impurity concentration is equal to the channel impurity concentration is determined as a junction, the total impurity amount on the surface side is determined by the depth distribution of the impurity concentration, and the total impurity amount decreases as the junction becomes shallower.

On the other hand, as a means for reducing the junction depth and further improving the resistance, there is a method called a pocket injection method.
This is because the impurity implantation amount is increased in order to increase the impurity concentration of the source and the drain, and the impurity of the opposite conductivity type is added below the source and the drain for the purpose of preventing the junction depth from being increased by the increased amount. In this method, the diffusion layer bonding surface is brought to the front side. Thereby, a shallow and low-resistance diffusion layer can be formed. Furthermore, the depletion layer extending from the drain can be made thin, and as a result, the short channel effect can be improved.

Next, referring to FIG. 6, a pocket injection structure conventionally proposed (for example, S. Oguro et al. “A ha
lf micron MOSFET using double implanted LDD ”, IE
DM 82,718, (1982)). FIG. 6 is a schematic cross-sectional view in the middle of a step showing a method of forming a pocket structure in an n-type MOSFET.

First, as shown in FIG. 6A, a P-type channel impurity layer 62 is formed in an element formation region on a P-type silicon substrate 61 by ion implantation. An insulating film 63 is formed, and then a gate electrode 64 is formed.

In the next step, as shown in FIG. 6B, a P-type impurity is implanted at a concentration higher than the channel concentration using the gate electrode 64 as a mask to form a P-type impurity region 67. Thereafter, an N-type impurity is implanted shallower than the P-type impurity region 67 to form an N ⁻ source 65 and an N ⁻ drain 6.
6 is formed.

In the next step, as shown in FIG. 6C, a sidewall insulating film 68 is formed, and then an N-type impurity is ion-implanted deeper than the P-type impurity region 67 to form an N ⁺ source 69.
And an N ⁺ drain 70 is formed. As a result, N ^-
A pocket region 71 surrounded by the source 65 and the N ⁻ drain 66, the N ⁺ source 69 and the N ⁺ drain 70, and the channel impurity layer 62 can be formed.

Subsequent steps such as wiring are performed by a usual conventional method.

However, the problems of this method include the following. First, wraparound to the gate direction of the pocket region 71 substrate effect is increased by (N ^- around to the channel side of the drain 66 ^- source 65 and N).
As shown in FIG. 6C, when viewed in a cross section cut parallel to the gate length direction, the depth of the N ⁺ drain 70 is at least about 0.1 μm, and the side wall insulating film 68 Considering that at least about 50 nm is provided, the length of the pocket region 71 in contact with the drain diffusion layers (the N ⁻ drain 66 and the N ⁺ drain 70) is 0.1 μm or more in this cross section.

In the pocket region 71, since the impurity amount is higher than that of the channel, the depletion layer formed there is thin and the contact area with the drain diffusion layer is large. Speed decreases.

On the other hand, another method conventionally proposed as a technique for pocket injection is disclosed in, for example,
No. 02568. This will be described with reference to FIG. This has been proposed to improve the problem of the method of FIG.

First, as shown in FIG. 7A, two types of P-type channel impurities are implanted into an element formation region on a P-type silicon substrate 61 to form a deep ion-implanted layer. After forming 72, a shallow channel layer 73 is formed. In the subsequent steps, a gate insulating film 74, a gate electrode 75, and a sidewall insulating film 76 are sequentially formed.

In the next step, after the exposure step, FIG.
As shown in (b), a resist 77 is formed on the side wall insulating film 76 at a position slightly away from the gate electrode 75, and using the resist 77 as a mask, the resist 77 has a higher concentration than the deep ion implantation layer 72 and the shallow channel layer 73. P-type impurities are ion-implanted so as to be deeper than the deeper ion-implanted layer 72 to form the pocket region 78.

In the subsequent steps, as shown in FIG. 7C, after removing the resist 77, phosphorus ions and arsenic ions are sequentially ion-implanted to form N ⁺ source 81 and N ⁺ drain 82, respectively. The next step is a heat treatment by, N extend the source and drain each end by diffusing phosphorus into the gate terminal direction from the pocket region 78 to the gate electrode 75 side ^- to form respective drain 80 ^- source 79 and N.

In the method shown in FIG. 7, the substrate effect caused by the wraparound of the pocket region in the gate direction, which is a problem in the method described with reference to FIG. 6, can be suppressed, and the formation of the pocket region is affected. It is possible to prevent the N ^- source 79 and the N ^- drain 80 from increasing in resistance.

[0020] However, as a problem, N ^- source 79 and N ^- junction depth of the drain 80 is formed by diffusion,
The pocket region 7 is located at a position away from the end of the gate electrode 75.
8, the junction becomes deeper and does not contribute to the improvement of the short channel effect even if the pocket region is formed. Further, since the mask for forming the pocket region is formed by registering the resist 77, it is at least about 0.1 μm, and the capacity of the diffusion layer becomes large.

[0021]

[0005] Of the method of manufacturing the above-mentioned conventional semiconductor <br/> equipment, the low energy ion implantation or solid phase diffusion method, improves the shallow to the short channel effect junction depth However, in this case, the resistance of each of the source and the drain is large. As a result, MOSF
There is a problem that the current of the ET decreases and the speed of the element decreases.

In the pocket implantation method, since the pocket region is in wide contact with each of the source and the drain, and is in long contact with each of the deep source and the deep drain in the depth direction, the parasitic capacitance is increased and the speed of the device is reduced. There is a problem.

An object of the present invention is to provide a MOSFET (Field Ef).
To improve the short channel effect upon finer fect Transistor), shallow junction depth of the source and drain respectively of the diffusion layer, and to provide a method of manufacturing a semiconductor equipment to reduce the parasitic resistance and parasitic capacitance It is in.

[0024]

[0025]

[0026]

[0027]

One embodiment of a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device using a MOS structure.
In a method of manufacturing a conductor device , a channel layer is formed on a surface of an element formation region of a conductive semiconductor substrate, a gate insulating film is formed on a surface of the channel layer, and a gate electrode is formed on a surface of the gate insulating film. Forming a thin first insulating film on the side surface of the gate electrode, and implanting required impurity ions into the surface of the semiconductor substrate by irradiation to form a required first conductive type thin film; A step of selectively growing a semiconductor while forming a facet on the surface of the semiconductor opposite to the gate electrode of the first insulating film; and implanting required impurity ions by irradiation to form the first conductive thin film. Forming a region of the opposite conductivity type below the gate electrode end under the first conductivity type thin film, and forming a second insulation film on a side surface of the first insulation film, Implant impurity ions by irradiation , And a step of forming the first high concentration of the conductive thin film of the same conductivity type as a conductivity type thin film conductor, said selectively grown semiconductor and the surface of the semiconductor substrate.

[0028]

[0029]

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

[0031] FIG. 1 is a schematic sectional view showing a semiconductor device as a reference <br/> the first embodiment for the present invention.

[0032] First, the semiconductor device will be described by reference type <br/> status of the first embodiment with reference to FIG. This structure has a pocket region 10 in addition to the structure of a normal MOSFET as shown in the figure.

In the normal structure of the MOSFET shown in FIG. 1, a field insulating film, an N-type well and a field insulating film are formed at predetermined positions on the surface of a P-type silicon substrate 1 having an impurity concentration of about 1 × 10 ¹⁴ cm ^−3. P-type well (name symbols are omitted), a channel impurity layer 2 having a concentration of about 5 × 10 ¹⁷ cm ^−3, a gate insulating film 3 having a thickness of about 7 nm, for example, a stacked structure of polysilicon and a metal such as tungsten. The formed gate electrode 4, a sidewall insulating film 5 having a width of about the gate length, a shallow source 6 having a depth of about 50 nm, a shallow drain 7 having a depth of about 50 nm, a deep source 8 having a depth of about 200 nm, and a depth of about 200 nm A deep drain 9 is formed.

The added pocket region 10 has a conductivity type opposite to that of the drain and has an impurity concentration of 2 × 10 ¹⁸ cm ^−3.
And shallow source 6 and shallow drain 7
It is located below each gate end portion and between the channel impurity layer 2 and overlaps a part of each. For this reason, in each of the shallow source 6 and the shallow drain 7, a part has been inverted to the opposite conductivity type, and the junction depth is shallow from 20 nm to 30 nm. The pocket region 10 is formed apart from each of the source 8 and the drain 9 having a small width and a large depth. As a result, the area in contact with each of the source and the drain in the lateral direction and the depth direction is reduced.

The short channel effect is improved by this shallow coupling, and the area where the high-concentration pocket region is in contact with the source and the drain is small, so that the capacitance of the diffusion layer can be reduced.

Next, referring to the schematic sectional view of FIG.
A semiconductor device according to the reference embodiment will be described.
This structure, as shown, is a reference to the first embodiment described above.
A pocket region 10 is provided at a different position in the structure of a normal MOSFET different from the embodiment.

In the normal structure of the MOSFET shown in FIG. 2, a field insulating film is formed at a predetermined position on the surface of a P-type silicon substrate 1 having an impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ .
N-type well and P-type well (name symbols are omitted) Channel impurity layer 2 having a concentration of about 5 × 10 ¹⁷ cm ⁻³ , gate insulating film 3 having a thickness of about 7 nm, for example, metal such as polysilicon and tungsten A gate electrode 4, a sidewall insulating film 5 having a width of about the gate length, a source 21 having a depth of about 100 nm, and a drain 22 having a depth of about 100 nm are formed.

The pocket region 10 shown in FIG. 2 has a conductivity type opposite to that of the drain and has an impurity concentration of 2 × 10 ¹⁸ c.
m ⁻³ , a width of about 30% of the gate length, the source 21 and the drain 22, and the channel impurity layer 2
Are located below the gate end portion, and partially overlap each of the source 21 and the drain 22. Therefore, in each of the source 21 and the drain 22, a part thereof is inverted to the opposite conductivity type, and the junction depth is shallow from 40 nm to 50 nm. Further, since the width of the pocket region 10 is as small as 30% or less of the gate length, the area in contact with each of the source and the drain is small.

As a result, the short channel effect is improved by the shallow junction, and the area of the high-concentration pocket region in contact with the source and the drain is small, so that the capacitance of the diffusion layer can be reduced.

The above description, although each source and drain describes the case of one layer deep, the source is formed from a depth of two different layers such as the first embodiment of the reference described above and In the case of the drain, even when the pocket region and the deep source and the deep drain are separated from each other or in contact with each other, the width of the pocket region is set to 30% of the gate length by applying the reference mode of the present embodiment. The capacity can be reduced by suppressing the content below.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the schematic cross-sectional views of each step in FIG. Implementation form of this is to create a groove of V-shaped by utilizing the selective growth of silicon on the side of the gate, a manufacturing method manufactured that form a pocket structure using the groove.

First, the structure resulting from the first step is shown in FIG.
This is shown in FIG. In this step, the impurity concentration is 1 × 1
A field insulating film, an N-type well, and a P-type well (name symbols are not shown) are formed at predetermined positions on the surface of the P-type silicon substrate 1 of about 0 ¹⁴ cm ^-3 to determine an element formation region. In the next step, for example, when an N-type MOSFET is formed, boron is ion-implanted into the surface of the P-type well in the element formation region at an energy of 50 keV and 5 × 10 ¹² cm ⁻² to form a channel impurity layer having a depth of about 300 nm. Form 2 Subsequently, a gate insulating film 3 having a thickness of about 7 nm is formed by thermal oxidation, and then a 150 nm-thick is formed by vapor phase growth.
After forming polysilicon, resist coating, gate exposure and etching of the polysilicon (not shown)
Are sequentially processed to form the gate electrode 4.

FIG. 3 (b) shows the resulting structure of the next step. In this step, a silicon oxide film is grown to a thickness of 20 nm on the entire upper surface by vapor phase growth, and then anisotropically etched to form a first sidewall insulating film 31. In the subsequent step, the arsenic ions were converted to an energy of 15 keV and 5 × 1.
The channel impurity layer 2 is irradiated with ions at 0 ¹⁴ cm ^-2 and ion-implanted to form a first source 32 and a first drain 33. At this time, the junction depth of each of the first source 32 and the first drain 33 formed by arsenic ion implantation is about 50 nm. In the subsequent steps, silicon is selectively formed on the silicon surface only by a facet (30 degrees or 45 degrees) by vapor phase growth to a thickness of 30 nm.
To form a selective epitaxial growth layer 34.

In the above description, after the first side wall insulating film 31 is formed, the first source 32 and the first
Although the respective drains 33 are formed, the order may be reversed, and the effect of the present invention is not impaired. Although the selective epitaxial growth layer is made of silicon here, germanium or silicon germanium may be used.

FIG. 3 (c) shows the resulting structure of the next step. In this step, boron fluoride (B
F ₂ ) ion energy of 30 keV, 1 × 10 ¹⁴ cm
Irradiate with ^-2 for ion implantation. As a result, a boron distribution reflecting the shapes of the first sidewall insulating film 31 and the selective epitaxial growth layer 34 is formed and overlaps with the arsenic distributions of the first source 32 and the first drain 33, so that the first source 32 and the first drain A part of each of 33 is inverted to a P-type to form a P-type pocket injection region 35.

As a result, in the vicinity of the end of the gate electrode 4 of each of the first source 32 and the first drain 33, which are diffusion layers, the lower portion of about 30 nm is inverted to the P type, the junction depth is about 20 nm, and the pocket depth is about 20 nm. The length of the contact portion between the implantation region 35 and the first drain 33 is 4 when viewed in cross section.
It becomes as small as about 0 nm.

FIG. 3 (d) shows the resulting structure of the next step. In this step, a silicon oxide film is grown to a thickness of 80 nm by vapor phase growth and anisotropically etched to form a second sidewall insulating film. In the subsequent step, the surface is irradiated with arsenic ions at an energy of 50 keV and 5 × 10 ¹⁵ cm ⁻² to perform ion implantation and heat treatment (for example, 1000 ° C. for 10 seconds) to form the second source 37 and the second drain 38. .

As a result, most of each of the selective epitaxial growth layer 34 and the gate electrode 4 which have become P-type by the ion implantation of BF ₂ in the process described with reference to FIG. It is inverted to N-type by implantation and heat treatment. The depth of the second source 37 and the second drain 38 is about 200 nm.

The subsequent steps of performing wiring and the like are the same as in the conventional case.

The above Your facilities in the form, that is, according to the <br/> manufacturing method according to the invention, the junction depth of the source and drain diffusion layer near the gate edge can shallow to about 20 nm, and also the amount of impurities Can be ^increased to 4 × 10 ¹⁴ cm ^-2 and 1 more
Resistance can be improved by more than an order of magnitude. The contact portion between the pocket injection region and the drain is about 40 nm in cross section, which can be reduced to less than half compared with the conventional method.

Next, with reference to the schematic sectional view another step 4, a method for manufacturing a semiconductor device according to a third exemplary reference embodiment. Reference embodiment of this third embodiment is described above
This is another manufacturing method for the present invention .

First, the structure resulting from the first step is shown in FIG.
This is shown in FIG. The steps up to the production of the gate electrode 4 are the same as those described with reference to FIG.

FIG. 4B shows the structure resulting from the next step. In this step, a first sidewall insulating film 31 is formed by growing a silicon nitride film to a thickness of 20 nm by vapor phase growth on the entire upper surface and then performing anisotropic etching. In the subsequent step, the arsenic ions are converted to an energy of 15 keV, 5 × 10 ¹⁴ c
The channel impurity layer 2 is irradiated with ions at m ⁻² and ion-implanted to form a first source 32 and a first drain 33. As a result, the first source 32 formed by arsenic ion implantation is formed.
And the first drain 33 has a junction depth of 50 nm.
It is about. In a subsequent step, silicon is grown by vapor phase growth to a thickness of 30 nm selectively only on the silicon surface so as to be in contact with the first sidewall insulating film 31 to form a selective epitaxial growth layer 41.

In the above description, the first source 32 and the first drain 33 are formed by ion-implanting arsenic after the formation of the first sidewall insulating film 31, but the order may be reversed. Although the selective epi growth layer is described as silicon, germanium or silicon germanium may be used.

The resulting structure from the next step is shown in FIG. In this step, the first sidewall insulating film 31 is removed by etching with phosphoric acid, and the upper surface is irradiated with BF ₂ ions at an energy of 30 keV and at 1 × 10 ¹⁴ cm ⁻² for ion implantation. At this time, a boron distribution reflecting the shapes of the gate electrode 4 and the selective epi growth layer 41 is formed and overlaps with the arsenic distribution of the first source 32 and the first drain 33. A part is inverted to the P type, and the P type pocket injection region 4
You can do 2.

As a result, in the first source 32 and the first drain 33, which are diffusion layers, in the vicinity of the end of the gate electrode 4, the lower portion of about 30 nm is inverted to the P type, the junction depth is about 20 nm, and the pocket implantation is performed. The contact portion between the region 42 and the first drain 33 is as small as about 40 nm when viewed in cross section.

FIG. 4D shows the structure as a result of the next step. In this step, a silicon oxide film is grown to a thickness of 80 nm on the side surface of the gate portion by vapor phase growth and anisotropically etched to form a second sidewall insulating film 43. In the subsequent steps, the selective epi growth layer 41 and the gate electrode 4 are irradiated with arsenic ions at an energy of 50 keV and 5 × 10 ¹⁵ cm ⁻² to perform ion implantation, and heat treatment (for example, 1000 ° C., 10 seconds) to perform the second source 44. And the second drain 45 are formed. Most of the selective epitaxial growth layer 41 and the gate electrode 4 which have been made P-type by the ion implantation of BF ₂ in the process described with reference to FIG. 4C are inverted to N-type by this arsenic ion implantation and heat treatment. . The depth of the second source 44 and the second drain 45 is about 200 nm.

The subsequent steps are ordinary steps for forming wirings and the like, and a description thereof will be omitted.

[0059] The manufacturing method according to the third embodiment of the reference embodiment can shallow junction depth of the source and drain respectively of the diffusion layer is about 20nm near the gate end and the impurity amount 4 × 10 ¹⁴ cm ^-2 Therefore, the resistance value can be improved by one digit or more than the conventional method. The contact portion between the pocket injection region and the drain is about 40 nm in cross section, which can be reduced to less than half compared with the conventional method.

Next, with reference to the schematic sectional view another step 5, a method for manufacturing a semiconductor device according to a fourth embodiment of the reference embodiment. Reference embodiment of this fourth embodiment is described above
This is a different manufacturing method from the two manufacturing methods .

First, the structure resulting from the first step is shown in FIG.
This is shown in FIG. The steps up to the fabrication of the gate electrode 4 are the same as those described with reference to FIG.

FIG. 5B shows the structure obtained by the next step. In this step, first, a silicon nitride film is grown to a thickness of 20 nm on the entire upper surface by vapor phase growth and anisotropically etched to form a first sidewall insulating film 31. In the subsequent step, arsenic ions are supplied to the channel impurity layer 2 with an energy of 15%.
The first source 32 and the first drain 33 are formed by irradiation with keV and irradiation at 5 × 10 ¹⁴ cm ⁻² and ion implantation. At this time, the junction depth of the first source 32 and the first drain 33 formed by arsenic ion implantation is about 50 nm.

In the above description, the first source 32 and the first drain 33 are formed by ion-implanting arsenic after forming the first side wall insulating film 31, but the order may be reversed.

FIG. 5C shows the structure resulting from the next step. In this step, first, a silicon oxide film is grown to a thickness of 80 nm by vapor phase growth on the side surface of the gate and anisotropically etched to form a second sidewall insulating film 51. The following steps
Arsenic ions are applied to the upper surface at an energy of 50 keV, 5 × 1
The second source 52 and the second drain 53 are formed by irradiating at 0 ¹⁵ cm ^-2 and implanting ions.

FIG. 5D shows a structure resulting from the next step. In this step, after the first sidewall insulating film 31 is removed by etching with phosphoric acid, BF ₂ ions are irradiated at an energy of 30 keV and 1 × 10 ¹⁴ cm ⁻² to be ion-implanted. At this time, the gate electrode 4 and the second sidewall insulating film 5
1 is formed and the arsenic distribution of the first source 32 and the first drain 33 overlaps.
A part of each of the first source 32 and the first drain 33 is inverted to P-type, and a P-type pocket injection region 54 is formed. Subsequent steps are heat treatment (for example, 1000 ° C., 10 ° C.).
Seconds) to activate the impurities.

As a result, in the vicinity of the gate ends of the first source 32 and the first drain 33, which are the diffusion layers, the lower side is inverted to P-type about 30 nm, the junction depth becomes about 20 nm, and the pocket injection region and the drain are The contact length is as small as about 40 nm when viewed in cross section.

The subsequent steps are ordinary steps for forming wirings and the like, and illustration and description thereof are omitted.

[0068] The above, according to the fourth exemplary reference embodiment, the source and drain junction depth of each of the diffusion layer near the gate edge is shallow in the order of 20 nm, and 4 × also the amount of impurities
Since the resistance can be ^increased to 10 ¹⁴ cm ^-2 , the resistance value is 1
Can improve by more than an order of magnitude. The contact portion between the pocket injection region and the drain has a length of about 40 nm when viewed in cross section, which can be reduced to half or less compared to the conventional method.

[0069]

[0070]

[0071]

As described above , according to the method of manufacturing a semiconductor device of the present invention, when a pocket region is formed by implanting impurity ions, a V-shaped structure or a rectangular groove serving as a mask is formed. The pocket region can be formed in a self-aligned manner, the length of the pocket region (as viewed in the channel length direction) can be arbitrarily set, and the junction can be formed away from the deep N ⁺ drain. As a result, the alignment can be made unnecessary, and the capacitance of the diffusion layer can be reduced by reducing the junction area between the pocket region and the drain.

That is, in the formation of the source and the drain of the MOSFET, the junction depth of the diffusion layer can be improved to less than half of the conventional one, and the resistance of the diffusion layer can be improved to one digit or less than that of the conventional one. In addition, the capacity of the diffusion layer can be reduced to about half of the conventional capacity. Therefore, improvement of the short channel effect and improvement of the switching speed due to miniaturization can be expected.

The present invention is particularly effective for MOSFETs having a gate length of 0.3 μm or less, in which the short channel effect is remarkable.

[Brief description of the drawings]

It is a schematic sectional view showing a semiconductor device according to a first reference embodiment for the present invention; FIG.

It is a schematic sectional view showing a semiconductor device according to a second reference embodiment for the present invention; FIG.

3 is a schematic sectional view another step showing a method of manufacturing a semiconductor device in the form status of one embodiment of the present invention.

Is a schematic sectional view another step showing a method of manufacturing a semiconductor device according to a third reference embodiment for the present invention; FIG.

5 is a another cross-sectional schematic view process showing a manufacturing method of a semiconductor device according to a fourth reference embodiment for the present invention.

FIG. 6 is a schematic sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.

FIG. 7 is a schematic sectional view showing another example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Channel impurity layer 3 Gate insulating film 4 Gate electrode 5 Side wall insulating film 6 Shallow source 7 Shallow drain 8 Deep source 9 Deep drain 10 Pocket region 21 Source 22 Drain 31 First sidewall insulating film 32 First source 33 First Drain 34, 41 selective epi growth layer 35, 42, 54 pocket injection region 36, 43, 51 second sidewall insulating film 37, 44, 52 second source 38, 45, 53 second drain

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/265 H01L 21/336

Claims (2)

(57) [Claims] 1. A MOS (Metal Oxide Semiconductor)
In a method of manufacturing a semiconductor device having a structure , a channel layer is formed on a surface of an element forming region of a conductive semiconductor substrate, a gate insulating film is formed on a surface of the channel layer, and a gate electrode is formed on a surface of the gate insulating film. Forming a thin first insulating film on the side surface of the gate electrode, and irradiating the surface of the semiconductor substrate with required impurity ions to form a required first conductivity type thin film; A step of selectively growing a semiconductor while forming a facet on the surface of the semiconductor opposite to the gate electrode of the first insulating film; The region of the conductivity type is formed under the first electrode below the end of the gate electrode.
Forming a second insulating film on a side surface of the first insulating film and irradiating a required impurity ion with the same conductive type as the first conductive type thin film. Forming a high-concentration conductive thin film on the surface of the selectively grown semiconductor and the semiconductor substrate. 2. A semiconductor device according to claim 1, wherein the order of the step of forming the first insulating step and the first membrane to the <br/> formation of the conductive thin film is reversed Manufacturing method.