CN111952238A - SOI substrate having cavity structure and method for manufacturing the same - Google Patents

SOI substrate having cavity structure and method for manufacturing the same Download PDF

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Publication number
CN111952238A
CN111952238A CN202010849555.9A CN202010849555A CN111952238A CN 111952238 A CN111952238 A CN 111952238A CN 202010849555 A CN202010849555 A CN 202010849555A CN 111952238 A CN111952238 A CN 111952238A
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substrate
layer
cavity structure
cavity
sacrificial
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CN111952238B (en
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俞文杰
刘强
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The invention provides an SOI substrate with a cavity structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first substrate, forming a first sacrificial layer, a second sacrificial layer and a side wall structure on the first substrate, etching a first groove and a second groove in sequence based on the side wall structure, using the second groove as a subsequent cavity structure, and bonding the first substrate and the second substrate to obtain the SOI substrate with the cavity structure. The invention prepares the SOI substrate with embedded nano-scale cavity by using the side wall mask, and forms a groove structure by using the protruded side wall structure as the mask for etching to obtain the cavity structure, and further can prepare the nano-scale cavity in the top silicon, thereby preventing the top silicon from being damaged because the characteristic dimension of the cavity is larger and the stress born by the top silicon easily exceeds the limit when preparing the SOI substrate with micron-scale and submicron-scale cavities.

Description

SOI substrate having cavity structure and method for manufacturing the same
Technical Field
The invention belongs to the technical field of semiconductor device structure design and manufacture, and particularly relates to an SOI substrate with a cavity structure and a preparation method thereof.
Background
The cavity is prepared in the semiconductor substrate, the cavity can play the roles of insulation and the like, and the semiconductor functional device can be prepared on the cavity, so that the characteristics of the device, such as good subthreshold value and the like, can be kept. For example, to improve the performance and cost-to-performance ratio of integrated circuit chips, shrinking device feature sizes and thus increasing integration density is a major approach. However, as the device size is reduced, power consumption and leakage current become the most significant concerns. Silicon-On-Insulator (SOI) structures have become the preferred structure for deep sub-micron MOS devices because of their ability to suppress short channel effects and improve device scaling. With the development of SOI technology, researchers have developed a new transistor structure son (silicon on nothing) transistor. The SON forms a localized SOI under the channel through a "void" structure, and the SON technology is one way to reduce the short channel effects of SOI devices. Compared with the SO1 device, the SON device removes the buried oxide layer below the channel, reduces the interface state of the bottom of the top silicon layer, reduces the influence of the body charge in the buried oxide layer on the conducting characteristic of the channel, reduces the parasitic capacitance between the channel and the substrate, and simultaneously has good total dose radiation resistance. Compared with an SOI device, the SON device has certain enhancement on the inhibition capability of the short channel effect due to the removal of back charge and capacitance influence.
However, in the conventional process for manufacturing a semiconductor substrate having a cavity, a Smart-cut (Smart-cut) process is often required along a peeling layer, for example, when a SON substrate is manufactured, a top layer silicon is required to be intelligently peeled, for example, taking hydrogen ion implantation to form the peeling layer as an example, in the Smart-cut process, hydrogen bubbles are generated at a peeling interface, and generate a large pressure on the peeling layer, so that the peeling layer finally obtained is damaged, and when a part of the top layer silicon in the SON substrate is damaged, the substrate cannot meet application requirements of an integrated circuit, a micro electro mechanical system and the like. In the prior art, if the size of the cavity is larger, the material layer (such as top silicon) above the cavity is easy to break. When the SOI substrate containing micron-scale and submicron-scale cavities is prepared by a process scheme including intelligent stripping, the stress borne by the top silicon easily exceeds the limit due to the large characteristic size of the cavities, and the damage is generated. And it is difficult to effectively prepare a nano-scale cavity structure in the structure of the SOI by a simple process by means of the existing lithography technology. In addition, the cavity formed in the intermediate insulating layer is difficult to effectively meet the performance requirement of the device, and the overall performance of the device is further improved and limited.
Therefore, it is necessary to provide an SOI substrate having a cavity structure and a method for fabricating the same to solve the above-mentioned technical problems in the prior art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an SOI substrate with a cavity structure and a method for manufacturing the SOI substrate, which are used to solve the problems in the prior art that when an SOI substrate with a cavity of micron or submicron scale is manufactured, due to a large characteristic dimension of the cavity, a material layer above the cavity is prone to exceed a limit of stress, breakage occurs, and the conventional SOI substrate with a cavity structure has a single structure, so that it is difficult to effectively meet device requirements, and improvement of overall performance of the device is limited.
To achieve the above and other related objects, the present invention provides a method for manufacturing an SOI substrate having a cavity structure, the method comprising the steps of:
providing a first base, wherein the first base comprises a first substrate and a first dielectric layer formed on the first substrate;
forming a first sacrificial layer on the first dielectric layer, wherein the first sacrificial layer comprises a plurality of first sacrificial units which are arranged at intervals and a first opening which exposes the first dielectric layer, and the first opening defines the position of a cavity structure to be formed;
forming side wall structures on the side walls of the first sacrificial units, and forming second sacrificial layers on the surfaces of the first dielectric layers exposed among the side wall structures, wherein the second sacrificial layers comprise a plurality of second sacrificial units which are arranged at intervals, the first openings are filled with the second sacrificial units, and the width of the side wall structures defines the width of the cavity structures;
performing ion implantation on the first substrate to form a preset stripping layer in the first substrate;
removing the side wall structure and the first dielectric layer corresponding to the lower part of the side wall structure to form a first groove;
removing the first sacrificial layer and the second sacrificial layer, and etching the first substrate downwards based on the first groove to form a second groove, wherein the bottom of the second groove is higher than the preset stripping layer;
providing a second substrate, and bonding one side of the first substrate, on which the second groove is formed, with the second substrate to obtain an initial bonding structure, wherein the second groove forms the cavity structure;
and peeling the first base along the preset peeling layer, transferring a part of the first base onto the second base, and forming a transfer substrate film layer on the second base to obtain the SOI substrate with the cavity structure, wherein the SOI substrate is composed of the second base and the transfer substrate film layer.
Optionally, the step of forming the sidewall structure includes: forming a continuous second dielectric layer on the surface of the first sacrificial unit and the exposed surface of the first dielectric layer; and removing the first sacrificial unit and the second dielectric layer above the first dielectric layer, and reserving the second dielectric layer formed on the side wall of the first sacrificial unit to obtain the side wall structure.
Optionally, the material of the second dielectric layer is different from the material of the first dielectric layer.
Optionally, the thickness of the first dielectric layer is greater than 2 nm; the thickness of the first sacrificial layer is larger than the height of the cavity structure formed in the first substrate; the size of the side wall structure is in a nanometer level, and the width of the side wall structure is between 5nm and 15 nm.
Optionally, the step of forming the second sacrificial layer comprises: forming a second sacrificial material layer on the top of the first sacrificial unit, the surface of the side wall structure and the surface of the first medium layer exposed among the side wall structures; and thinning the second sacrificial material layer to expose the side wall structure to obtain the second sacrificial layer, wherein after thinning, the heights of the first sacrificial layer, the side wall structure and the second sacrificial layer are the same, and the heights are greater than the depth of the cavity structure.
Optionally, the method further includes, after forming the second groove: and thinning the first dielectric layer to a preset thickness or removing the first dielectric layer to control the surface roughness to be less than 0.5 nm.
Optionally, the step of performing the ion implantation to form the preset peeling layer includes: performing a first ion implantation on the first substrate to form an initial lift-off layer in the first substrate; and performing second ion implantation at the position of the initial peeling layer to form the preset peeling layer, wherein the implanted particles of the first ion implantation comprise B-containing impurities, and the implanted particles of the second ion implantation comprise at least one of H ions and He ions.
Optionally, a preset distance is provided between the preset peeling layer and the cavity structure to be formed, and the preset distance is set according to the cavity structure, wherein the setting manner includes that the preset distance is greater than 1/8 of the characteristic size of the cavity structure.
Optionally, the defining manner of the characteristic dimension of the cavity includes: defining a two-dimensional plane above the cavity structure parallel to the surface of the cavity structure; in the two-dimensional plane, a plurality of selected points are arranged above the cavity structure; for each said selected point, there are a number of straight lines passing through said selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are respectively adjacent to the selected point in two directions of the straight line extending through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum size of the cavity based on a number of the straight lines passing through each of the selected points; and selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the characteristic size of the cavity.
Optionally, peeling the first substrate along the predetermined peeling layer comprises: and carrying out reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment comprises the step of carrying out heating treatment on the semiconductor substrate with the cavity structure.
Optionally, the heat treatment is performed in a preset atmosphere, the preset atmosphere includes an oxygen atmosphere, so as to form a surface oxide layer on the surface of the transfer substrate film layer, and the surface oxide layer is removed to thin the transfer substrate film layer after the heat treatment is completed.
Optionally, after obtaining the semiconductor substrate with the cavity structure, the method further includes: it is right to shift the rete structure and carry out the attenuate processing, the attenuate processing is including adopting chemical mechanical polishing to carry out first attenuate and adopt the oxidation attenuate to carry out the second attenuate.
Optionally, the method further includes, after performing the thinning process, the steps of: and repairing the thinned surface to ensure that the thinned surface reaches atomic level flatness, wherein the repairing process comprises annealing the thinned semiconductor substrate with the cavity structure in a hydrogen atmosphere at the annealing temperature of between 800 and 1300 ℃.
Optionally, the second base includes a second substrate and an intermediate dielectric layer formed on the second substrate, and one side of the first base having the second groove is bonded to the intermediate dielectric layer.
Optionally, the first substrate includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate comprises a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2O3At least one of the substrate and the InP substrate.
The invention also provides an SOI substrate with a cavity structure, wherein the SOI substrate with the cavity structure is preferably prepared by the preparation method of the SOI substrate with the cavity structure provided by the invention, and can be prepared by other methods. Wherein the SOI substrate comprises:
the first substrate comprises a first substrate, wherein a groove structure with the size of a nanometer level is formed in the first substrate;
and the second base comprises a second substrate and an intermediate medium layer formed on the second substrate, one side of the first base, on which the groove structure is formed, is bonded with one side of the second base, on which the intermediate medium layer is formed, the groove structure exposes the intermediate medium layer, and the groove structure forms a cavity structure of the SOI substrate with the cavity structure.
Optionally, the first substrate includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate comprises a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2O3At least one of the substrate and the InP substrate.
As described above, according to the SOI substrate with the cavity structure and the preparation method thereof, the SOI substrate with the embedded nano-scale cavity is prepared by utilizing the side wall mask, the side wall structure is not a mask for blocking etching but a negative mask which needs to be etched, the side wall structure does not protrude and is embedded between the sacrificial layers to obtain the cavity structure, and further, the nano-scale cavity can be prepared in the top silicon, so that the phenomenon that when the SOI substrate with the micron-scale and submicron-scale cavities is prepared, the stress borne by the top silicon easily exceeds the limit and is damaged due to the large characteristic size of the cavity can be prevented. In addition, when the preset stripping layer is formed, the preset distance between the preset stripping layer and the cavity structure to be formed is larger than 1/8 of the characteristic dimension of the cavity structure, so that the material layer above the cavity structure is further prevented from being damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and the performance of a device are improved.
Drawings
Fig. 1 shows a process flow diagram for the preparation of an SOI substrate having a cavity structure of the present invention.
Fig. 2-14 show schematic views of structures obtained at various steps in the fabrication process of the SOI substrate having a cavity structure according to the present invention.
Fig. 15 shows a schematic diagram obtained for one characteristic dimension of the cavity of the SOI substrate having a cavity structure obtained by the present invention.
FIG. 16 is a schematic diagram of the stress on the material layer above the cavity structure in the smart peeling process.
Fig. 17 shows that at the corresponding release layer midline position above the cavity, the upper and lower edges are subject to the greatest compressive and tensile stresses, and the lower edge is susceptible to breakage.
Fig. 18 to fig. 30 are schematic views showing structures obtained at respective steps in the fabrication of the SOI substrate having a cavity structure according to the present invention using SOI as the first base.
Description of the element reference numerals
100 first substrate
101 first dielectric layer
102 first layer of sacrificial material
103 first sacrificial layer
103a first victim unit
103b first opening
104 second dielectric layer
105 side wall structure
106 second sacrificial material layer
107a second sacrificial layer
108 thinning the first sacrificial layer
108a thinning the first sacrificial unit
109 side wall structure after thinning
110 predetermined peeling layer
111 first groove
112 second recess
113 thinning the dielectric layer
114 transfer substrate film layer
200 second substrate
201 intermediate dielectric layer
S1-S8
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing an SOI substrate having a cavity structure, the method comprising the steps of:
s1: providing a first base, wherein the first base comprises a first substrate and a first dielectric layer formed on the first substrate;
s2: forming a first sacrificial layer on the first dielectric layer, wherein the first sacrificial layer comprises a plurality of first sacrificial units which are arranged at intervals and a first opening which exposes the first dielectric layer, and the first opening defines the position of a cavity structure to be formed;
s3: forming side wall structures on the side walls of the first sacrificial units, and forming second sacrificial layers on the surfaces of the first dielectric layers exposed among the side wall structures, wherein the second sacrificial layers comprise a plurality of second sacrificial units which are arranged at intervals, the first openings are filled with the second sacrificial units, and the width of the side wall structures defines the width of the cavity structures;
s4: performing ion implantation on the first substrate to form a preset stripping layer in the first substrate;
s5: removing the side wall structure and the first dielectric layer corresponding to the lower part of the side wall structure to form a first groove;
s6: removing the first sacrificial layer and the second sacrificial layer, and etching the first substrate downwards based on the first groove to form a second groove, wherein the bottom of the second groove is higher than the preset stripping layer;
s7: providing a second substrate, and bonding one side of the first substrate, on which the second groove is formed, with the second substrate to obtain an initial bonding structure, wherein the second groove forms the cavity structure;
s8: and peeling the first base along the preset peeling layer, transferring a part of the first base onto the second base, and forming a transfer substrate film layer on the second base to obtain the SOI substrate with the cavity structure, wherein the SOI substrate is composed of the second base and the transfer substrate film layer.
The method for manufacturing an SOI substrate having a cavity structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above-mentioned sequence does not strictly represent the manufacturing sequence of the method for manufacturing an SOI substrate having a cavity structure according to the present invention, and the skilled person can change the sequence of steps depending on the actual process, for example, the second base may be provided before the step of performing ion implantation on the first base to form a predetermined peeling layer. Fig. 1 shows only the manufacturing steps of the manufacturing method of the SOI substrate having the cavity structure in one example of the present invention.
First, as shown in S1 of fig. 1 and fig. 2, step S1 is performed to provide a first base, which includes a first substrate 100 and a first dielectric layer 101 formed on the first substrate 100. Specifically, the first substrate 100 may be a substrate formed of a single material layer, or may be a substrate formed of a stacked material layer structure. Wherein the first semiconductor substrate 101 may be Si, Ge, GaN, SiC, GaAs, AlGaN, Ga2O3The InP material layer may be a combination of two or more of the above material layers. Of course, the semiconductor device may be other crystalline semiconductors, and is not limited thereto, and a preset lift-off layer formed by subsequent ion implantation is formed in the first semiconductor substrate 100.
In addition, the first dielectric layer 101 may be an oxide layer, and the material of the oxide layer includes, but is not limited to, a silicon oxide layer, and of course, the first dielectric layer 101 may also be another insulating dielectric layer. In an example, the thickness of the first dielectric layer 101 is greater than 2nm, which is beneficial for the process of forming the cavity structure based on the first dielectric layer 101 and can be beneficial for the subsequent use as a device material layer. In a preferred example, the thickness of the first dielectric layer 101 is greater than 4nm, and may be, for example, 5nm or 8 nm.
Next, as shown in S2 of fig. 1 and fig. 3-4, step S2 is performed to form a first sacrificial layer 103 on the first dielectric layer 101, where the first sacrificial layer 103 includes a plurality of first sacrificial units 103a arranged at intervals and a first opening 103b exposing the first dielectric layer 101, and the first opening 103b defines a position of a cavity structure to be formed.
As an example, the step of forming the first sacrificial layer 103 may be forming a first sacrificial material layer 102 on the first dielectric layer 101, as shown in fig. 3, where the material of the first sacrificial material layer 102 includes, but is not limited to, polysilicon. In one example, the thickness of the first sacrificial material layer 102 is greater than the height of the cavity structure to be formed. Then, the first sacrificial material layer 102 is patterned, and the first sacrificial layer 103 is obtained by photolithography and etching processes, as shown in fig. 4. The edge position of the first opening 103b defines the position of the cavity structure in the finally formed SOI substrate.
Next, as shown in S3 in fig. 1 and fig. 5-8, performing step S3, forming sidewall structures 105 on sidewalls of the first sacrificial units 103a, and forming a second sacrificial layer 107 on the surface of the first dielectric layer 101 exposed between the sidewall structures 105, where the second sacrificial layer 107 includes a plurality of second sacrificial units 107a arranged at intervals, the first openings 103b are filled with the second sacrificial units 107a, and a width of the sidewall structures 105 defines a width of the cavity structure;
as an example, the step of forming the sidewall structure 105 includes: firstly, forming a continuous second dielectric layer 104 on the surface of the first sacrificial unit 103a and the surface of the exposed first dielectric layer 101, as shown in fig. 5; then, the first sacrificial unit 103a and the second dielectric layer 104 above the first dielectric layer 101 are removed, and the second dielectric layer 104 formed on the sidewall of the first sacrificial unit 103a is remained, so as to obtain the sidewall structure 105, as shown in fig. 6.
Specifically, the material of the second dielectric layer 104 may be the same as or different from the material of the first dielectric layer 101, and in a preferred example, the material of the second dielectric layer 104 and the material of the first dielectric layer 101, are different, thereby facilitating the formation of the sidewall structure 105 on the basis of selective etching. For example, the first dielectric layer 101 is SiO2When the second dielectric layer 104 is Si3N4. If the second dielectric layer is the same as the first dielectric layer in material, the precision requirement on the etching process is higher; if the materials of the second dielectric layer and the first dielectric layer are different, an etching scheme with a high selective etching ratio can be selected to etch the side wall, so that the first dielectric layer is ensured to be less damaged by over-etching. The width of the preset cavity structure is defined by the thickness of the second dielectric layer 104, that is, the width of the cavity structure is defined by the width of the sidewall structure 105.
In a preferred example, the thickness of the second dielectric layer 104 is in a nanometer range, so as to form a nanometer-scale cavity structure subsequently, for example, the thickness of the second dielectric layer 104 (i.e., the width of the sidewall structure 105) is between 3nm and 200nm, and may be between 5nm and 15nm, and the thickness of the second dielectric layer 104 may be selected to be 6nm, 8nm, 10nm, 12nm, 15nm, 20nm, and the like. Meanwhile, in a direction perpendicular to the width of the sidewall structure 105, that is, in a length direction of the first opening 103b perpendicular to the paper surface, the size of the sidewall structure may be set according to actual requirements of devices. Thereby obtaining a nanoscale cavity structure based on the size of the sidewall structure 105. In addition, in order to ensure that the nano-cavity can be successfully prepared, when the nano-cavity is etched, the depth-to-width ratio is less than 10: 1, such as 8:1, 7:1, 6:1, 3:1, preferably 5: 1.
as an example, the step of forming the second sacrificial layer 107 includes:
first, a second sacrificial material layer 106 is formed on the top of the first sacrificial element 103a, the surface of the sidewall structure 105, and the surface of the first dielectric layer 101 exposed between the sidewall structures 105, as shown in fig. 7. Wherein the material of the second sacrificial material layer 106 includes, but is not limited to, polysilicon. Preferably, the material of the first sacrificial layer is the same as the material of the second sacrificial layer. In addition, the thickness of the second sacrificial material layer 106 is preferably the same as the thickness of the first sacrificial layer.
Then, the second sacrificial material layer 106 is thinned to expose the sidewall structure 105, so as to obtain the second sacrificial layer 107, the thinning process includes but is not limited to CMP, wherein the heights of the first sacrificial layer 103, the sidewall structure 105 and the second sacrificial layer 107 after thinning are the same, and the height is greater than the depth of the cavity structure, as shown in fig. 8. In this step, the second sacrificial material layer 106 is thinned to obtain the second sacrificial layer 107, where the second sacrificial layer 107 may be regarded as including a second sacrificial element 107a and second openings, the second sacrificial element 107a is filled in the first openings 103b remaining after the formation of the sidewall structures 105, so as to fill the first openings 103b, and in addition, the second sacrificial layer 107 may also be regarded as including second openings alternately arranged with the second sacrificial elements 107a, and each of the second openings is filled with one first sacrificial element and two sidewall structures 105 respectively located at two sides of the first sacrificial element. In an example, the second sacrificial material layer 106 is thinned while the first sacrificial layer 103 and the side wall structure 105 are thinned, the first sacrificial layer 108 and the thinned side wall structure 109 are obtained after the thinning, the first sacrificial layer 108 comprises a plurality of thinned first sacrificial units 108a after the thinning, and the upper surfaces of the thinned first sacrificial units 108a, the thinned side wall structure 109 and the second sacrificial units 107a are flush with each other.
As an example, the height of the second sacrificial layer 107 is slightly larger than the height of the cavity structure to be formed later.
Next, as shown in S4 of fig. 1 and fig. 9, step S4 is performed to perform ion implantation on the first base, so as to form a predetermined peeling layer 110 in the first substrate 100. As an example, before ion implantation is performed on the first substrate, the surface of the substrate needs to be polished to be thin, so that the top sacrificial layer has a uniform thickness and the surface roughness of the top sacrificial layer is reduced.
As an example, the predetermined peeling layer 110 has a predetermined distance d from a cavity structure (e.g., the cavity structure 112) to be formed, as shown in fig. 11. In the present invention, the preset distance D is set according to the cavity structure, and the setting manner is that the preset distance D is greater than 1/8 of the cavity characteristic dimension D of the cavity structure. In another alternative example, the preset distance is set between 2nm and 10 μm, and may be less than 1.8 μm, and may be selected as: 5nm, 10nm, 50nm, 200nm, 1 μm, 5 μm, 8 μm, preferably 5-15nm, which is advantageous for obtaining a uniform material layer surface. In this step, the preset peeling layer 110 for subsequent substrate peeling is formed by ion implantation, and the position of the preset peeling layer 110 is set according to the cavity structure to be formed, so that the material layer above the cavity structure can be protected in the subsequent process, and the material layer above the cavity is prevented from being damaged in the process of grinding, for example. It is ensured that the material layer above the cavity has a probability close to 100% without breakage. The process is simplified, and the cost is saved. In addition, the predetermined release layer may of course also be set with reference to the actually required thickness, for example, when 1/8 that is smaller than the cavity characteristic dimension D of the cavity structure is required subsequently, it may also be realized based on a subsequent thinning process.
In this embodiment, the preset distance D is greater than 1/8 of a cavity characteristic dimension D of the cavity structure, where the cavity characteristic dimension D may be defined as: in the two-dimensional plane above the cavity (i.e., the cavity structure 112), the two-dimensional plane may be the two-dimensional plane where the top opening of the cavity structure is located, because the cavity is a closed structure, for any point a above the cavity, any straight line is made through the point, the straight line has more than two contact points with the edge of the cavity, and two points a', a ″ adjacent to the point a in two directions in which the point a straight line extends are taken as the first contact point and the second contact point, as shown in fig. 15, where fig. 15 shows a finally prepared SOI substrate, in which the thickness of the finally transferred substrate film layer is h in this example. The distance between the two points A 'and A' is the size of a section of cavity, and the smallest size of the section of cavity can be found by changing the direction of the straight line passing through the point A. There is a corresponding minimum cavity size for all points above the cavity. Of all the smallest cavity dimensions, the largest one is selected, defined as the cavity characteristic dimension. For example, as shown in fig. 15, in the cavity structure having a rectangular shape in plan view, the size of the cavity characteristic dimension D is the length of the short side of the rectangle.
As an example, the setting of the ratio of the preset distance to the characteristic dimension of the cavity structure includes: defining the pressure on the upper surface of the cavity structure in the stripping process as p, defining the length of the cavity structure in a pointing plane as infinite length, and defining the worst condition as that two sides of the central position of the transfer substrate film layer above the cavity only use the patterned dielectric layer as a supporting point to obtain the maximum stress Mmax ÷ pL2 and the maximum stress sigma max ÷ qL2/h2 in the transfer substrate film layer, wherein h is the preset distance, L is the characteristic dimension of the cavity structure, and obtaining the ratio of the preset distance to the characteristic dimension of the cavity structure by adopting a test design mode based on the maximum stress which can be borne by the transfer substrate film layer.
Specifically, as shown in fig. 16 and 17, in the smart cut process, the hydrogen bubble peels the peeled layer away from the original substrate. The peel ply is stressed the most due to its limited thickness. In the worst case, the area where the hydrogen bubbles exert pressure on the peeling layer covers the entire cavity at a pressure p. In defining the characteristic dimension of the cavity, the peeling layer is supported only by the oxygen buried layers on the left and right sides, assuming that the peeling layer located at the position of the dimension is subjected to an equal pressure of hydrogen bubbles everywhere. The stress in the release layer is worst at this time. The maximum internal stress is located at the center of the peeling layer as can be seen by simple stress analysis. If the length of the cavity in the z direction (in the direction of the plane) is long, the cavity can be approximately infinitely long when stress analysis is carried out on the cavity, the stripping layer only takes the oxygen buried layers on the left side and the right side as supporting points, and the stress born by the stripping layer is the worst condition at the moment. The maximum stress Mmax ^ pL of the release layer2And (. alpha. -. is proportional to the mean.), and the maximum stress σ max. alpha. -. pL received in the peeled layer2/h2I.e., σ max ℃ ∈ (L/h)2I.e. the ratio of the cavity width L to the release layer thickness h defines the maximum stress to which the release layer is subjected. The upper limit of the maximum stress that the release layer can withstand is a constant, and is determined by the material properties. The ratio of the cavity width L to the peel ply thickness h at which the peel ply is subjected to the upper limit of maximum stress can be found by experimentation.
As an example, the step of performing the ion implantation to form the preset peeling layer 110 includes: performing a first ion implantation on the first substrate to form an initial peeling layer (not shown in the figure) in the first substrate, wherein implanted particles of the first ion implantation include B-containing impurities; and performing second ion implantation at the position of the initial peeling layer to form the preset peeling layer 110, wherein the implanted particles of the second ion implantation comprise at least one of H ions and He ions. Through the mode, in the process of defining the stripping interface, B + and BF2 plasma is implanted into the stripping interface in advance, so that the distribution profile of the implanted particles with clear table can be defined at a lower dosage, the subsequent ion implantation dosage is reduced, the implanted ions implanted for the second time are enriched at the first implanted particles, the stripping interface is accurately defined, the stripping damage is reduced, and the stripping surface roughness is reduced. In an example, an implantation dose of the first ion implantation is less than an implantation dose of the second ion implantation. Optionally, the implantation dose of the first ion implantation is between 1e11～1e13/cm2E.g. can be 1e12/cm2(ii) a Performing a second ion implantation on the basis of the first particle implantation, i.e. then implanting hydrogen ions, at an implant dose of 1e16～1e17/cm2E.g. can be 6e16/cm2Of course, He ions or other ions can be used, so that hydrogen ions are enriched near B + ions, thereby accurately defining a stripping interface, reducing stripping damage and reducing the roughness of a stripping surface.
Next, as shown in S5 of fig. 1 and fig. 10, step S5 is performed to remove the sidewall structures 105 and the corresponding first dielectric layer 101 under the sidewall structures 105 to form first grooves 111. In an example, this step uses an etching process with selective etching materials (etching the first dielectric layer 101 and the second dielectric layer 104 (the sidewall structure 105), and not etching or slowly etching the polysilicon layer (the first sacrificial layer 103 and the second sacrificial layer 107)) to etch the first dielectric layer 101 and the sidewall structure 105 (the second dielectric layer 104), so as to expose the first substrate 100 (e.g., a silicon substrate).
Next, as shown in S6 of fig. 1 and fig. 11-12, step S6 is performed to remove the first sacrificial layer 103 and the second sacrificial layer 107, and the first substrate 100 is etched downward based on the first groove 111 to form a second groove 112, wherein the bottom of the second groove 112 is higher than the predetermined peeling layer 110. In one example, the distance that the bottom of the second groove 112 is higher than the predetermined peeling layer 110 is the predetermined distance d mentioned in the previous examples. In an example, the material of the first sacrificial layer 103 and the material of the second sacrificial layer 107 are both selected to be polysilicon, and the material of the first substrate 100 is selected to be silicon, in this step, the polysilicon layer is etched, the silicon substrate is simultaneously etched, and the second groove 112 is introduced into the silicon substrate.
As an example, the step of forming the second groove 112 further includes: the first dielectric layer 101 is thinned to a preset thickness or the first dielectric layer 101 is removed, a wet etching process or a dry etching process may be adopted, and the preset thickness may be selected according to the actual condition, as shown in fig. 12, so as to control the surface roughness to be less than 0.5nm, may be 0.3nm, and is preferably 0.2. The polishing temperature can be reached by CMP polishing or by hydrogen atmosphere annealing, and the annealing temperature is 800-1300 ℃. In the case that the first dielectric layer 101 is not completely removed, the first dielectric layer 101 is converted into a thinned dielectric layer 113 after the step.
Next, as shown in S7 of fig. 1 and fig. 13, step S7 is performed to provide a second substrate, and the side of the first substrate where the second groove 112 is formed is bonded to the second substrate, and an original bonding structure may be obtained by using an existing bonding process, such as direct bonding, and the second groove 112 forms the cavity structure. The bonding atmosphere can be selected from vacuum, inert gas and reducing gas. The number and the shape of the cavity structures can be obtained by limiting the shape of the side wall structure according to the etching process.
As an example, the second base includes a second substrate 200 and an intermediate dielectric layer 201 formed on the second substrate 200, and the side of the first base having the second groove 112 is bonded to the intermediate dielectric layer 201. Thus, based on this example, an SOI substrate having a nanoscale cavity structure formed in the upper top silicon material layer can be obtained.
As an example, the first substrate 100 includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer 201 comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate 200 includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2O3At least one of the substrate and the InP substrate.
Finally, as shown in S8 in fig. 1 and fig. 14, step S8 is performed to peel off the first base along the predetermined peeling layer 110, transfer a portion of the first base onto the second base, and form a transfer substrate film layer 114 on the second base, so as to obtain an SOI substrate having a cavity structure and composed of the second base and the transfer substrate film layer. Wherein, the initial bonding structure can be annealed at the temperature of 400-700 ℃ for intelligent stripping to obtain the SOI substrate containing the nano-scale cavity. Of course, other common stripping methods can be adopted, and the SOI top layer structure can also be obtained by adopting a back polishing thinning method, according to practical selection.
As an example, peeling 110 the first substrate along the predetermined peeling layer includes the steps of: and carrying out reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment comprises the step of carrying out heating treatment on the semiconductor substrate with the cavity structure. Such as a high temperature heat treatment, for example at 1000 ℃ to 1300 ℃. Of course, other means of reinforcement may be employed.
In a further alternative example, the heating process is performed under a predetermined atmosphere, which includes an oxygen atmosphere, to oxidize the surface of the transfer substrate film layer 114 to form a surface oxide layer (not shown), and the surface oxide layer is removed after the heating process is performed to thin the transfer substrate film layer. In this way, the transfer substrate film layer can be thinned by oxidation during the consolidation of the composite substrate structure, i.e. the semiconductor substrate with a cavity structure. In one example, the surface oxide layer is etched using hydrofluoric acid to thin the transfer substrate film layer.
As an example, obtaining the SOI substrate having the cavity structure further includes: it is right to shift substrate film layer 114 and carry out the attenuate processing, the attenuate processing is including adopting the first attenuate of chemical mechanical polishing technology machinery and adopting oxidation attenuate technology to carry out the second attenuate, obtains the attenuate and handles the back structure. That is, the transfer substrate film layer is thinned by a two-step thinning method, wherein the first thinning step may be rough polishing, for example, CPM, and the time for performing the first thinning may be selected according to practical experience. Then, the second thinning is carried out on the basis, and the oxidation thinning process can be adopted, namely, an oxide layer is formed on the surface of the transfer substrate film layer after the first thinning is oxidized, then the oxide layer is removed, and the thinning is further realized, so that the thickness of the transfer substrate film layer remained after the thinning is accurately defined.
In one example, it is preferable that the processes of the first thinning and the second thinning in this example are performed after the heat curing treatment in the oxygen atmosphere and the removal of the surface oxide layer in the above example are performed, so as to obtain the structure after the thinning treatment. After the oxidation attenuate of above-mentioned example is accomplished, get rid of promptly after the surface oxidation layer, the thickness that shifts the substrate rete (like top silicon) reduces, the pressure that shifts the substrate rete and can bear above the cavity structure reduces, if adopt the CMP technology right this moment shift further attenuate, the polishing of substrate rete, cause the top silicon damaged easily, consequently, can adopt in this example earlier to carry out thick attenuate with CMP and continue the secondary oxidation attenuate again with oxidation attenuate technology, do benefit to accurate definition thickness.
As an example, the method further includes, after performing the thinning process, the steps of: and repairing the surface after the thinning treatment to ensure that the surface after the thinning treatment reaches atomic level flatness, and obtaining a cavity upper film layer (not shown in the figure). In one example, the repair process includes annealing the semiconductor substrate having the cavity structure in a hydrogen atmosphere at a temperature between 800 ℃ and 1300 ℃, which may be 1000 ℃, for example. The upper film layer of the cavity with excellent performance and almost no damage can be obtained.
In addition, the present invention also provides another method for manufacturing a substrate having a cavity structure, wherein an SOI substrate is selected to replace the first base in the above example, and other process steps can be referred to the description of the above example, in this example:
as shown in fig. 18-30, a schematic structural view of steps of replacing the first base 100 with the SOI substrate 300 is shown. The SOI substrate 300 includes a bottom layer of silicon 301, a buried oxide layer 302, and a top layer of silicon 303. In the specific process, in fig. 24, after obtaining the structures in which the upper surfaces of the thinned first sacrificial unit 108a, the thinned sidewall structure 109, and the second sacrificial unit 107a are flush, the sidewall structure 105 and the corresponding first dielectric layer 101 below the sidewall structure 105 are directly removed without performing ion implantation to form a first groove 111, as shown in fig. 25. Further, after the bonding shown in fig. 28, a peeling process is not required, and then the process of removing the bottom layer silicon 301 shown in fig. 29 is performed, in an example, a selective CMP process is used for polishing and thinning, the silicon substrate layer of the original silicon oxide substrate is removed, and after the silicon oxide layer is polished, the CMP process is stopped. Further, the step shown in fig. 30 is performed to remove the buried oxide layer 302. In an example, the substrate is subjected to high-temperature reinforcement at 1000-1300 ℃, and processes such as CMP polishing, oxidation thinning, H2 annealing and the like are performed at the same time, so as to obtain a high-quality SOI substrate with embedded nano-scale cavities, and specific processes can be referred to in the description of the above example.
This embodiment also provides an SOI substrate structure having a cavity structure, wherein the SOI substrate having a cavity structure is preferably prepared by the method for preparing an SOI substrate having a cavity structure provided in this embodiment of the present invention, and may be prepared by other methods. For the features of each structural layer in the SOI substrate having a cavity structure in this embodiment, reference may be made to the description of the method for manufacturing the SOI substrate having a cavity structure in this embodiment, and details are not repeated here.
Wherein the SOI substrate comprises:
a first base including a first substrate 100, the first substrate 100 having a groove structure formed therein, in one example, the groove structure having a size of a nanometer scale;
and the second base comprises a second substrate 200 and an intermediate dielectric layer 201 formed on the second substrate 200, one side of the first base, on which the groove structure is formed, is bonded with one side of the second base, on which the intermediate dielectric layer 201 is formed, the groove structure exposes the intermediate dielectric layer 201, and the groove structure forms a cavity structure of the SOI substrate with the cavity structure.
As an example, the first base includes a cavity upper film layer (not shown) thinned based on a transfer substrate film layer 114 formed based on the first substrate, wherein the groove structure is formed in the cavity upper film layer. Further, the transfer substrate film layer 114 has a first surface proximate to the cavity structure and a second surface opposite the first surface, the second surface being spaced from the cavity structure by a distance greater than 1/8 of the cavity characteristic dimension of the cavity structure.
As an example, the first substrate 100 includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer 201 comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate 200 includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2O3At least one of the substrate and the InP substrate.
In summary, according to the SOI substrate with a cavity structure and the method for manufacturing the SOI substrate with a cavity structure of the present invention, the SOI substrate with the embedded nano-scale cavity is manufactured by using the side wall mask, and the groove structure is formed by etching using the protruding side wall structure as the mask, so as to obtain the cavity structure. In addition, when the preset stripping layer is formed, the preset distance between the preset stripping layer and the cavity structure to be formed is larger than 1/8 of the characteristic dimension of the cavity structure, so that the material layer above the cavity structure is further prevented from being damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and the performance of a device are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (17)

1. A method for producing an SOI substrate having a cavity structure, characterized by comprising the steps of:
providing a first base, wherein the first base comprises a first substrate and a first dielectric layer formed on the first substrate;
forming a first sacrificial layer on the first dielectric layer, wherein the first sacrificial layer comprises a plurality of first sacrificial units which are arranged at intervals and a first opening which exposes the first dielectric layer, and the first opening defines the position of a cavity structure to be formed;
forming side wall structures on the side walls of the first sacrificial units, and forming second sacrificial layers on the surfaces of the first dielectric layers exposed among the side wall structures, wherein the second sacrificial layers comprise a plurality of second sacrificial units which are arranged at intervals, the first openings are filled with the second sacrificial units, and the width of the side wall structures defines the width of the cavity structures;
performing ion implantation on the first substrate to form a preset stripping layer in the first substrate;
removing the side wall structure and the first dielectric layer corresponding to the lower part of the side wall structure to form a first groove;
removing the first sacrificial layer and the second sacrificial layer, and etching the first substrate downwards based on the first groove to form a second groove, wherein the bottom of the second groove is higher than the preset stripping layer;
providing a second substrate, and bonding one side of the first substrate, on which the second groove is formed, with the second substrate to obtain an initial bonding structure, wherein the second groove forms the cavity structure;
and peeling the first base along the preset peeling layer, transferring a part of the first base onto the second base, and forming a transfer substrate film layer on the second base to obtain the SOI substrate with the cavity structure, wherein the SOI substrate is composed of the second base and the transfer substrate film layer.
2. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, wherein the step of forming the sidewall structure includes: forming a continuous second dielectric layer on the surface of the first sacrificial unit and the exposed surface of the first dielectric layer; and removing the first sacrificial unit and the second dielectric layer above the first dielectric layer, and reserving the second dielectric layer formed on the side wall of the first sacrificial unit to obtain the side wall structure.
3. The method for manufacturing an SOI substrate having a cavity structure according to claim 2, wherein a material of the second dielectric layer is different from a material of the first dielectric layer.
4. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, wherein a thickness of the first dielectric layer is more than 2 nm; the size of the side wall structure is in a nanometer level, and the width of the side wall structure is between 5nm and 15 nm.
5. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, wherein the step of forming the second sacrificial layer includes: forming a second sacrificial material layer on the top of the first sacrificial unit, the surface of the side wall structure and the surface of the first medium layer exposed among the side wall structures; and thinning the second sacrificial material layer to expose the side wall structure to obtain the second sacrificial layer, wherein after thinning, the heights of the first sacrificial layer, the side wall structure and the second sacrificial layer are the same, and the heights are greater than the depth of the cavity structure.
6. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, further comprising, after forming the second recess, the steps of: and thinning the first dielectric layer to a preset thickness or removing the first dielectric layer to control the surface roughness to be less than 0.5 nm.
7. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, wherein the step of performing the ion implantation to form the predetermined peeling layer includes: performing a first ion implantation on the first substrate to form an initial lift-off layer in the first substrate; and performing second ion implantation at the position of the initial peeling layer to form the preset peeling layer, wherein the implanted particles of the first ion implantation comprise B-containing impurities, and the implanted particles of the second ion implantation comprise at least one of H ions and He ions.
8. The method of claim 1, wherein a predetermined distance is provided between the predetermined exfoliation layer and the cavity structure to be formed, and the predetermined distance is set according to the cavity structure, wherein the setting comprises 1/8 that the predetermined distance is greater than a characteristic dimension of the cavity structure.
9. The method for manufacturing an SOI substrate having a cavity structure according to claim 8, wherein the cavity feature size is defined in a manner including: defining a two-dimensional plane above the cavity structure parallel to the surface of the cavity structure; in the two-dimensional plane, a plurality of selected points are arranged above the cavity structure; for each said selected point, there are a number of straight lines passing through said selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are respectively adjacent to the selected point in two directions of the straight line extending through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum size of the cavity based on a number of the straight lines passing through each of the selected points; and selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the characteristic size of the cavity.
10. The method for producing an SOI substrate having a cavity structure according to claim 1, further comprising, after peeling the first base along the predetermined peeling layer, the steps of: and carrying out reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment comprises the step of carrying out heating treatment on the semiconductor substrate with the cavity structure.
11. The method for manufacturing an SOI substrate having a cavity structure according to claim 10, wherein the heat treatment is performed under a predetermined atmosphere including an oxygen atmosphere to form a surface oxide layer on the surface of the transfer substrate film layer, and the surface oxide layer is removed to thin the transfer substrate film layer after the heat treatment is completed.
12. The method for manufacturing an SOI substrate having a cavity structure according to claim 1, further comprising, after obtaining the semiconductor substrate having a cavity structure, the steps of: it is right to shift the rete structure and carry out the attenuate processing, the attenuate processing is including adopting chemical mechanical polishing to carry out first attenuate and adopt the oxidation attenuate to carry out the second attenuate.
13. The method for manufacturing an SOI substrate having a cavity structure according to claim 12, further comprising, after performing the thinning process, the steps of: and repairing the thinned surface to ensure that the thinned surface reaches atomic level flatness, wherein the repairing process comprises annealing the thinned semiconductor substrate with the cavity structure in a hydrogen atmosphere at the annealing temperature of between 800 and 1300 ℃.
14. The method for manufacturing an SOI substrate having a cavity structure according to any one of claims 1 to 13, wherein the second base includes a second substrate and an intermediate dielectric layer formed on the second substrate, and the side of the first base having the second groove is bonded to the intermediate dielectric layer.
15. The method for manufacturing an SOI substrate having a cavity structure according to claim 14, wherein the first substrate includes a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate comprises a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2O3At least one of the substrate and the InP substrate.
16. An SOI substrate having a cavity structure, characterized in that the SOI substrate comprises:
the first substrate comprises a first substrate, wherein a groove structure with the size of a nanometer level is formed in the first substrate;
and the second base comprises a second substrate and an intermediate medium layer formed on the second substrate, one side of the first base, on which the groove structure is formed, is bonded with one side of the second base, on which the intermediate medium layer is formed, the groove structure exposes the intermediate medium layer, and the groove structure forms a cavity structure of the SOI substrate with the cavity structure.
17. The SOI substrate having a cavity structure according to claim 16, wherein the first substrate comprises a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, Ga2O3At least one of a substrate and an InP substrate; the middle dielectric layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer and an aluminum oxide layer; the second substrate comprises a Si substrate, a Ge substrate, a GaN substrate, a SiC substrate, a GaAs substrate, an AlGaN substrate, and Ga2At least one of an O3 substrate and an InP substrate.
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