CN111952239B - Semiconductor substrate with cavity structure and preparation method thereof - Google Patents

Semiconductor substrate with cavity structure and preparation method thereof Download PDF

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Publication number
CN111952239B
CN111952239B CN202010849584.5A CN202010849584A CN111952239B CN 111952239 B CN111952239 B CN 111952239B CN 202010849584 A CN202010849584 A CN 202010849584A CN 111952239 B CN111952239 B CN 111952239B
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cavity structure
semiconductor substrate
layer
cavity
substrate
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CN111952239A (en
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俞文杰
刘强
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

The invention provides a semiconductor substrate with a cavity structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first substrate and a second substrate, performing ion implantation in the first substrate to form a preset stripping layer, wherein a preset distance is reserved between the preset stripping layer and a cavity structure to be formed, the preset distance is larger than 1/8 of the cavity characteristic dimension of the cavity structure, bonding the first substrate and the second substrate, and stripping along the preset stripping layer to obtain the semiconductor substrate with the cavity structure. The invention prefabricates the preset stripping layer according to the cavity structure to be formed when ion implantation is carried out to form the stripping interface, and the preset distance between the preset stripping layer and the cavity structure to be formed is larger than 1/8 of the cavity characteristic dimension of the cavity structure, thereby ensuring that a material layer above the cavity structure is not damaged in the process of preparing the semiconductor substrate with the cavity structure, and improving the yield and performance of devices.

Description

Semiconductor substrate with cavity structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor device structure design and manufacture, and particularly relates to a semiconductor substrate with a cavity structure and a preparation method thereof.
Background
A cavity is prepared in the semiconductor substrate, the cavity can play roles in insulation and the like, a semiconductor functional device can be prepared on the cavity, and the characteristics of good subthreshold and the like of a retainer piece can be realized. In order to improve the performance and cost performance of integrated circuit chips, shrinking the device feature size and thus improving the integration is a major approach. However, as the device size is reduced, power consumption and leakage current become the most important issues. Silicon-On-Insulator (SOI) structures have become the preferred structure for deep sub-micron MOS devices because they suppress the short channel effect well and improve the device scaling capability. With the continued development of SOI technology, researchers have developed a new transistor structure SON (Silicon onnothing) transistor. SON forms local silicon on insulator under the channel through a 'cavity' structure, and SON technology is a method for reducing effects such as short trenches of SOI devices. Compared with an SO1 device, the SON device removes the buried oxide layer below the channel, reduces the interface state at the bottom of the top silicon, reduces the influence of the body charge in the buried oxide layer on the conductive characteristic of the channel, reduces the parasitic capacitance between the channel and the substrate, and simultaneously ensures that the device has good total dose radiation resistance. Compared with an SOI device, the SON device has a certain enhancement on the suppression capability of short channel effect due to the removal of back charge and capacitance influence.
However, in the existing process of manufacturing a semiconductor substrate with a cavity, an intelligent lift-off (Smart-cut) process is often required along a lift-off layer, for example, when a SON substrate is manufactured, for example, the lift-off layer is formed by injecting hydrogen ions, in the process of intelligent lift-off, hydrogen bubbles are generated at a lift-off interface, and the hydrogen bubbles exert a larger pressure on the lift-off layer, so that the finally obtained lift-off layer is damaged, and when part of the top silicon in the SON substrate is damaged, the substrate cannot meet the application requirements of an integrated circuit, a micro-electromechanical system and the like. In the prior art, if the cavity size is larger, the material layer above the cavity (such as the top silicon) is easily damaged, as shown in fig. 26, which shows the damage condition of the top silicon above the cavity for the cavity structures with different sizes in the prior art. As the cavity size increases, the probability of breakage of the top silicon layer above the cavity increases rapidly, and cracks appear at the edges of the cavity where the part is not completely broken. Seriously affecting the yield and performance of the device.
Therefore, it is necessary to provide a semiconductor substrate with a cavity structure and a method for manufacturing the same, so as to solve the above technical problems in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor substrate with a cavity structure and a method for manufacturing the same, which are used for solving the problem that a material layer above a cavity is easy to be damaged when a substrate with a cavity is manufactured in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor substrate having a cavity structure, the method comprising the steps of:
Providing a first substrate and a second substrate;
performing ion implantation on the first substrate to form a preset stripping layer in the first substrate, wherein a preset distance is reserved between the preset stripping layer and a cavity structure to be formed, the preset distance is set according to the cavity structure, and the setting mode comprises that the preset distance is greater than 1/8 of the cavity characteristic size of the cavity structure;
The defining mode of the characteristic dimension of the cavity comprises the following steps: defining a two-dimensional plane parallel to the surface of the cavity structure above the cavity structure; in the two-dimensional plane, a plurality of selection points are arranged above the cavity structure; for each of the selected points, there are several straight lines passing through the selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are adjacent to the selected point in the two directions of extending the straight line passing through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum of said cavity dimensions based on a number of said straight lines passing through each of said selected points; selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the cavity characteristic size;
bonding one side of the first substrate subjected to the ion implantation and the second substrate to obtain an initial bonding structure, wherein the initial bonding structure comprises a graphical medium layer with the cavity structure, and a space is reserved between the graphical medium layer and the preset stripping layer; and
And stripping the first substrate along the preset stripping layer, and transferring a part of the first substrate onto the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer so as to obtain the semiconductor substrate with the cavity structure.
Optionally, the first substrate includes a first semiconductor substrate, the preset release layer is formed in the first semiconductor substrate, the second substrate includes a second semiconductor substrate and the patterned dielectric layer formed on the second semiconductor substrate, and a side of the first substrate where the ion implantation is performed is bonded with the patterned dielectric layer of the second substrate.
Optionally, the ion implantation further comprises the steps of: and forming a sacrificial dielectric layer on the surface of the first semiconductor substrate, performing ion implantation from the side on which the sacrificial dielectric layer is formed, and removing the sacrificial dielectric layer after the ion implantation is completed.
Optionally, an isolation layer is further formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.
Optionally, the first substrate includes a first semiconductor substrate and the patterned dielectric layer formed on the first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, and the second substrate includes a second semiconductor substrate, wherein the patterned dielectric layer of the first substrate is bonded with the second substrate.
Optionally, the step of forming the first substrate includes: providing the first semiconductor substrate; forming a sacrificial dielectric layer on the first semiconductor substrate; performing the ion implantation on the first semiconductor substrate from the side where the sacrificial dielectric layer is formed; and patterning the sacrificial dielectric layer to obtain the patterned dielectric layer with the cavity structure.
Optionally, the second substrate further includes an isolation layer formed on the second semiconductor substrate, the isolation layer is bonded to the patterned dielectric layer of the first substrate, and the cavity structure in the patterned dielectric layer exposes the isolation layer.
Optionally, the step of performing the ion implantation to form the preset peeling layer includes: performing a first ion implantation on the first substrate to form an initial release layer in the first substrate; and performing second ion implantation at the position of the initial stripping layer to form the preset stripping layer, wherein the implantation particles of the first ion implantation comprise B-containing impurities, and the implantation particles of the second ion implantation comprise at least one of H ions and He ions.
Optionally, the implantation dose of the first ion implantation is smaller than the implantation dose of the second ion implantation; the implantation dosage of the first ion implantation is between 1e11 and 1e13/cm 2, and the implantation dosage of the second ion implantation is between 1e16 and 1e17/cm 2.
Optionally, the step of peeling the first substrate along the preset peeling layer comprises the steps of: and carrying out reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment comprises heating treatment on the semiconductor substrate with the cavity structure.
Optionally, the heating treatment is performed under a preset atmosphere, the preset atmosphere includes an oxygen atmosphere, so as to form a surface oxide layer on the surface of the transfer substrate film layer, and the surface oxide layer is removed after the heating treatment is completed, so as to thin the transfer substrate film layer.
Optionally, the cavity structure also extends into the material layer below the patterned dielectric layer.
Optionally, the preset distance between the preset release layer and the cavity structure is between 2nm and 10 μm.
Optionally, the setting manner of the ratio of the preset distance to the characteristic dimension of the cavity structure includes: defining the pressure on the upper surface of the cavity structure as p in the stripping process, defining the length of the cavity structure in the directional plane as infinitely long, defining the worst condition as that the two sides of the central position of the transfer substrate film layer above the cavity only use the patterned dielectric layer as supporting points to obtain the maximum stress Mmax-pL 2 and the maximum stress sigma max-qL 2/h2 in the transfer substrate film layer, wherein h is the preset distance, L is the characteristic dimension of the cavity structure, and obtaining the ratio of the preset distance to the characteristic dimension of the cavity structure by adopting a test design mode based on the maximum stress which can be born by the transfer substrate film layer.
Optionally, the step of obtaining the semiconductor substrate with the cavity structure further comprises the following steps: and carrying out thinning treatment on the transfer film layer structure, wherein the thinning treatment comprises first thinning by adopting a chemical mechanical polishing process and second thinning by adopting an oxidation thinning process.
Optionally, the thinning process further includes the steps of: and carrying out repair treatment on the thinned surface so as to enable the thinned surface to be atomically flat, wherein the repair treatment comprises annealing the semiconductor substrate with the cavity structure in a hydrogen atmosphere, and the annealing temperature is between 800 and 1300 ℃.
The invention also provides a semiconductor substrate structure with a cavity structure, wherein the semiconductor substrate with the cavity structure is preferably prepared by the preparation method of the semiconductor substrate with the cavity structure, and of course, the semiconductor substrate with the cavity structure can also be prepared by other methods. The semiconductor substrate structure comprises:
the first substrate comprises a cavity upper film layer, and the cavity upper film layer is obtained by thinning the transfer substrate film layer;
A second substrate bonded to the first substrate, the second substrate comprising a second semiconductor substrate;
The patterned dielectric layer is formed between the second semiconductor substrate and the upper film layer of the cavity, the transfer substrate film layer is provided with a first surface close to the cavity structure and a second surface opposite to the first surface, and the distance between the second surface and the cavity structure is greater than 1/8 of the cavity characteristic size of the cavity structure.
Optionally, an isolation layer is further formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.
Optionally, the cavity structure extends through the patterned dielectric layer and the cavity structure also extends into at least one of the second semiconductor substrate and the transfer substrate film.
As described above, in the semiconductor substrate with a cavity structure and the method for manufacturing the same, when ion implantation is performed to form a peeling interface, a preset peeling layer is prefabricated according to the cavity structure to be formed, and the preset distance between the preset peeling layer and the cavity structure to be formed is greater than 1/8 of the cavity characteristic dimension of the cavity structure, so that the material layer above the cavity structure can be ensured not to be damaged in the process of manufacturing the semiconductor substrate with the cavity structure, and the yield and performance of a device are improved.
Drawings
Fig. 1 shows a method for manufacturing a semiconductor substrate having a cavity structure according to an embodiment of the present invention.
Fig. 2 to 21 are schematic structural views showing steps in the preparation process of a semiconductor substrate having a cavity structure according to an embodiment of the present invention.
Figure 22 illustrates the cavity feature dimensions of a cavity structure having a rectangular shape during the formation of a predetermined release layer.
Fig. 23 is a perspective view of a SON structure prepared according to the scheme of the present invention.
Fig. 24 (a) and 24 (b) are schematic views showing at least one end of the support structure contacting the side wall of the cavity structure in the embodiment of the present invention.
Fig. 25 (a) and 25 (b) are schematic views showing the support structure being located in the cavity structure in the embodiment of the present invention.
Fig. 26 shows the prior art situation where the top layer silicon over the different sized cavities is damaged.
FIG. 27 shows the occurrence of various levels of breakage of the top layer silicon over the cavity when the lift-off thickness of the top layer silicon (top layer silicon thickness 1 μm) is 1/8 or less of the feature size of the cavity.
Figure 28 shows the damage of the top silicon layer on different sized cavities when the pre-set release layer is formed using the inventive approach.
Figure 29 shows a SON substrate with a large-area, high-density closed cavity structure prepared using the inventive approach.
FIG. 30 is a schematic view showing the stress of a material layer above a cavity structure during smart lift-off.
Figure 31 shows the maximum compressive and tensile stresses experienced by the upper and lower edges at the corresponding centerline position of the release layer above the cavity, with breakage at the lower edge.
Description of element reference numerals
100. A first substrate
101. First semiconductor substrate
101A preset release layer
102. Sacrificial dielectric layer
103. Patterning dielectric layer
103A cavity structure
104. Transferring substrate film
105. Surface oxide layer
106. Structure after thinning treatment
107. Upper film layer of cavity
200. A second substrate
201. Second semiconductor substrate
202. Isolation layer
203. Patterning dielectric layer
203A cavity structure
S1 to S4 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a method for preparing a semiconductor substrate having a cavity structure, comprising the steps of:
S1: providing a first substrate and a second substrate;
S2: performing ion implantation on the first substrate to form a preset stripping layer in the first substrate, wherein a preset distance is reserved between the preset stripping layer and a cavity structure to be formed, the preset distance is set according to the cavity structure, and the setting mode comprises that the preset distance is greater than 1/8 of the cavity characteristic dimension of the cavity structure;
S3: bonding one side of the first substrate subjected to the ion implantation and the second substrate to obtain an initial bonding structure, wherein the initial bonding structure comprises a graphical medium layer with the cavity structure, and a space is reserved between the graphical medium layer and the preset stripping layer; and
S4: and stripping the first substrate along the preset stripping layer, and transferring a part of the first substrate onto the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer so as to obtain the semiconductor substrate with the cavity structure.
The method for manufacturing a semiconductor substrate having a cavity structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein, the above-mentioned sequence does not strictly represent the manufacturing sequence of the method for manufacturing a semiconductor substrate having a cavity structure protected by the present invention, and a person skilled in the art may perform a change between the sequence of steps according to an actual process, for example, the second substrate may be provided after the step of performing ion implantation on the first substrate to form a predetermined release layer. In which fig. 1 shows only the preparation steps of a preparation method of a semiconductor substrate having a cavity structure in one example of the present invention.
Example 1:
The embodiment 1 provides a specific method for manufacturing a semiconductor substrate with a cavity structure. First, as shown in S1 in fig. 1 and fig. 2 and 5-7, step S1 is performed to provide a first substrate 100 and a second substrate 200. The first substrate 100 and the second substrate 200 are used for preparing the semiconductor substrate with the cavity structure according to the present invention, and both may be provided according to actual process methods. The first substrate 100 may be a substrate formed of a single material layer or a substrate formed of a laminated material layer structure. Similarly, the first substrate 200 may be a substrate made of a single material layer or a substrate made of a laminated material layer structure.
As an example, as shown in fig. 2, the first base 100 includes a first semiconductor substrate 101, and a preset peeling layer formed by subsequent ion implantation is formed in the first semiconductor substrate 101. The first semiconductor substrate 101 may be Si, ge, gaN, siC, gaAs, alGaN, ga 2O3, inP material layers, or a combination of two or more of the foregoing material layers. Of course, other crystalline semiconductors are also possible, without being limited thereto.
In a further alternative example, the first substrate 100 further includes a sacrificial dielectric layer 102 formed on the first semiconductor substrate 101, where the sacrificial dielectric layer 102 may be a SiO 2, a silicon nitride, a silicon oxynitride, an aluminum oxide material layer, or a combination of two or more of the foregoing material layers. Of course, other insulating sacrificial dielectric layers are also possible and are not limited thereto. The sacrificial dielectric layer 102 may be formed on the first semiconductor substrate 101 by, but not limited to, thermal oxidation. The sacrificial dielectric layer 102 may protect the surface of the first semiconductor substrate 101 in the subsequent ion implantation process or the like, and may also be used for preparing a functional layer of a device, and is selected according to the actual preparation requirement of the device.
As an example, as shown in fig. 5-7, the second base 200 includes a second semiconductor substrate 201 and the patterned dielectric layer 203 formed on the second semiconductor substrate 201, as shown in fig. 6. The second semiconductor substrate 201 may be Si, ge, gaN, siC, gaAs, alGaN, ga 2O3, inP material layers, or a combination of two or more of the above material layers. Of course, other crystalline semiconductors are also possible, without being limited thereto. In addition, a cavity structure 203a is formed in the patterned dielectric layer 203 for use as the cavity structure in a subsequently obtained semiconductor substrate having the cavity structure. The patterned dielectric layer 203 may be a SiO 2, a silicon nitride, a silicon oxynitride, an aluminum oxide material layer, or a combination of two or more of the above material layers. Of course, other insulating sacrificial dielectric layers are also possible and are not limited thereto. In addition, the number and arrangement of the cavity structures 203a may be set according to practical requirements, for example, in a periodic array arrangement.
In a further alternative example, as shown in fig. 5, an isolation layer 202 is further formed between the second semiconductor substrate 201 and the patterned dielectric layer 203, and the cavity structure 203a exposes the isolation layer 202. The isolation layer 202 may be used to isolate the cavity structure 203a from the second semiconductor substrate 201 to facilitate tuning of device performance based on the structural layer. The isolation layer 202 may be a SiO 2, silicon nitride, silicon oxynitride, aluminum oxide material layer, or a combination of two or more of the above material layers. Of course, other insulating sacrificial dielectric layers are also possible and are not limited thereto. In an example, the material of the isolation layer 202 is different from the material of the patterned dielectric layer 203, so as to facilitate the preparation of the patterned dielectric layer 203 and improve the device performance based on the isolation layer 202. The isolation layer and the patterned dielectric layer supporting layer can be made of the same material or different materials, and when the isolation layer and the patterned dielectric layer supporting layer are made of different materials, a certain selective etching ratio is arranged between the two structural layers, so that the device structure can be defined in the subsequent device preparation process.
As an example, as shown in fig. 7, the cavity structure 203a in the patterned dielectric layer 203 may also extend into the material layer under the patterned dielectric layer 203, and the extension of the cavity structure 203a may be achieved by controlling the etching conditions when the cavity structure 203a is formed. For example, the cavity structure 203a may also extend into the second semiconductor substrate 201 to facilitate adjusting the size of the cavity structure according to the device performance requirement, and of course, when the isolation layer 202 is further provided, the cavity structure 203 may also extend into the second semiconductor substrate 201 through the isolation layer 202. In an example, the second semiconductor substrate layer 201 of the second substrate 200 is used as a bottom silicon layer of a SON structure formed later, the patterned dielectric layer 203 is used as an intermediate insulating layer, and the first semiconductor substrate layer 101 in the first substrate 100 in this embodiment is used as a material layer for forming the top silicon layer. In this example, the cavity structure 203a extends into the underlying silicon of the SON.
Next, as shown in S2 in fig. 1 and fig. 3 to 4 and 22, step S2 is performed to perform ion implantation on the first substrate 100 to form a preset release layer 101a in the first substrate 100, where a preset distance is provided between the preset release layer 101a and a cavity structure (such as the cavity structure 203 a) to be formed, as shown in d in fig. 8. The preset distance D is set according to the cavity structure 203a, where the preset distance D is greater than 1/8 of the cavity feature size D of the cavity structure 203 a. In another alternative example, the preset distance is set between 2nm-10 μm, which may be less than 1.8 μm, and may be selected as: 5nm, 10nm, 50nm, 1 μm,5 μm and 8 μm, which is favorable for obtaining the surface of the uniform material layer. In this step, the preset release layer 101a for subsequent substrate release is formed by performing ion implantation, and the position of the preset release layer 101a is set according to the cavity structure 203a to be formed, which is beneficial to protecting the material layer above the cavity structure 203a in the subsequent process, so as to avoid breakage of the material layer above the cavity, for example, in the grinding process. The material layer above the cavity is guaranteed to have a probability of nearly 100% without breakage. The process is simplified and the cost is saved. In addition, the preset release layer 101a may of course also be set with reference to the actual required thickness, for example, when the required subsequent thickness is smaller than 1/8 of the cavity feature size D of the cavity structure 203a, and may also be implemented based on the subsequent thinning process.
In this embodiment, the preset distance D is greater than 1/8 of the cavity feature size D of the cavity structure 203a, where the definition of the cavity feature size D may be: in the two-dimensional plane above the cavity (i.e., the cavity structure 203), the two-dimensional plane may be a two-dimensional plane where the top opening of the cavity structure 203a is located, because the cavity is a closed structure, for any point a above the cavity, any line is made through the point, the line has more than two contact points with the edge of the cavity, two points a ', a″ adjacent to the point a in two directions in which the line extends are taken, namely, the first contact point and the second contact point, as shown in fig. 22, the distance between the two points a', a″ is one section of the cavity size, the direction of the line passing through the point a is changed, and the minimum section of the cavity size can be found. For all points above the cavity, there is a corresponding minimum cavity size. Of all the smallest cavity dimensions, the largest one is selected and defined as the cavity feature size. For example, as shown in fig. 22, in the cavity structure having a rectangular shape in plan view, the cavity feature D is sized to be the short side length of the rectangle.
As an example, the step of forming the preset peeling layer 101a by performing the ion implantation includes: performing a first ion implantation on the first substrate 100 to form an initial release layer (not shown in the drawing) in the first substrate 100, wherein implantation particles of the first ion implantation include B-containing impurities; and performing second ion implantation at the position of the initial release layer to form the preset release layer 101a, wherein the implantation particles of the second ion implantation comprise at least one of H ions and He ions. By the method, in the process of defining the stripping interface, ions such as B+, BF2 and the like are injected into the stripping interface in advance, so that a clear distribution profile of the injected particles can be defined at a lower dose, the subsequent ion injection dose is reduced, the injected ions of the second ion injection are enriched at the first injected particles, the stripping interface is accurately defined, stripping damage is reduced, and the surface roughness of stripping is reduced. In one example, the implant dose of the first ion implant is less than the implant dose of the second ion implant. Optionally, the implantation dose of the first ion implantation is between 1e 11～1e13/cm2, such as 1e 12/cm2; on the basis of the first particle implantation, the second ion implantation is performed, namely hydrogen ions are then implanted, the implantation dosage is 1e 16～1e17/cm2, for example, the implantation dosage can be 6e 16/cm2, and of course, he ions or other ions can also be used, so that the hydrogen ions are enriched near the B+ ions, the stripping interface is accurately defined, the stripping damage is reduced, and the stripping surface roughness is reduced.
As an example, as shown in fig. 4, in this example, the ion implantation further includes the steps of: a sacrificial dielectric layer 102 is formed on the surface of the first semiconductor substrate 101, the ion implantation is performed from the side where the sacrificial dielectric layer 102 is formed, as shown with reference to fig. 2 to 3, and the sacrificial dielectric layer 102 is removed after the ion implantation is completed, that is, a subsequent bonding is performed using the first semiconductor substrate 101 after the removal of the sacrificial dielectric layer 102.
As an example, the setting manner of the ratio of the preset distance to the feature size of the cavity structure includes: defining the pressure on the upper surface of the cavity structure as p in the stripping process, defining the length of the cavity structure in the directional plane as infinitely long, defining the worst condition as that the two sides of the central position of the transfer substrate film layer above the cavity only use the patterned dielectric layer as supporting points to obtain the maximum stress Mmax-pL 2 and the maximum stress sigma max-qL 2/h2 in the transfer substrate film layer, wherein h is the preset distance, L is the characteristic dimension of the cavity structure, and obtaining the ratio of the preset distance to the characteristic dimension of the cavity structure by adopting a test design mode based on the maximum stress which can be born by the transfer substrate film layer.
Specifically, referring to fig. 30 and 31, hydrogen bubbles strip the release layer from the original substrate during the smart-cut process. The release layer is subjected to the greatest stress due to its limited thickness. In the worst case, the area of the hydrogen bubbles exerting pressure on the release layer covers the entire cavity with a pressure p. In defining the feature size of the cavity, it is assumed that an equal pressure of hydrogen bubbles is applied everywhere over the lift-off layer at the size position, and the lift-off layer is supported only by the buried oxide layers on the left and right sides. The stress condition of the peeling layer is worst at this time. The maximum internal stress is located at the center of the release layer as is known by simple stress analysis. Assuming that the length of the cavity in the z direction (pointing in the plane) is long, the stress analysis can be performed approximately infinitely, and the peeling layer only uses the oxygen-buried layers on the left and right sides as supporting points, so that the stress born by the peeling layer is worst. The maximum stress Mmax oc pL 2, (. Oc stands for proportional) of the release layer, the maximum stress σmax oc pL 2/h2, i.e. σmax oc (L/h) 2, experienced in the release layer, i.e. the ratio of the cavity width L to the release layer thickness h defines the maximum stress experienced by the release layer. The upper limit of the maximum stress that the release layer can withstand is considered to be a constant, determined by the nature of the material. The ratio of the cavity width L to the release layer thickness h at the upper limit of the maximum stress that the release layer is subjected to can be found by experiment.
Next, as shown in S3 in fig. 1 and fig. 8-9, step S3 is performed to bond the side of the first substrate 100 subjected to the ion implantation and the second substrate 200, so as to obtain an initial bonding structure, where the initial bonding structure includes a patterned dielectric layer 203 having the cavity structure 203a, and a space is provided between the patterned dielectric layer 203 and the preset release layer 101 a. The bonding mode can be selected according to actual practice, such as direct bonding. The number and arrangement of the cavity structures 203a may be selected according to practical requirements.
In this embodiment, a side of the first substrate 100, on which the ion implantation is performed, is bonded to the patterned dielectric layer 203 of the second substrate 200, where a distance between the preset peeling layer 101a and the patterned dielectric layer 203 refers to a distance between a side of the patterned dielectric layer 203, on which the patterned dielectric layer 203 is close to the preset peeling layer 101a, and the preset peeling layer 101a, in a plane where the patterned dielectric layer 203 is arranged with the preset peeling layer 101a, where one side is close to the preset peeling layer 101a, and the other side is far from the preset peeling layer 101a, and the distance refers to a distance between the side of the patterned dielectric layer 203, on which the patterned dielectric layer is close to the preset peeling layer 101 a. This distance is also the distance between the cavity structure 203 and the predetermined release layer 101a when the cavity structure 203a penetrates the patterned dielectric layer 203. In this embodiment, the pitch described herein is equal to the preset distance d set in the previous step when ion implantation is performed according to the cavity structure 203 a.
Wherein. As shown in fig. 8, in the bonding process, the surface of the first semiconductor substrate 101 after the sacrificial dielectric layer 102 is removed according to the scheme in fig. 4 is bonded with the patterned dielectric layer 203 of the second substrate 200, so as to obtain the closed cavity structure 203a, and thus, the initial bonding structure of the semiconductor substrate with the cavity structure is obtained. In addition, as shown in fig. 9, an initial bonding structure after bonding with the first base 100 when the cavity structure 203a extends into the second semiconductor substrate 201 is further shown.
As an example, the cavity structure 203a further has a support structure 203b therein, where a top surface of the support structure 203b is flush with an upper surface of the patterned dielectric layer 203, and the support structure 203b is located in the cavity structure 203a or at least one end of the support structure 203b is in contact with a sidewall of the cavity structure 203 a. Alternatively, the support structures 203b may be formed simultaneously with the etching to form the cavity structures 203 a. The existence of the supporting structure 203b can obtain a larger cavity area in a certain area under the condition that the peeling interface is determined, and the rotary island cavity with the semi-enclosed and fully enclosed structures is designed to reduce the characteristic size of the cavity and avoid the damage of top silicon. The shape of the cavity structure 203a includes, but is not limited to, triangle, quadrilateral, polygon, circle, and other patterns with closed boundaries. The island-shaped supporting structure 203b may be connected to or disconnected from the periphery of the cavity, and the island-shaped supporting structure may be quadrilateral or triangular. In addition, as shown in fig. 24 (a) and (b) and 25 (a) and (b), which show a topography of a SON substrate employing the cavity structure including a support structure, fig. 24 (a) and (b) show that at least one end of the support structure 203b is in contact with a sidewall of the cavity structure 203a, and fig. 25 (a) and (b) show that the support structure 203b is located within the cavity structure 203 a. By adopting the cavity containing the graphical supporting structure, the SON substrate with larger area and no top silicon damage can be prepared. By adopting the design of the invention, the SON substrate with a large-area and high-density closed cavity structure can be prepared, the proportion of the cavity area to the total area of the substrate exceeds 12 percent, and the SON substrate is suitable for preparing integrated circuits.
In addition, in one example, for the design of the support structure, the following may be used: for any cavity structure, all points on the cavity plane can be taken as examples, for example, point 1, point 2, point 3 and … points n; the minimum cavity size corresponding to each point is found first, for example: dimension 1, dimension 2, dimension 3, …, dimension n, wherein the definition of cavity dimensions can be found in the description of the present specification at the definition of feature dimensions; then, from 1 to n minimum cavity sizes, a maximum size D can be found, defined as a cavity feature size, consistent with the cavity feature size definition described above; then, setting the minimum cavity size of m (m < n) points to be equal to the cavity characteristic size D in 1-n points; finally, after the peninsula/rotary island type supporting structure is added in the cavity, the structure simultaneously reduces the minimum cavity size corresponding to the m points, so that the characteristic size of the cavity can be reduced by the supporting structure. In an example, it may be that for all support structures within the cavity structure, its projection onto each sidewall of the cavity structure covers that sidewall, with no exposed sidewall. Thereby reducing a feature size of the cavity structure based on the support structure.
Finally, as shown in S4 in fig. 1 and fig. 17 to 21, step S4 is performed to peel the first substrate 100 along the preset peeling layer 101a, so that a portion of the first substrate 100 is transferred onto the patterned dielectric layer 203, so as to form a transfer substrate film 104 on the patterned dielectric layer 203, thereby obtaining a semiconductor substrate with a cavity structure, as shown in fig. 17.
Specifically, the first substrate 100 may be peeled from the position of the preset peeling layer 101a by thermal annealing, for example, the initial bonding structure may be annealed at a temperature between 400 ℃ and 700 ℃, and other peeling methods known in the art may be used. At this time, due to the setting of the position of the preset release layer 101a in the present invention, the thickness of the transfer substrate film 104 is the preset distance d, and the thickness of the transfer substrate film 104 is greater than 1/8 of the cavity feature size of the cavity structure 203 a.
As an example, the step of peeling the first substrate along the preset peeling layer 101a further includes: the semiconductor substrate with the cavity structure is subjected to a strengthening treatment, wherein the strengthening treatment comprises a heating treatment, such as a high-temperature heating treatment, for example, at 1000-1300 ℃. Of course, other reinforcement means may be employed.
In a further alternative example, the heating treatment is performed under a preset atmosphere including an oxygen atmosphere to oxidize the surface of the transfer substrate film 104 to form a surface oxide layer 105 as shown in fig. 18, and the surface oxide layer 105 is removed after the heating treatment is performed as shown in fig. 19 to thin the transfer substrate film 104. In this way, the transfer substrate film 104 can be thinned by oxidation during the process of reinforcing the composite substrate structure, which is the semiconductor substrate having the cavity structure. In one example, hydrofluoric acid is used to etch the surface oxide layer 105 to thin the transfer substrate film 104.
As an example, the method further comprises the steps of: the transfer substrate film 104 is thinned, which includes mechanical first thinning by a chemical mechanical polishing process and second thinning by an oxidation thinning process, to obtain a thinned structure 106. That is, the transfer substrate film 104 is thinned in a two-step manner, wherein the first thinning may be rough polishing, for example, CPM may be performed, and the time for performing the first thinning may be selected according to practical experience. Then, the second thinning is performed on the basis, and an oxidation thinning process can be adopted, that is, an oxide layer is formed on the surface of the transfer substrate film layer after the first thinning, and then the oxide layer is removed, so that thinning is further realized, and the thickness of the transfer substrate film layer remained after thinning is accurately defined.
In an example, the first thinning and the second thinning in this example are preferably performed after performing the heat curing treatment and removing the surface oxide layer 105 in the oxygen atmosphere in the above example, to obtain the post-thinning structure 106, as shown in fig. 20. After the oxide layer 105 is removed, the thickness of the transfer substrate film 107 (e.g., top silicon) is reduced, and the pressure that the transfer substrate film above the cavity structure 203a can bear is reduced, so if the transfer substrate film is further thinned and polished by using a CMP process, the top silicon is easily damaged, and therefore, in this example, the CMP process is used to perform the rough thinning and then the oxide thinning process is used to continue the secondary oxide thinning, which is beneficial to precisely defining the thickness.
As an example, the thinning process further comprises the steps of: and repairing the thinned surface to make the thinned surface reach atomic level flatness, so as to obtain a cavity upper film layer 107, as shown in fig. 21. In an example, the repair process includes annealing the semiconductor substrate having the cavity structure under a hydrogen atmosphere at a temperature between 800 ℃ and 1300 ℃, for example, 1000 ℃. In addition, fig. 23 shows that the semiconductor substrate structure (SON substrate) obtained by the above steps of the present embodiment can obtain the cavity upper film layer 107 having excellent performance and almost no breakage. The second semiconductor substrate 201 is used as a bottom silicon layer, the patterned dielectric layer 203 is used as an intermediate buried oxide layer in SON, the cavity structure 203a is used as a substrate cavity, and the upper film layer 107 of the cavity is used as a top silicon layer.
For further explanation of the effects of the present invention, referring to FIGS. 27-28, FIG. 27 shows that when the lift-off thickness of the top silicon (top silicon thickness 1 μm) is less than or equal to 1/8 of the feature size of the cavity, the top silicon above the cavity is broken to varying degrees; as can be seen from the experiment in FIG. 27, the top silicon layer had a thickness of 1 μm and a breakage occurred in the top silicon layer at a cavity feature size of 8. Mu.m. As can be seen from fig. 27, the top silicon thickness should be at least greater than 1/8 of the cavity feature size to ensure top silicon integrity. Of course, other thickness values of the top layer silicon, such as 2 μm, 3 μm, 5 μm, etc., may be further selected to ensure the full range of the top layer silicon when other thicknesses are obtained. Fig. 28 shows a damaged top silicon layer over a hollow cavity structure of a semiconductor substrate having a hollow cavity structure formed by the method of forming a preset lift-off layer according to the present invention, wherein the top silicon layer over the hollow cavity structure is substantially undamaged according to the present invention. Fig. 29 shows a SON substrate with a large-area, high-density closed cavity structure prepared by the inventive scheme, wherein the top silicon is translucent and the lower part contains 0.5 um by 3 um cavities. After the optimization technology (the initial stripping thickness is set through the characteristic dimension) is adopted, the SON substrate containing a large-area cavity and 100% of top silicon without damage can be prepared, and the SON substrate can be applied to high-density integrated circuits. By adopting the design of the invention, the SON substrate with a large-area and high-density closed cavity structure can be prepared, the proportion of the cavity area to the total area of the substrate exceeds 12 percent, and the SON substrate is suitable for preparing integrated circuits.
Example 2:
This embodiment 2 provides another method for manufacturing a semiconductor substrate having a cavity structure, and this embodiment 2 is different from embodiment 1 in the process of forming an initial bonding structure, as shown in fig. 2, 3, and 10-16. In this example 2: the first base 100 includes a first semiconductor substrate 101 and the patterned dielectric layer 103 formed on the first semiconductor substrate 101, and as shown in fig. 10, the preset peeling layer 101a is formed in the first semiconductor substrate 101.
The forming process of the patterned dielectric layer 103 includes: the sacrificial dielectric layer 102 is formed on the first semiconductor substrate 101, the ion implantation is performed from the side where the sacrificial dielectric layer is formed to form the preset release layer 101a, the sacrificial dielectric layer 102 is patterned to obtain the patterned dielectric layer 103, and the patterned dielectric layer 103 has the cavity structure 103a therein, see fig. 2, 3 and 10.
In an example, the cavity structure 103a extends into the material layer below the patterned dielectric layer 103 and into the first semiconductor substrate 101, as shown in fig. 11. When the cavity structure 103a needs to extend into the first semiconductor substrate 101, the preset distance d is a distance between the bottom of the cavity structure 103a extending into the first semiconductor substrate 101 and the preset release layer 101a, and is set according to the manner in embodiment 1 when performing ion implantation, and is defined by the energy of the implanted ions, and the like. In an example, after bonding to obtain an initial bonding structure, the first substrate 100 is used as the top silicon of the SON substrate, i.e. the cavity structure 103a extends into the top silicon.
In addition, in this embodiment 2, the second base 200 includes a second semiconductor substrate 201, as shown in fig. 13, in which the patterned dielectric layer 103 of the first base 100 is bonded to the second base 200. In an alternative example, the second substrate 200 further includes an isolation layer 202 formed on the second semiconductor substrate 201, as shown in fig. 12, the isolation layer 202 is bonded to the patterned dielectric layer 103 of the first substrate 100, and the cavity structure 103a in the patterned dielectric layer 103 exposes the isolation layer 202 to facilitate isolation of device cavities.
In this embodiment 2, the initial bonding structure obtained by bonding the first substrate and the second substrate is shown in three examples of fig. 14 to 16. FIG. 14 shows a bonding initiation structure in which the second substrate 200 has an isolation layer 202; fig. 15 shows that in the bonding initiation structure, the cavity structure 103a in the patterned dielectric layer 103 of the first substrate 100 extends into the first semiconductor substrate 101, and the second substrate 200 has an isolation layer 202; fig. 16 shows that in the bonding initiation structure, the cavity structure 103a in the patterned dielectric layer 103 of the first substrate 100 extends into the first semiconductor substrate 101, and the second substrate 200 does not have the isolation layer 202. Of course, other initial bonding structures may be formed according to the descriptions of the first substrate and the second substrate.
Example 3:
as shown in fig. 17 and 23, referring to fig. 1 to 16, embodiment 3 provides a semiconductor substrate structure with a cavity structure, where the semiconductor substrate with a cavity structure is preferably prepared by using the preparation method of the semiconductor substrate with a cavity structure provided in embodiment 1 or embodiment 2 of the present invention, and of course, other methods may also be used for preparing the semiconductor substrate with a cavity structure. Features of each structural layer in the semiconductor substrate with a cavity structure in this embodiment may be referred to the descriptions in embodiment 1 and embodiment 2, and will not be described herein again.
The semiconductor substrate structure comprises: the first substrate 100 comprises a cavity upper film layer 107, wherein the cavity upper film layer 107 is obtained by stripping the first semiconductor substrate 101 and is further obtained by thinning the transfer substrate film layer 104; and a second base 200 bonded to the first base 100, the second base 200 including a second semiconductor substrate 201; the semiconductor substrate further comprises a patterned dielectric layer 203 or 103 having a cavity structure 203a or 103a, the patterned dielectric layer 203 or 103 is formed between the second semiconductor substrate 201 and the upper cavity film 107, the transfer substrate film 104 has a first surface close to the cavity structure 203a or 103a and a second surface opposite to the first surface, and a distance between the second surface and the cavity structure 203a or 103a is greater than 1/8 of a characteristic size of the cavity, where the surface of the transfer substrate film 104 close to the patterned dielectric layer is a surface of the upper cavity film 107 close to the patterned dielectric layer, and an upper surface of the upper cavity film 107 is thinned based on the second surface. In another example, the distance between the second surface and the cavity structure 203a or 103a is less than 2 μm. In this embodiment 3, the first substrate 100 and the second substrate 200 are described in accordance with embodiments 1 and 2, and the patterned dielectric layer 203 or 103 is described separately from embodiments 1 and 2, and is described separately from the first substrate 100 and the second substrate 200, as will be understood by those skilled in the art.
As an example, the cavity structure 203a or 103a has a support structure 300 therein, a top surface of the support structure 300 is flush with an upper surface of the patterned dielectric layer 203 or 103, and the support structure 300 is located within the cavity structure 203a or 103a or at least one end of the support structure 300 is in contact with a sidewall of the cavity structure 203. The cavity structure is designed into a cavity structure with a supporting structure, namely, a semi-enclosed type and full-enclosed type rotary island cavity is formed, a larger cavity area can be obtained in a certain area under the condition that the stripping interface is determined, the rotary island cavity with the semi-enclosed and full-enclosed structure is contained, the characteristic size of the cavity can be reduced, and the damage of top silicon is avoided.
As an example, an isolation layer 202 is further formed between the second semiconductor substrate 200 and the patterned dielectric layer 203 or 103, and the cavity structure 203a or 103a exposes the isolation layer 202.
As an example, the cavity structure 203a or 103a extends through the patterned dielectric layer 203 or 103 and the cavity structure 203a or 103a extends into at least one of the second semiconductor substrate 201 and the transfer substrate film 107.
In summary, in the semiconductor substrate with the cavity structure and the preparation method thereof, when ion implantation is performed to form the peeling interface, the preset peeling layer is prefabricated according to the cavity structure to be formed, and the preset distance between the preset peeling layer and the cavity structure to be formed is greater than 1/8 of the cavity characteristic dimension of the cavity structure, so that the material layer above the cavity structure can be ensured not to be damaged in the process of preparing the semiconductor substrate with the cavity structure, and the yield and performance of the device are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (19)

1. A method for manufacturing a semiconductor substrate having a cavity structure, the method comprising the steps of:
Providing a first substrate and a second substrate;
performing ion implantation on the first substrate to form a preset stripping layer in the first substrate, wherein a preset distance is reserved between the preset stripping layer and a cavity structure to be formed, the preset distance is set according to the cavity structure, and the setting mode comprises that the preset distance is greater than 1/8 of the cavity characteristic size of the cavity structure;
The defining mode of the characteristic dimension of the cavity comprises the following steps: defining a two-dimensional plane parallel to the surface of the cavity structure above the cavity structure; in the two-dimensional plane, a plurality of selection points are arranged above the cavity structure; for each of the selected points, there are several straight lines passing through the selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are adjacent to the selected point in the two directions of extending the straight line passing through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum of said cavity dimensions based on a number of said straight lines passing through each of said selected points; selecting the maximum value of all the cavity sizes based on a plurality of selected points above the cavity structure to obtain the cavity characteristic size; bonding one side of the first substrate subjected to the ion implantation and the second substrate to obtain an initial bonding structure, wherein the initial bonding structure comprises a graphical medium layer with the cavity structure, and a space is reserved between the graphical medium layer and the preset stripping layer; and
And stripping the first substrate along the preset stripping layer, and transferring a part of the first substrate onto the patterned dielectric layer to form a transfer substrate film layer on the patterned dielectric layer so as to obtain the semiconductor substrate with the cavity structure.
2. The method of manufacturing a semiconductor substrate having a cavity structure according to claim 1, wherein the first base includes a first semiconductor substrate, the preset release layer is formed in the first semiconductor substrate, the second base includes a second semiconductor substrate and the patterned dielectric layer formed on the second semiconductor substrate, and wherein a side of the first base where the ion implantation is performed and the patterned dielectric layer of the second base are bonded.
3. The method of manufacturing a semiconductor substrate having a cavity structure according to claim 2, further comprising the step of, before performing the ion implantation: and forming a sacrificial dielectric layer on the surface of the first semiconductor substrate, performing ion implantation from the side on which the sacrificial dielectric layer is formed, and removing the sacrificial dielectric layer after the ion implantation is completed.
4. The method of manufacturing a semiconductor substrate having a cavity structure according to claim 2, wherein an isolation layer is further formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.
5. The method of manufacturing a semiconductor substrate having a cavity structure according to claim 1, wherein the first base includes a first semiconductor substrate and the patterned dielectric layer formed on the first semiconductor substrate, the preset peeling layer is formed in the first semiconductor substrate, and the second base includes a second semiconductor substrate, wherein the patterned dielectric layer of the first base is bonded to the second base.
6. The method of manufacturing a semiconductor substrate having a cavity structure according to claim 5, wherein the step of forming the first base includes: providing the first semiconductor substrate; forming a sacrificial dielectric layer on the first semiconductor substrate; performing the ion implantation on the first semiconductor substrate from the side where the sacrificial dielectric layer is formed; and patterning the sacrificial dielectric layer to obtain the patterned dielectric layer with the cavity structure.
7. The method of claim 5, wherein the second base further comprises an isolation layer formed on the second semiconductor substrate, the isolation layer is bonded to the patterned dielectric layer of the first base, and the cavity structure in the patterned dielectric layer reveals the isolation layer.
8. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 1, wherein the step of performing the ion implantation to form the predetermined peeling layer comprises: performing a first ion implantation on the first substrate to form an initial release layer in the first substrate; and performing second ion implantation at the position of the initial stripping layer to form the preset stripping layer, wherein the implantation particles of the first ion implantation comprise B-containing impurities, and the implantation particles of the second ion implantation comprise at least one of H ions and He ions.
9. The method according to claim 8, wherein the first ion implantation dose is smaller than the second ion implantation dose; the implantation dosage of the first ion implantation is between 1e11 and 1e13/cm 2, and the implantation dosage of the second ion implantation is between 1e16 and 1e17/cm 2.
10. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 1, further comprising the step of, after peeling the first base along the preset peeling layer: and carrying out reinforcement treatment on the semiconductor substrate with the cavity structure, wherein the reinforcement treatment comprises heating treatment on the semiconductor substrate with the cavity structure.
11. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 10, wherein the heating treatment is performed under a preset atmosphere including an oxygen atmosphere to form a surface oxide layer on the surface of the transfer substrate film, and the surface oxide layer is removed after the heating treatment is completed to thin the transfer substrate film.
12. The method of claim 1, wherein the cavity structure in the patterned dielectric layer further extends into a material layer below the patterned dielectric layer.
13. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 1, wherein the predetermined distance between the predetermined peeling layer and the cavity structure is between 2nm and 10 μm.
14. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 1, wherein the setting of the ratio of the preset distance to the feature size of the cavity structure comprises: defining the pressure on the upper surface of the cavity structure as p in the stripping process, defining the length of the cavity structure in the directional plane as infinitely long, defining the worst condition as that the two sides of the central position of the transfer substrate film layer above the cavity only use the patterned dielectric layer as supporting points to obtain the maximum stress Mmax-pL 2 and the maximum stress sigma max-qL 2/h2 in the transfer substrate film layer, wherein h is the preset distance, L is the characteristic dimension of the cavity structure, and obtaining the ratio of the preset distance to the characteristic dimension of the cavity structure by adopting a test design mode based on the maximum stress which can be born by the transfer substrate film layer.
15. The method for manufacturing a semiconductor substrate having a cavity structure according to any one of claims 1 to 14, further comprising the step of, after obtaining the semiconductor substrate having a cavity structure: and carrying out thinning treatment on the transfer substrate film layer structure, wherein the thinning treatment comprises first thinning by adopting chemical mechanical polishing and second thinning by adopting oxidation thinning.
16. The method for manufacturing a semiconductor substrate having a cavity structure according to claim 15, further comprising the step of, after the thinning process: and carrying out repair treatment on the thinned surface so as to enable the thinned surface to be atomically flat, wherein the repair treatment process comprises the step of annealing the thinned semiconductor substrate with the cavity structure in a hydrogen atmosphere, and the annealing temperature is between 800 and 1300 ℃.
17. A semiconductor substrate structure having a cavity structure, the semiconductor substrate structure comprising:
the first substrate comprises a cavity upper film layer, and the cavity upper film layer is obtained by thinning the transfer substrate film layer;
A second substrate bonded to the first substrate, the second substrate comprising a second semiconductor substrate;
The patterned dielectric layer is formed between the second semiconductor substrate and the upper film layer of the cavity, the transfer substrate film layer is provided with a first surface close to the cavity structure and a second surface opposite to the first surface, and the distance between the second surface and the cavity structure is greater than 1/8 of the cavity characteristic size of the cavity structure;
The defining mode of the cavity characteristic dimension comprises the following steps: defining a two-dimensional plane parallel to the surface of the cavity structure above the cavity structure; in the two-dimensional plane, a plurality of selection points are arranged above the cavity structure; for each of the selected points, there are several straight lines passing through the selected point; at least two contact points are arranged between each straight line and the edge of the cavity structure, a first contact point and a second contact point which are adjacent to the selected point in the two directions of extending the straight line passing through the selected point are selected, and the distance between the first contact point and the second contact point is defined as the size of the cavity; obtaining a minimum of said cavity dimensions based on a number of said straight lines passing through each of said selected points; and selecting the maximum value in all the cavity sizes based on a plurality of selected points above the cavity structure, and obtaining the cavity characteristic size.
18. The semiconductor substrate with the cavity structure according to claim 17, wherein an isolation layer is further formed between the second semiconductor substrate and the patterned dielectric layer, and the cavity structure exposes the isolation layer.
19. The semiconductor substrate with cavity structure of any one of claims 17-18, wherein the cavity structure extends through the patterned dielectric layer and the cavity structure further extends into at least one of the second semiconductor substrate and the transfer substrate film.
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