CN116193858A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN116193858A CN116193858A CN202211542608.8A CN202211542608A CN116193858A CN 116193858 A CN116193858 A CN 116193858A CN 202211542608 A CN202211542608 A CN 202211542608A CN 116193858 A CN116193858 A CN 116193858A
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- 238000002360 preparation method Methods 0.000 title abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 204
- 239000000758 substrate Substances 0.000 claims abstract description 111
- 239000002346 layers by function Substances 0.000 claims abstract description 65
- 238000002161 passivation Methods 0.000 claims description 54
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 238000005530 etching Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005498 polishing Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000004952 Polyamide Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a three-dimensional memory and a preparation method thereof. The preparation method of the three-dimensional memory comprises the following steps: providing a wafer structure, wherein the wafer structure comprises a memory cell array, the memory cell array comprises a first substrate, a first insulating layer and a functional layer, the first substrate comprises a first surface and a second surface opposite to the first surface, the first insulating layer is formed on the first surface, and the functional layer is formed on the second surface; forming a contact hole in the first insulating layer and the first substrate, wherein the contact hole exposes the functional layer; and forming the first contact in the contact hole, wherein the first contact is flush with the functional layer. The three-dimensional memory structure is smooth, and the yield of the three-dimensional memory is high.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-dimensional memory and a preparation method thereof.
Background
The first contact extends into the functional layer, after the through hole is formed at the position of the functional layer corresponding to the first contact, the first contact protrudes into the through hole, when a subsequent structure is formed in the through hole, a bulge is usually formed at the position of the subsequent structure corresponding to the first contact, and finally the formed three-dimensional memory structure is uneven, so that the yield of the three-dimensional memory is affected.
Disclosure of Invention
The invention aims to provide a three-dimensional memory and a preparation method thereof, which are used for solving the technical problem that the structure of the three-dimensional memory is uneven and the yield of the three-dimensional memory is affected.
The invention provides a preparation method of a three-dimensional memory, which comprises the following steps: providing a wafer structure, wherein the wafer structure comprises a memory cell array, the memory cell array comprises a first substrate, a first insulating layer and a functional layer, the first substrate comprises a first surface and a second surface opposite to the first surface, the first insulating layer is formed on the first surface, and the functional layer is formed on the second surface; forming a contact hole in the first insulating layer and the first substrate, wherein the contact hole exposes the functional layer; and forming the first contact in the contact hole, wherein the first contact is flush with the functional layer.
Wherein the functional layer includes a first passivation layer laminated on the first substrate, and the "forming a contact hole in the first insulating layer and the first substrate" includes: and selectively etching the first substrate and the first insulating layer, so that the contact hole stops on the surface of the first passivation layer after penetrating through the first insulating layer and the first substrate.
Wherein, after forming the functional layer, the preparation method further comprises: and forming a first via hole and a second via hole on the functional layer, wherein the first contact is exposed out of the first via hole, and the first substrate is exposed out of the second via hole.
The functional layer further comprises a second insulating layer, the second insulating layer is formed on the first passivation layer, and a second substrate is laminated on the surface, facing away from the first passivation layer, of the second insulating layer; the "forming the first via hole and the second via hole on the functional layer" includes: removing a portion of the second substrate from a surface of the second substrate facing away from the second insulating layer to form a reference substrate, wherein a thickness of the reference substrate is less than a thickness of the second substrate; removing the reference substrate; and forming the first via hole and the second via hole on the second insulating layer and the first passivation layer.
Wherein, after forming the first via hole and the second via hole, the preparation method further comprises: and forming a first connection structure in the first via hole and a second connection structure in the second via hole, wherein the first connection structure is connected with the first contact, and the second connection structure is connected with the first substrate.
Wherein, after forming the first connection structure and the second connection structure, the preparation method further comprises: and forming a flat layer, a second passivation layer and a protective layer on the first connecting structure, the second connecting structure and the second insulating layer in sequence, wherein a first through hole and a second through hole are formed on the flat layer, the second passivation layer and the protective layer, the first through hole is exposed out of the first connecting structure, and the second through hole is exposed out of the second connecting structure.
The memory cell array further comprises a plurality of gate layers and a plurality of channel structures, wherein the gate layers are positioned in the first insulating layer at intervals, and the gate layers form a step shape; each channel structure penetrates through a plurality of the gate layers; the memory cell array further comprises a first bonding layer, wherein the first bonding layer is arranged on the first insulating layer, a plurality of first wirings and a plurality of second contacts are further arranged in the first insulating layer, the second contacts are respectively connected with one grid layer and then connected with one first wiring, the channel structures are connected with one first wiring, and each first contact is connected with one first wiring; the wafer structure also comprises a peripheral circuit, wherein the peripheral circuit comprises a third substrate, a peripheral interconnection layer arranged on the third substrate and a second bonding layer arranged on the peripheral interconnection layer, and a plurality of second wiring lines arranged at intervals are arranged in the peripheral interconnection layer; the first bonding layer is in bonding connection with the second insulating layer, and the plurality of first wirings are correspondingly connected with the plurality of second wirings.
The first contact is made of tungsten, and the first connecting structure and the second connecting structure are made of aluminum; the first passivation layer and the second passivation layer are made of silicon nitride; the first substrate is made of amorphous silicon; the first insulating layer and the second insulating layer are made of uniform silicon dioxide; the material of the flat layer is silicon dioxide.
The invention provides a three-dimensional memory, which is prepared by the preparation method.
The present invention provides a three-dimensional memory comprising: a memory cell array including a first substrate including a first surface on which the first insulating layer is formed, and a second surface disposed opposite to the first surface, a first insulating layer formed on the second surface, and a functional layer formed on the first surface; a first contact formed within the first insulating layer and the first substrate, and the first contact is flush with the functional layer.
The functional layer comprises a first passivation layer, the first passivation layer is laminated on the first substrate, and the first contact is flush with the first passivation layer.
The functional layer further comprises a second insulating layer, the second insulating layer is formed on the first passivation layer, a first via hole and a second via hole are formed in the second insulating layer and the first passivation layer, a first connecting structure is formed in the first via hole, a second connecting structure is formed in the second via hole, the first connecting structure is connected with the first contact, and the second connecting structure is connected with the first substrate.
Wherein the memory cell array further comprises: the flat layer, the second passivation layer and the protective layer are sequentially formed on the second insulating layer, the first connecting structure and the second connecting structure, wherein a first through hole and a second through hole are formed in the flat layer, the second passivation layer and the protective layer, the first through hole is exposed out of the first connecting structure, and the second through hole is exposed out of the second connecting structure.
To sum up, this application is through setting up first contact and functional layer parallel and level, when the position that the functional layer corresponds first contact forms the via hole, first contact can not extend in the via hole, when forming subsequent structure in the via hole, and subsequent structure is also level, and three-dimensional memory structure is level, and three-dimensional memory's yield is better.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 to 3 are schematic structural views of a three-dimensional memory manufactured by a conventional manufacturing method.
Fig. 4 is a flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.
Fig. 5 is a schematic structural view of the wafer structure of fig. 4.
Fig. 6 is a schematic diagram of the structure of the second substrate in fig. 4 thinned to obtain a reference substrate.
Fig. 7 is a schematic diagram of a structure in which the reference substrate in fig. 6 is removed.
Fig. 8 is a schematic structural view of forming a first via hole and a second via hole in the functional layer in fig. 7.
Fig. 9 is a schematic structural view of forming a first connection structure in the first through hole and forming a second connection structure in the second through hole in fig. 8.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Before describing the embodiments of the present invention, the following method for preparing a conventional three-dimensional memory will be briefly described.
Referring to fig. 1-3, a conventional method for manufacturing a three-dimensional memory generally includes: providing a wafer structure, wherein the wafer structure comprises a memory cell array 10, the memory cell array 10 comprises a first substrate 101, a first insulating layer 102 and a functional layer 20, the first substrate 101 comprises a first surface 101a and a second surface 101b opposite to the first surface 101a, the first insulating layer 102 is formed on the first surface 101a, the functional layer 20 is formed on the second surface 101b, and the functional layer 20 is laminated with a second substrate 90 (fig. 1); a contact hole 30 is formed in the first insulating layer 102 and the first substrate 101, and a first contact 40 is formed in the contact hole 30. However, since the etching performance of the first substrate 101, the functional layer 20 and the second substrate 90 is relatively close, the contact hole 30 formed by etching generally extends into the second substrate 90, after the first contact 40 is formed in the contact hole 30, the first contact 40 also extends into the second substrate 90, after the functional layer 20 is removed, the first contact 40 protrudes out of the functional layer 20 (fig. 2), and of course, when the via hole is formed at the position of the functional layer 20 corresponding to the first contact 40, the first contact 40 also protrudes into the via hole, and when the subsequent structure is formed in the via hole, the protrusion C (fig. 3) is generally formed at the position of the subsequent structure corresponding to the first contact 40, and the finally formed three-dimensional memory structure is uneven, which affects the yield of the three-dimensional memory.
In order to solve the technical problems, the invention provides a preparation method of a three-dimensional memory. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a method for manufacturing a three-dimensional memory according to the present invention. According to the method, the first contact 40 is flush with the functional layer 20, when the position of the functional layer 20 corresponding to the first contact 40 forms a via hole, the first contact 40 cannot extend into the via hole, when a subsequent structure is formed in the via hole, the subsequent structure is also smooth, the three-dimensional memory structure is smooth, and the yield of the three-dimensional memory is good.
The method of manufacturing a three-dimensional memory is shown in fig. 4. As shown in fig. 4, the method can be broadly summarized as follows: a wafer structure is provided (S1), a contact hole 30 is formed in the first insulating layer 102 and the first substrate 101 (S2), and a first contact 40 is formed in the contact hole 30 (S3). As will be described below, respectively.
Referring to FIG. 4, the method first performs operations S1-S3:
s1, referring to fig. 5, a wafer structure is provided, the wafer structure includes a memory cell array 10, the memory cell array 10 includes a first substrate 101, a first insulating layer 102 and a functional layer 20, the first substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to the first surface 101a, the first insulating layer 102 is formed on the first surface 101a, and the functional layer 20 is formed on the second surface 101 b.
S2, a contact hole 30 is formed in the first insulating layer 102 and the first substrate 101, and the contact hole 30 exposes the functional layer 20. In this step, the contact hole 30 does not extend to the functional layer 20 after penetrating the first substrate 101. That is, the contact hole 30 penetrates only the first insulating layer 102 and the first substrate 101.
S3, forming a first contact 40 in the contact hole 30, wherein the first contact 40 is flush with the functional layer 20. It will be appreciated that the surface of the first contact 40 is coplanar with the surface of the functional layer 20 and that the first contact 40 does not extend into the functional layer 20. The material of the first contact 40 is typically tungsten (W).
It is understood that the first substrate 101 includes a substrate body 105 and an insulator 106 disposed within the substrate body 105, and the contact hole 30 penetrates the insulator 106. The method of forming insulator 106 may be: an insulating hole is formed in the substrate body 105, and an insulating material is filled in the insulating hole to form an insulator 106. The first contact 40 is insulated from the substrate body 105. The insulator 106 may be silicon dioxide (SiO) 2 ). The substrate body 105 is made of amorphous silicon (a-Si), but may be made of other silicon-containing substrate bodies 105, such as silicon (Silicon On Insulator, SOI), siGe, si: C, etc. on the insulator 106, and various p-type/n-type or deep or shallow potential wells required by the device can be formed in the substrate body 105 by ion implantation or other processes. The material of the first insulating layer 102 is typically silicon dioxide (SiO 2 )。
In this application, through setting up first contact 40 and functional layer 20 parallel and level, when the position that functional layer 20 corresponds first contact 40 forms the via hole, first contact 40 can not extend in the via hole, when forming subsequent structure in the via hole, subsequent structure is also level, and three-dimensional memory structure is level, and three-dimensional memory's yield is better.
As shown in fig. 5, it can be understood that the memory cell array 10 has a step region a and an edge region B connected to the step region a.
The memory cell array 10 further includes a plurality of gate layers 103 and a plurality of channel structures 107, wherein the plurality of gate layers 103 are spaced apart from each other within the first insulating layer 102, and the plurality of gate layers 103 form a step shape; each channel structure 107 extends through multiple gate layers 103; the plurality of gate layers 103 are located in the step region a and the first contact 40 is located in the edge region B. It will be appreciated that a plurality of channel holes penetrating the plurality of gate layers 103 and the first insulating layer 102 are provided in the step region a, and one channel structure 107 is provided in each channel hole, the channel structure 107 including a charge storage layer and a channel layer, the charge storage layer including a blocking insulating layer, a charge trapping layer and a tunneling insulating layer along sidewalls of the channel hole toward a center of the hole. An exemplary material for the blocking insulating layer and the tunneling insulating layer is silicon oxide, an exemplary material for the charge trapping layer is silicon nitride, and the charge storage layer forms a silicon oxide-silicon nitride-silicon oxide (ONO) stack structure. An exemplary material for the channel layer is silicon (Si). Other materials may be selected for the blocking insulating layer, the charge trapping layer, and the tunneling insulating layer, and are not limited herein.
The memory cell array 10 further includes a first bonding layer 108, the first bonding layer 108 is disposed on the first insulating layer 102, a plurality of first wirings 50 and a plurality of second contacts 104 are disposed in the first insulating layer 102, the plurality of second contacts 104 are connected to one first wiring 50 after being connected to one gate layer 103, the plurality of channel structures 107 are connected to one first wiring 50, and each first contact 40 is connected to one first wiring 50.
The wafer structure further comprises a peripheral circuit 60, wherein the peripheral circuit 60 comprises a third substrate 601, a peripheral interconnection layer 602 arranged on the third substrate 601 and a second bonding layer 603 arranged on the peripheral interconnection layer 602, and a plurality of second wirings 604 arranged at intervals are arranged in the peripheral interconnection layer 602; the first bonding layer 108 is bonded to the second bonding layer 108, and the plurality of first wirings 50 are correspondingly connected to the plurality of second wirings 604. The material of the third substrate 601 is typically silicon (Si).
It can be appreciated that the memory cell array 10 is connected to the peripheral circuit 60 to form a wafer structure by bonding the first bonding layer 108 to the second bonding layer 603. The connection of the first wires 50 to the corresponding second wires 604 forms a via structure inside the wafer structure. In fig. 5, two first contacts 40 are respectively connected to one first wiring 50 located on the left side, five gate layers 103 are provided, five second contacts 104 are respectively connected to one gate layer 103 and then to one first wiring 50, for example, two first wirings 50 located in the middle in fig. 5 are provided, two channel structures 107 are provided, and two channel structures 107 are connected to the first wiring 50 located on the right side. Alternatively, the internal pads 70 and the conductive vias 80 may be disposed within the first insulating layer 102, and the first contacts 40, the second contacts 104, and the channel structures 107 may each be connected to one of the internal pads 70, with the conductive vias 80 connecting the internal pad 70 with the first wiring 50. I.e., the first contact 40, the second contact 104, and the channel structure 107, may be connected to the first wiring 50 through the internal pad 70 and the conductive via 80.
It may be understood that the first bonding layer 108 is provided with a first interconnection channel, the second bonding layer 603 is provided with a second interconnection channel, and when the first bonding layer 108 is bonded to the second bonding layer 603, the first interconnection channel and the second interconnection channel are correspondingly connected, so that the plurality of first wires 50 are correspondingly connected to the plurality of second wires 604.
In a specific embodiment, the functional layer 20 includes a first passivation layer 201, the first passivation layer 201 is stacked on the first substrate 101, "forming the contact hole 30 in the first insulating layer 102 and the first substrate 101" includes:
the first substrate 101 and the first insulating layer 102 are selectively etched such that the contact hole 30 stops on the surface of the first passivation layer 201 after penetrating the first insulating layer 102 and the first substrate 101. It is understood that the material properties of the first passivation layer 201 are different from those of the first substrate 101, so that the contact hole 30 stops extending after penetrating the first substrate 101, and the first passivation layer 201 is not etched. The etching process of the first insulating layer 102 and the first substrate 101 may be an anisotropic dry etching process, and a selective etchant such as an etching gas such as SF6, NF3, COS, cl2, HBr, fluorocarbon (CF 4, CHF 3) or the like having relatively small fluorocarbon may be used; of course, the present application may also etch the first substrate 101 and the first insulating layer 102 with a high carbon/fluorine ratio gas (C/F ratio) and/or a hydrocarbon gas (CHx) to avoid etching the first passivation layer 201 with an etching gas. The etching ratio of the first substrate 101 to the first passivation layer 201 may be greater than 5, for example, the etching ratio may be 6, 10, 15, 100, 1000, etc., and the application is not particularly limited to the etching ratio of the first substrate 101 to the first passivation layer 201, as long as the etching gas does not etch or does not substantially etch the first passivation layer 201 after etching the first substrate 101. In this application, since the contact hole 30 does not extend into the first passivation layer 201, the first contact 40 does not extend into the first passivation layer 201, i.e., the first contact 40 is not at all in the first passivation layer 201, and the first passivation layer 201 is flush with the first contact 40. When the functional layer 20 is formed at a position corresponding to the electric shock of the substrate, the first contact 40 cannot extend into the via hole, the first contact 40 does not exist in the via hole, and when a subsequent structure is formed in the via hole, the subsequent structure is flat, the three-dimensional memory structure is flat, and the yield of the three-dimensional memory is good. The material of the first passivation layer 201 may be silicon nitride (SiN).
In a specific embodiment, after forming the functional layer 20, the preparation method further includes:
referring to fig. 8, a first via hole 20a and a second via hole 20b are formed on the functional layer 20, the first via hole 20a exposes the first contact 40, and the second via hole 20b exposes the first substrate 101. It will be appreciated that since the first contact 40 does not extend within the functional layer 20, after the first via 20a is formed on the functional layer 20, the first contact 40 does not extend within the first via 20a, and the first contact 40 is flush with the bottom wall of the first via 20 a. When the subsequent structure is formed in the first via hole 20a, the subsequent structure may be accommodated in the first via hole 20a smoothly. The second via hole 20b is used for exposing the first substrate 101, a subsequent structure for guiding the first substrate 101 is formed in the second via hole 20b, and when the subsequent structure is formed in the second via hole 20b, the subsequent structure can be accommodated in the second via hole 20b smoothly.
Referring to fig. 6-7, in a specific embodiment, the functional layer 20 further includes a second insulating layer 202, the second insulating layer 202 is formed on the first passivation layer 201, and the second substrate 90 is laminated on a surface of the second insulating layer 202 facing away from the first passivation layer 201;
the "forming the first via hole 20a and the second via hole 20b on the functional layer 20" includes:
referring to fig. 6, a portion of the second substrate 90 is removed from a surface of the second substrate 90 facing away from the second insulating layer 202 to form a reference substrate 110, wherein a thickness of the reference substrate 110 is less than a thickness of the second substrate 90;
referring to fig. 7, the reference substrate 110 is removed;
a first via hole 20a and a second via hole 20b are formed on the second insulating layer 202 and the first passivation layer 201.
It can be appreciated that the method of forming the memory cell array 10 is generally: a layer structure of the memory cell array 10 is formed on the second substrate 90, and then the second substrate 90 is removed. The present application first faces away from the second insulating layer from the second substrate 90202, removing a portion of the second substrate 90 from the surface of the second substrate 90 facing away from the second insulating layer 202, i.e. thinning the second substrate 90, the method of thinning the second substrate 90 may be chemical mechanical polishing. Since the second substrate 90 is thicker, the process of removing part of the second substrate 90 may be rapid grinding or rough grinding, that is, the process from the second substrate 90 to the reference substrate 110 is rapid grinding, so as to accelerate the thinning speed of the second substrate 90 and save time; after the reference substrate 110 is formed, the method of removing the reference substrate 110 may be chemical mechanical polishing, and the process of removing the reference substrate 110 may be slow polishing or fine polishing, so that the reference substrate 110 may be polished to a desired thickness and avoid polishing to the second insulating layer 202. In this embodiment, the reference substrate 110 is entirely polished away and not polished to the second insulating layer 202. The number of the first vias 20a may be plural, the number of the second vias 20b may be plural, and the number of the first vias 20a and the number of the second vias 20b may be set according to actual requirements. The material of the second substrate 90 is typically silicon (Si). The material of the second insulating layer 202 may be silicon dioxide (SiO 2 )。
In a specific embodiment, after forming the first via hole 20a and the second via hole 20b, the preparation method further includes:
referring to fig. 9, a first connection structure 120 is formed in the first via 20a, and a second connection structure 130 is formed in the second via 20b, wherein the first connection structure 120 is connected to the first contact 40, and the second connection structure 130 is connected to the first substrate 101. It will be appreciated that the first connection structure 120 is used to bring out the first contact 40 and the second connection structure 130 is used to bring out the first substrate 101. The subsequent structures above may be the first connection structure 120 and the second connection structure 130 herein. The first connection structure 120 may be formed smoothly within the first via 20a, and the second connection structure 130 may be formed smoothly within the second via 20b.
In a specific embodiment, after forming the first connection structure 120 and the second connection structure 130, the preparation method further includes:
at the first connection structure 120, the second connection structure 130 and the second insulation layer 202The planarization layer 140, the second passivation layer 150, and the protection layer 160 are sequentially formed thereon, wherein the planarization layer 140, the second passivation layer 150, and the protection layer 160 are formed with a first via 170 and a second via 180, the first via 170 exposes the first connection structure 120, and the second via 180 exposes the second connection structure 130. It can be understood that the first through hole 170 is used for conducting the first connection structure 120 and the outside, and the second through hole 180 is used for conducting the second connection structure 130 and the outside. Thus, when the first connection structure 120 is formed flatly in the first via hole 20a, the finally formed three-dimensional memory structure is flat, and the yield of the three-dimensional memory is better. The planarization layer 140 is made of silicon dioxide (SiO 2 ). The first connection structure 120 and the second connection structure 130 are made of aluminum (Al); the material of the second passivation layer 150 may be silicon nitride (SiN). The material of the protective layer is polyamide (polyamide).
Referring to fig. 9, in addition to the above method for manufacturing a three-dimensional memory, the embodiment of the invention further provides a three-dimensional memory. The three-dimensional memory and the preparation method of the three-dimensional memory in the embodiment of the invention can realize the advantages of the invention, and the three-dimensional memory and the preparation method of the three-dimensional memory can be used together or independently, and the invention is not particularly limited. In a specific embodiment, the three-dimensional memory is formed by the preparation method of the three-dimensional memory.
Referring to fig. 9, the present invention provides a three-dimensional memory, comprising:
the memory cell array 10, the memory cell array 10 includes a first substrate 101, a first insulating layer 102, and a functional layer 20, the first substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to the first surface 101a, the first insulating layer 102 is formed on the first surface 101a, and the functional layer 20 is formed on the second surface 101 b;
the first contact 40, the first contact 40 is formed in the first insulating layer 102 and the first substrate 101, and the first contact 40 is flush with the functional layer 20.
In this application, first contact 40 and functional layer 20 parallel and level, when the position that functional layer 20 corresponds first contact 40 forms the via hole, first contact 40 can not extend in the via hole, when forming subsequent structure in the via hole, and subsequent structure is also level, and three-dimensional memory structure is level, and three-dimensional memory's yield is better.
In a specific embodiment, the functional layer 20 includes a first passivation layer 201, the first passivation layer 201 being laminated on the first substrate 101, the first contact 40 being flush with the first passivation layer 201. In this application, since the contact hole 30 does not extend into the first passivation layer 201, the first contact 40 does not extend into the first passivation layer 201, i.e., the first contact 40 is not at all in the first passivation layer 201, and the first passivation layer 201 is flush with the first contact 40. When the functional layer 20 is formed at a position corresponding to the electric shock of the substrate, the first contact 40 cannot extend into the via hole, the first contact 40 does not exist in the via hole, and when a subsequent structure is formed in the via hole, the subsequent structure is flat, the three-dimensional memory structure is flat, and the yield of the three-dimensional memory is good. The material of the first passivation layer 201 may be silicon nitride (SiN).
In a specific embodiment, the functional layer 20 further includes a second insulating layer 202, the second insulating layer 202 is formed on the first passivation layer 201, the first via hole 20a and the second via hole 20b are formed on the second insulating layer 202 and the first passivation layer 201, the first connection structure 120 is formed in the first via hole 20a, the second connection structure 130 is formed in the second via hole 20b, the first connection structure 120 is connected to the first contact 40, and the second connection structure 130 is connected to the first substrate 101. In this application, the first connection structure 120 may be formed in the first via hole 20a, the second connection structure 130 may be formed in the second via hole 20b, the three-dimensional memory structure is flat, and the yield of the three-dimensional memory is better.
In a specific embodiment, the memory cell array 10 further includes: the planarization layer 140, the second passivation layer 150, and the protection layer 160 are sequentially formed on the second insulating layer 202, the first connection structure 120, and the second connection structure 130, wherein the planarization layer 140, the second passivation layer 150, and the protection layer 160 are formed with a first via 170 and a second via 180, the first via 170 exposing the first connection structure 120, and the second via 180 exposing the second connection structure 130. In this application, the first through hole 170 is used for conducting the first connection structure 120 and the outside, and the second through hole 180 is used for conducting the second connection structure 130 and the outside.
The memory cell array 10 further includes a first bonding layer 108, the first bonding layer 108 is disposed on the first insulating layer 102, a plurality of first wirings 50 and a plurality of second contacts 104 are disposed in the first insulating layer 102, the plurality of second contacts 104 are connected to one first wiring 50 after being connected to one gate layer 103, the plurality of channel structures 107 are connected to one first wiring 50, and each first contact 40 is connected to one first wiring 50.
The three-dimensional memory further comprises a peripheral circuit 60, wherein the peripheral circuit 60 comprises a third substrate 601, a peripheral interconnection layer 602 arranged on the third substrate 601 and a second bonding layer 603 arranged on the peripheral interconnection layer 602, and a plurality of second wirings 604 arranged at intervals are arranged in the peripheral interconnection layer 602; the first bonding layer 108 is bonded to the second bonding layer 108, and the plurality of first wirings 50 are correspondingly connected to the plurality of second wirings 604. The material of the third substrate 601 is typically silicon (Si).
The foregoing disclosure is illustrative of the preferred embodiments of the present invention, and is not to be construed as limiting the scope of the invention, as it is understood by those skilled in the art that all or part of the above-described embodiments may be practiced with equivalents thereof, which fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A three-dimensional memory, comprising:
the wafer structure comprises a first substrate, an insulating structure and a functional layer;
the first substrate comprises a first surface and a second surface opposite to the first surface;
the insulating structure comprises a first insulating layer positioned on the first surface and an insulator penetrating through the first substrate;
the functional layer is positioned on the second surface, and the functional layer comprises a material different from the insulator;
and the first contact is positioned in the first insulating layer and the insulator.
2. The three-dimensional memory of claim 1, wherein the functional layer comprises a first passivation layer, the first passivation layer being an etch stop layer.
3. The three-dimensional memory of claim 2, wherein the first contact is coplanar with a side of the first passivation layer proximate the first substrate.
4. The three-dimensional memory of claim 1, further comprising:
a first connection structure located at the second surface and in contact with the insulator;
the first contact is connected with the first connection structure;
the first connection structure is in contact with a side surface of the functional layer.
5. The three-dimensional memory of claim 4, further comprising:
a second connection structure located on the second surface and in contact with the first substrate;
the second connection structure is in contact with the side and surface of the functional layer.
6. The three-dimensional memory of claim 2, wherein the functional layer further comprises a second insulating layer located on a side of the first passivation layer remote from the first substrate.
7. The three-dimensional memory of claim 5, further comprising:
and the flat layer is positioned on the functional layer, the first connecting structure and the second connecting structure.
8. The three-dimensional memory of claim 7, further comprising:
a second passivation layer on the planar layer;
and the protective layer is positioned on the second passivation layer.
9. The three-dimensional memory of claim 1, wherein:
the wafer structure further comprises a memory cell array;
the memory cell array comprises a plurality of gate layers and a plurality of channel structures;
the channel structure includes a charge storage layer and a channel layer.
10. The three-dimensional memory of claim 9, further comprising:
a peripheral circuit;
the peripheral circuit is connected with the memory cell array through a bonding layer;
the peripheral circuit and the functional layer are respectively positioned at two sides of the memory cell array.
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