CN112185969B

CN112185969B - Three-dimensional memory structure and preparation method thereof

Info

Publication number: CN112185969B
Application number: CN202011058911.1A
Authority: CN
Inventors: 张坤; 吴林春; 周文犀; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2021-08-13
Anticipated expiration: 2040-09-30
Also published as: CN112185969A

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate; forming a zero-layer groove on the upper surface of a semiconductor substrate; forming a polysilicon sacrificial layer and filling the zero layer groove; forming a stacking structure and a channel structure on the polysilicon sacrificial layer; forming a grid gap groove in the stacked structure by dry etching, wherein the dry etching is stopped on the polysilicon sacrificial layer; removing the polysilicon sacrificial layer and forming a polishing stop material layer; forming a grid line gap structure and an upper layer metal connecting structure; polishing the lower surface of the semiconductor substrate with the polishing stop material layer as a polishing stop layer. According to the invention, the zero-layer groove is filled with the polysilicon sacrificial layer as an etching stop layer during etching of the grid line gap groove, so that the bottom semiconductor substrate is prevented from being damaged in different areas due to different film layer structures; the grinding stop material layer in the zero-layer groove can also serve as a grinding stop layer when the wafer is thinned, and the thinning uniformity is improved.

Description

Three-dimensional memory structure and preparation method thereof

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a three-dimensional memory structure and a preparation method thereof.

Background

The 3D NAND memory has a three-dimensional stacked structure and has a higher storage density per unit area than a two-dimensional memory device, and thus is a development direction of the memory generally seen in the industry.

At present, in the manufacturing process of a 3D NAND memory, with the continuous increase of the number of layers of a three-dimensional structure, the etching nonuniformity of a grid line groove of a device in different film layer areas tends to be more obvious, which will affect the appearance structure of the device after etching in different areas, and even damage a semiconductor substrate at the bottom in areas with serious over-etching, such as a step area, and further affect the subsequent process and the performance of the device.

In addition, in the bonding process of the 3D NAND memory, the bonded wafer formed by the array wafer and the CMOS wafer after bonding needs to be ground and thinned by Chemical Mechanical Polishing (CMP) or other processes, so that the overall thickness of the bonded wafer meets the process requirements. However, since the conventional array wafer lacks a polishing stop layer in the film structure, the polishing amount can be controlled only by the process time, resulting in poor in-plane uniformity of the bonded wafer polishing process.

Therefore, there is a need for a new three-dimensional memory structure and a method for fabricating the same to solve the above-mentioned problems.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for fabricating the same, which are used to solve the problems of the prior art that the substrate is damaged by etching the gate line trench of the three-dimensional memory structure and the uniformity of the back grinding process is poor.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory structure, comprising the steps of:

providing a semiconductor substrate having oppositely disposed upper and lower surfaces;

forming a zero-layer groove on the upper surface of the semiconductor substrate, wherein the position of the zero-layer groove is superposed with the projection of the design position of the grid gap structure on the upper surface of the semiconductor substrate;

forming a polysilicon sacrificial layer above the semiconductor substrate, wherein the polysilicon sacrificial layer fills the zero-layer groove;

forming a stack structure over the sacrificial layer of polysilicon and forming a channel structure in the stack structure;

forming a gate line gap groove in the stacked structure by dry etching, wherein the gate line gap groove is positioned above the zero-layer groove, and the dry etching process is stopped on the polycrystalline silicon sacrificial layer in the zero-layer groove;

removing the polysilicon sacrificial layer in the zero-layer groove and forming a grinding stop material layer in the zero-layer groove;

filling the grid line gap groove to form a grid line gap structure and forming an upper layer metal connecting structure;

and polishing the lower surface of the semiconductor substrate by using the polishing stop material layer as a polishing stop layer.

As an alternative of the present invention, a wafer on which the semiconductor substrate is located is defined as an array wafer, and before the lower surface of the semiconductor substrate is polished, a step of forming a bonding structure on the upper surface of the array wafer and bonding the array wafer and a CMOS wafer is further included.

As an alternative of the present invention, the method further includes the step of forming an electrical connection structure on the surface of the array wafer and the surface of the CMOS wafer after polishing the lower surface of the semiconductor substrate.

As an alternative of the present invention, the electrical connection structure includes a pad structure formed on the surface of the array wafer or the surface of the CMOS wafer.

As an alternative of the present invention, when removing the sacrificial polysilicon layer in the zero-layer trench, the method further comprises removing the sacrificial polysilicon layer except for other areas above the zero-layer trench and forming a polysilicon device layer.

As an alternative of the invention, the layer of polishing stop material comprises a layer of silicon dioxide.

As an alternative of the present invention, a void is formed in the polishing stop material layer.

As an alternative of the present invention, the stacked structure is formed by alternately stacking gate sacrificial layers and isolation layers; and after the grid line gap groove is formed in the stacked structure through dry etching, the method also comprises the steps of removing the grid sacrificial layer and forming a grid layer in situ of the grid sacrificial layer.

The present invention also provides a three-dimensional memory structure, comprising:

a semiconductor substrate having an upper surface and a lower surface disposed opposite to each other;

a polishing stop material layer formed in the semiconductor substrate; the position of the grinding stopping material layer is superposed with the projection of the design position of the grid gap structure on the upper surface of the semiconductor substrate; the polishing stop material layer includes a first surface exposed to an upper surface of the semiconductor substrate and a second surface exposed to a lower surface of the semiconductor substrate; the second surface is flush with the lower surface of the semiconductor substrate;

a stack structure formed on one side of an upper surface of the semiconductor substrate and composed of gate layers and isolation layers alternately stacked;

a channel structure formed in the stack structure;

a gate line gap structure formed in the stacked structure and connected to the first surface of the polish stop material layer.

As an alternative of the present invention, the stacked structure further includes a polysilicon device layer located at a side of the stacked structure close to the semiconductor substrate.

As an alternative of the present invention, the wafer on which the semiconductor substrate is located is defined as an array wafer, and the three-dimensional memory structure further includes a CMOS wafer bonded to the array wafer.

As an alternative of the invention, the array wafer and the CMOS wafer are formed with electrical connection structures on the surfaces.

As described above, the present invention provides a three-dimensional memory structure and a method for manufacturing the same, which have the following advantages:

according to the invention, the zero-layer groove is formed on the semiconductor substrate, and the polycrystalline silicon sacrificial layer filled in the zero-layer groove is used as the bottom etching stop layer during the etching of the grid-gap groove, so that the bottom semiconductor substrate is prevented from being damaged in different areas due to different film layer structures; the polishing stop material layer formed in the zero-layer groove can also be used as a polishing stop layer when the back surface of the wafer is thinned so as to improve the uniformity of back surface thinning.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a three-dimensional memory structure according to a first embodiment of the invention.

Fig. 2 to fig. 3 are schematic cross-sectional views illustrating steps of a method for fabricating a three-dimensional memory structure according to a first embodiment of the invention.

FIG. 4 is a schematic top view of a portion of a design layout of a three-dimensional memory according to an embodiment of the invention.

Fig. 5 to 17 are schematic cross-sectional views illustrating steps of a method for fabricating a three-dimensional memory structure according to a first embodiment of the invention.

Description of the element reference numerals

1 array wafer

100 semiconductor substrate

100a well region

101 zero layer trench

101a gap

102 grid line gap structure

102a gate gap trench

103 polysilicon sacrificial layer

104 channel structure

104a channel gate dielectric layer

104b channel conductive layer

104c channel insulating layer

105 core region

106 step area

107 gate layer

107a gate sacrificial layer

108 isolation layer

109 dielectric barrier layer

110 dielectric filling layer

111 dielectric cover layer

112 polysilicon device layer

113 silicon dioxide layer

114 conductive pillar structure

115 contact hole structure

116 bonded structure

117 welding pad structure

118 first conductive structure

119 second conductive structure

2 CMOS wafer

216 bonding structure

S1-S8 Steps 1) -8)

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 17. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

Referring to fig. 1 to 17, the present embodiment provides a method for manufacturing a three-dimensional memory structure, which is characterized in that: the method comprises the following steps:

1) providing a semiconductor substrate 100 having oppositely disposed upper and lower surfaces;

2) forming a zero-layer groove 101 on the upper surface of the semiconductor substrate 100, wherein the position of the zero-layer groove 101 is superposed with the projection of the designed position of the gate gap structure 102 on the upper surface of the semiconductor substrate 100;

3) forming a polysilicon sacrificial layer 103 over the semiconductor substrate 100, the polysilicon sacrificial layer 103 filling the zero layer trench 101;

4) forming a stack structure over the sacrificial layer of polysilicon 103 and forming a channel structure 104 in the stack structure;

5) forming a gate-gap trench 102a in the stacked structure by dry etching, wherein the gate-gap trench 102a is located above the zero-layer trench 101, and the dry etching process is stopped on the polysilicon sacrificial layer 103 in the zero-layer trench 101;

6) removing the sacrificial layer 103 of polysilicon in the zero layer trench 101 and forming a layer of polish stop material in the zero layer trench 101;

7) filling the gate gap trench 102a to form a gate gap structure 102 and forming an upper metal connection structure;

8) the lower surface of the semiconductor substrate 100 is polished with the polishing stop material layer as a polishing stop layer.

In step 1), referring to step S1 of fig. 1 and fig. 2, a semiconductor substrate 100 having an upper surface and a lower surface disposed opposite to each other is provided. In fig. 2, the upper side of the semiconductor substrate 100 is the upper surface thereof, and the lower side thereof is the lower surface thereof. Alternatively, the semiconductor substrate 100 includes a silicon substrate. The upper region of the semiconductor substrate 100 is also formed with a doped well region 100 a. When the semiconductor substrate 100 is a P-type silicon substrate, the well region 100a is doped N-type. The well region 100a is formed by furnace diffusion or ion implantation. Alternatively, an oxide layer may be formed on the semiconductor substrate 100 before ion implantation to control channeling during ion implantation, which is not shown in fig. 2.

In step 2), please refer to step S2 of fig. 1 and fig. 3 to 4, a zero-layer trench 101 is formed on the upper surface of the semiconductor substrate 100, and the position of the zero-layer trench 101 coincides with the projection of the designed position of the gate gap structure 102 on the upper surface of the semiconductor substrate 100. As shown in fig. 3, in the present embodiment, the zero-layer trench 101 is formed by photolithography and dry etching, and the bottom thereof is substantially flush with the bottom of the well region 100 a. Fig. 4 is a schematic top view of a part of a design layout of the three-dimensional memory structure in this embodiment. In fig. 4, the three-dimensional memory structure is divided into a core region 105 and a step region 106 in a top plane, and the gate-line-gap structure 102 penetrates through the core region 105 and the step region 106 from a longitudinal direction. The zero-layer trench 101 is formed at the position of the gate line gap structure 102 in fig. 4. Optionally, after the zero-layer trench 101 is formed, a step of forming an oxide layer on the surface of the semiconductor substrate 100 and in the zero-layer trench 101 by a thermal oxidation process is further included, where the oxide layer may serve as a stop layer for a subsequent polysilicon wet etching, and the oxide layer is not shown in fig. 4.

In step 3), referring to step S3 of fig. 1 and fig. 5, a sacrificial polysilicon layer 103 is formed over the semiconductor substrate 100, the sacrificial polysilicon layer 103 filling the zero layer trench 101. In the present embodiment, as shown in fig. 5, the sacrificial polysilicon layer 103 not only fills the zero-layer trench 101, but also covers other areas above the semiconductor substrate 100. Specifically, the sacrificial layer 103 of polysilicon is formed by a Chemical Vapor Deposition (CVD) process of polysilicon, and the upper surface is polished and planarized by Chemical Mechanical Polishing (CMP).

In step 4), referring to step S4 of fig. 1 and fig. 6-8, a stack structure is formed over the sacrificial polysilicon layer 103 and a channel structure 104 is formed in the stack structure. As shown in fig. 6, the stacked structure is formed by alternately stacking a gate sacrificial layer 107a and an isolation layer 108, wherein the gate sacrificial layer 107a may be a silicon nitride layer, and the isolation layer 108 may be a silicon dioxide layer. As shown in fig. 7, the stepped region 106 is formed in the left region in fig. 7 and the right region is the core region 105 by a multi-step dry etching of trimming photoresist. A dielectric isolation layer 109 and a dielectric filling layer 110 are covered on the step region 106. As shown in fig. 8, a channel structure 104 is formed in the stacked structure. Specifically, the channel structure 104 is, in order from outside to inside: a channel gate dielectric layer 104a, a channel conductive layer 104b, and a channel insulating layer 104 c. A dielectric cap layer 111 is also formed over the entire area.

In step 5), referring to step S5 of fig. 1 and fig. 9, a gate gap trench 102a is formed in the stacked structure by dry etching, the gate gap trench 102a is located above the zero layer trench 101, and the dry etching process is stopped on the polysilicon sacrificial layer 103 in the zero layer trench 101. After the gate-gap trench 102a is formed, a dielectric protection layer is further formed on the sidewall thereof to protect the stacked structure from being etched in the subsequent wet etching process of the dielectric layer. In the dry etching process of the gate gap trench in this step, the thickness of the polysilicon sacrificial layer 103 as an etching stop layer is increased due to the zero-layer trench 101 at the bottom, thereby increasing the etching process window. For example, at the position of the step region, etc., the etching will reach the upper part of the semiconductor substrate 100 before the core region due to the lower number of layers of the upper stacked structure compared with the core region. Generally, when the dry etching is directly applied to a semiconductor substrate, a substrate damage (plasma Damage) is often generated under the action of plasma, and the generated damaged layer is very likely to cause formation of lattice defects such as dislocation, thereby causing adverse effects on the performance of devices such as leakage. According to the invention, the zero-layer groove 101 filled with the polysilicon sacrificial layer 103 is introduced, so that the etching of the area is stopped on the polysilicon sacrificial layer 103, the damage to the semiconductor substrate 100 caused by dry etching is prevented, and the performance of the device is not influenced.

In step 6), referring to step S6 of fig. 1 and fig. 10 to 12, the sacrificial polysilicon layer 103 in the zero-layer trench 101 is removed, and a polishing stop material layer comprising a silicon dioxide layer is formed in the zero-layer trench. Optionally, this step further comprises the steps of removing the sacrificial polysilicon layer 103 except other areas above the zero-layer trench 101 and forming a polysilicon device layer 112, and removing the sacrificial gate layer 107a and forming a gate layer 107 in situ on the sacrificial gate layer 107 a.

As shown in fig. 10, the polysilicon sacrificial layer 103 is removed by a wet etching process or an isotropic dry etching process of polysilicon. And then, continuously removing a part of the channel gate dielectric layer 104a exposed below the channel structure 104 by a wet etching process, wherein in the process, a dielectric protection layer formed on the sidewall of the gate line gap trench 102a in fig. 9 can protect the stacked structure from being affected by etching, and is removed after the wet etching process, so that the structure shown in fig. 10 is finally obtained.

As shown in fig. 11, a polysilicon device layer 112 is formed in the void formed after the removal of the gate sacrificial layer 103 of fig. 10, and the gate sacrificial layer 107a made of a silicon nitride material is removed by a silicon nitride wet etching process.

As shown in fig. 12, a gate layer 107 is formed in situ on the gate sacrificial layer 107a, and the zero-layer trench 101 and the gate line gap trench 102a are filled with a silicon dioxide material to form a silicon dioxide layer 113. Alternatively, the gate layer 107 includes a composite layer structure composed of an AlO layer, a TiN layer, and a tungsten metal layer. The silicon dioxide layer in the zero-layer trench 101 constitutes the polishing stop material layer. The polishing stop material layer also has a void 101a formed therein and constituted by a region not filled with a silicon dioxide material. The void 101a is located in the central region of the zero-layer trench 101, and can play a role in relieving stress. Particularly when the silicon dioxide layer in the zero-layer trench 101 is used as a polishing stop layer in a CMP process, the void 101a can effectively release stress generated during polishing, and prevent a device structure from being cracked and damaged due to the stress. The gap 101a can be naturally formed by adjusting the hole filling capability when a silicon dioxide layer is grown by chemical vapor deposition, and the shape and size of the gap can also be adjusted by adjusting the process parameters of the chemical vapor deposition and the shape of the groove to be filled. In addition, although not shown in fig. 12, in other embodiments of the present invention, a void extending in a vertical direction may be formed in the gate line gap trench 102 a.

In step 7), referring to step S7 of fig. 1 and fig. 12 to 13, the gate line gap trench 102a is filled to form a gate line gap structure 102, and an upper metal connection structure is formed.

As shown in fig. 12, in step 6), the silicon dioxide layer 113 fills not only the zero-layer trench 101 but also the gate-gap trench 102 a. That is, in the present embodiment, the gate gap structure 102 is also made of a silicon dioxide material. In other embodiments of the present invention, other device structures such as an array common source structure may be further formed in the gate line gap structure 102, and the gate line gap structure 102 and the polishing stop material layer may be formed in different process steps.

As shown in fig. 13, an upper metal connection structure is further formed. Optionally, the upper metal connection structure includes a conductive pillar structure 114 and a contact hole structure 115. The conductive pillar structure 114 is connected to the substrate source or the gate layer 107, and the contact hole structure 115 is connected to the conductive pillar structure 114 or the channel structure 104, so as to electrically lead the conductive pillar structure to the upper surface of the wafer. A bonding structure 116 is further formed above the contact hole structure 115.

As an example, as shown in fig. 13 to 14, the wafer on which the semiconductor substrate is located is defined as an array wafer, that is, the structure shown in fig. 13 is a part of the array wafer. In fig. 14, the array wafer 1 is inverted and bonded to the underlying CMOS wafer 2. Specifically, the CMOS wafer 2 has formed therein a CMOS device and a bonding structure 216 on the upper surface, and the bonding structures of the array wafer 1 and the CMOS wafer 2 are aligned and bonded to obtain the bonding wafer in fig. 14.

In step 8), referring to step S8 of fig. 1 and fig. 14 to 15, the lower surface of the semiconductor substrate 100 is polished by using the polishing stop material layer as a polishing stop layer. In fig. 14, since the wafer on which the semiconductor substrate 100 is located is turned upside down, the lower surface of the semiconductor substrate 100 is the surface exposed to the surface of the bonded wafer, which may be referred to as the back surface of the semiconductor substrate 100, and this step is the back grinding of the semiconductor substrate 100. In this embodiment, the polishing stop material layer includes a silicon dioxide layer. The back surface of the semiconductor substrate 100 is also required to be thinned by a grinding process such as CMP, so that the thickness of the bonded wafer meets the specification requirement. As shown in fig. 15, the polishing process is stopped at the position of the zero-layer trench 101, and for the silicon material polishing process such as a silicon substrate, an End Point Detection (EPD) of the polishing process can be performed by using a heterogeneous silicon dioxide material layer as a polishing end point, so that the polishing process is accurately stopped at the position of the zero-layer trench 101, thereby avoiding the process method of setting the polishing amount according to the process time in the prior art, improving the uniformity of the polishing process in the wafer plane, increasing the process window of the polishing process, and making the polishing process not easily affected by the thickness fluctuation of the substrates in different batches.

As an example, as shown in fig. 16, the surface of the array wafer 1 is further formed with an electrical connection structure, the electrical connection structure includes a pad structure 117(pad), and the pad structure 117 is used as a signal input/output terminal of the three-dimensional memory and is electrically connected to the inside of the memory through a first conductive structure 118. The electrical connection structure further includes a second conductive structure 119 serving as a metal wiring structure to further electrically connect the conductive structures led out from the array wafer 1, and a passivation dielectric layer playing a role in protection is further covered above the second conductive structure 119.

As an example, as shown in fig. 17, another arrangement of the pad structure 117 is shown. In comparison with fig. 16, in fig. 17, the bonding pad structure 117 is disposed on one side of the CMOS wafer 2, and the second conductive structure 119 is still disposed on one side of the array wafer 1.

In the embodiment, by introducing the zero-layer groove structure in the preparation process of the three-dimensional memory device, the polysilicon sacrificial layer filled in the zero-layer groove structure can be used as an etching stop layer during etching of the grid-gap groove, so that the substrate damage caused by over-etching in areas such as a step area is prevented; after the grinding stop material layer is formed in the zero-layer groove structure, the grinding stop material layer can be used as a grinding stop layer during back grinding of the semiconductor substrate, and uniformity of a grinding process in a wafer surface is improved. In addition, compared with the prior art, the invention only needs to add a photoetching/etching process for introducing the zero-layer groove without adding other additional processes, has better compatibility with the prior process, and has the obvious advantages of simple and convenient implementation and low process cost.

Example two

Referring to fig. 4 and 14 to 17, the present embodiment provides a three-dimensional memory structure, which is characterized in that: the method comprises the following steps:

a semiconductor substrate 100 having an upper surface and a lower surface disposed oppositely;

a polishing stop material layer formed in the semiconductor substrate 100; the position of the grinding stop material layer is superposed with the projection of the design position of the grid gap structure 102 on the upper surface of the semiconductor substrate 100; the polishing stop material layer includes a first surface exposed to the upper surface of the semiconductor substrate 100 and a second surface exposed to the lower surface of the semiconductor substrate 100; the second surface is flush with the lower surface of the semiconductor substrate 100;

a stack structure formed on the upper surface side of the semiconductor substrate 100 and composed of gate layers 107 and isolation layers 108 alternately stacked;

a channel structure 104 formed in the stacked structure;

a gate line gap structure 102 formed in the stacked structure and connecting the first surface of the polish stop material layer.

As shown in fig. 4, the position of the zero-layer trench 101 in this embodiment coincides with the projection of the designed position of the gate line gap structure 102 on the upper surface of the semiconductor substrate 100, and fig. 4 shows that the three-dimensional memory structure is divided into a core region 105 and a step region 106 in a top plane, the gate line gap structure 102 penetrates through the core region 105 and the step region 106 from the longitudinal direction, and the zero-layer trench 101 in this embodiment is located in the semiconductor substrate at the designed position of the gate line gap structure 102.

As shown in fig. 14, the polishing stop material layer is formed by filling the zero-layer trench 101 with a polishing stop material. In this embodiment, the polishing stop material layer includes a silicon dioxide layer. Fig. 14 shows a schematic cross-sectional view of the semiconductor substrate 100 without backside thinning. In fig. 14, since the wafer on which the semiconductor substrate 100 is located is turned upside down, the lower surface of the semiconductor substrate 100 is the surface exposed to the surface of the bonded wafer, which may be referred to as the back surface of the semiconductor substrate 100, and this step is the back grinding of the semiconductor substrate 100.

Fig. 15 is a schematic cross-sectional view after performing backside thinning, where the silicon dioxide layer is used as a polishing stop material layer when performing backside thinning on the semiconductor substrate 100, and specific process steps and technical effects thereof can be described with reference to relevant portions of the first embodiment. The polishing stop material layer also has a void 101a formed therein.

As an example, as shown in fig. 16 to 17, a wafer on which the semiconductor substrate 100 is located is defined as an array wafer 1, and the three-dimensional memory structure further includes a CMOS wafer 2 bonded to the array wafer.

As shown in fig. 16, an electrical connection structure is formed on the surfaces of the array wafer 1 and the CMOS wafer 2. The electrical connection structure includes a pad structure 117(pad), and the pad structure 117 is used as a signal input/output terminal of the memory and is electrically connected to the inside of the memory through the first conductive structure 118. The electrical connection structure further includes a second conductive structure 119 serving as a metal wiring structure for further electrically connecting the conductive structures led out from the array wafer 1. A dielectric protection layer covers the second conductive structure 119.

As shown in fig. 17, another arrangement of the pad structure 117 is shown. In comparison with fig. 16, in fig. 17, the pad structure 117 is disposed on one side of the CMOS wafer 2, and the second conductive structure 119 is still disposed on one side of the array wafer 1.

In summary, the present invention provides a three-dimensional memory structure and a method for fabricating the same, wherein the method comprises the following steps: providing a semiconductor substrate having oppositely disposed upper and lower surfaces; forming a zero-layer groove on the upper surface of the semiconductor substrate, wherein the position of the zero-layer groove is superposed with the projection of the design position of the grid gap structure on the upper surface of the semiconductor substrate; forming a polysilicon sacrificial layer above the semiconductor substrate, wherein the polysilicon sacrificial layer fills the zero-layer groove; forming a stack structure over the sacrificial layer of polysilicon and forming a channel structure in the stack structure; forming a gate line gap groove in the stacked structure by dry etching, wherein the gate line gap groove is positioned above the zero-layer groove, and the dry etching process is stopped on the polycrystalline silicon sacrificial layer in the zero-layer groove; removing the polysilicon sacrificial layer in the zero-layer groove and forming a grinding stop material layer in the zero-layer groove; filling the grid line gap groove to form a grid line gap structure and forming an upper layer metal connecting structure; and polishing the lower surface of the semiconductor substrate by using the polishing stop material layer as a polishing stop layer. According to the invention, the zero-layer groove is formed on the semiconductor substrate, and the polycrystalline silicon sacrificial layer filled in the zero-layer groove is used as the bottom etching stop layer during the etching of the grid-gap groove, so that the bottom semiconductor substrate is prevented from being damaged in different areas due to different film layer structures; the grinding stop material layer formed in the zero-layer groove can also be used as a grinding stop layer when the back surface of the wafer is thinned so as to improve the uniformity of back surface thinning.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a three-dimensional memory structure is characterized by comprising the following steps:

forming a gate line gap groove in the stacked structure by dry etching, wherein the gate line gap groove is positioned above the zero-layer groove, and the dry etching is stopped on the polycrystalline silicon sacrificial layer in the zero-layer groove;

2. The method of fabricating a three-dimensional memory structure of claim 1, wherein: defining the wafer where the semiconductor substrate is located as an array wafer, and before grinding the lower surface of the semiconductor substrate, forming a bonding structure on the upper surface of the array wafer, and bonding the array wafer and the CMOS wafer.

3. The method of fabricating a three-dimensional memory structure of claim 2, wherein: and after the lower surface of the semiconductor substrate is ground, the method also comprises the step of forming an electrical connection structure on the surfaces of the array wafer and the CMOS wafer.

4. The method of fabricating a three-dimensional memory structure according to claim 3, wherein: the electrical connection structure comprises a welding pad structure formed on the surface of the array wafer or the surface of the CMOS wafer.

5. The method of fabricating a three-dimensional memory structure of claim 1, wherein: when the sacrificial polysilicon layer in the zero-layer trench is removed, the method further comprises the step of removing the sacrificial polysilicon layer except for the other area above the zero-layer trench and forming a polysilicon device layer.

6. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the polishing stop material layer includes a silicon dioxide layer.

7. The method of fabricating a three-dimensional memory structure of claim 1, wherein: a gap is formed in the polishing stop material layer.

8. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the stacked structure is formed by alternately stacking grid sacrificial layers and isolating layers; and after the grid line gap groove is formed in the stacked structure through dry etching, the method also comprises the steps of removing the grid sacrificial layer and forming a grid layer in situ of the grid sacrificial layer.

9. A three-dimensional memory structure, comprising:

a channel structure formed in the stack structure;

10. The three-dimensional memory structure of claim 9, wherein: the stacked structure further includes a polysilicon device layer located at a side of the stacked structure near the semiconductor substrate.

11. The three-dimensional memory structure of claim 9, wherein: a gap is formed in the polishing stop material layer.

12. The three-dimensional memory structure of claim 9, wherein: the polishing stop material layer includes a silicon dioxide layer.

13. The three-dimensional memory structure of claim 9, wherein: and defining the wafer on which the semiconductor substrate is positioned as an array wafer, wherein the three-dimensional memory structure further comprises a CMOS wafer bonded with the array wafer.

14. The three-dimensional memory structure of claim 13, wherein: and an electrical connection structure is formed on the surfaces of the array wafer and the CMOS wafer.

15. The three-dimensional memory structure of claim 14, wherein: the electrical connection structure comprises a welding pad structure formed on the surface of the array wafer or the surface of the CMOS wafer.