CN112614849B

CN112614849B - Three-dimensional memory structure and preparation method thereof

Info

Publication number: CN112614849B
Application number: CN202011466325.0A
Authority: CN
Inventors: 张坤
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2023-11-03
Anticipated expiration: 2040-12-14
Also published as: CN112614849A

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate; a groove is formed in the core area; forming a sacrificial layer and a first semiconductor layer in the recess; forming a stacked structure over the semiconductor substrate and the first semiconductor layer, and forming a channel structure; forming a gate line gap groove penetrating through the stacked structure, wherein a part of the gate line gap groove in the core region penetrates through the stacked structure to the sacrificial layer; removing the sacrificial layer and the isolation dielectric layer, and filling the second semiconductor layer; and forming a gate line gap structure in the gate line gap groove. According to the invention, the grooves with the sacrificial layers, the isolation medium layers and the first semiconductor layers are formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap grooves of the stacked structure, the etching damage defect caused by the too high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

Description

Three-dimensional memory structure and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a three-dimensional memory structure and a method for fabricating the same.

Background

The 3D NAND memory has a higher storage density per unit area than a general two-dimensional memory device due to its three-dimensional stacked structure, and is a very innovative main development direction of the memory.

At present, in the process of the 3D NAND memory, the number of layers of the device stacking structure is continuously increased based on the requirement of improving the performance of the device, which provides new challenges for the etching process of the structures such as the gate line gap groove or the channel hole penetrating through the stacking structure, and particularly, the etching non-uniformity of the areas with different film structures such as the core area and the step area tends to be more remarkable. In order to prevent the device structure from being damaged by over etching caused by the non-uniformity of etching, processes such as etching and the like need to be debugged and film structures in different areas are adjusted in a targeted manner.

However, in the existing 3D NAND memory process, the device structure defect caused by the etching non-uniformity cannot be overcome by adjusting the etching process and the film structure. For example, when the gate line gap trench is etched, the core region is mainly composed of alternately stacked silicon nitride layers and silicon oxide layers, and the silicon oxide layers occupy a larger proportion in the step region, which results in a faster etching rate of the core region in the same etching process. When the step region is still being etched, the etching process of the core region has reached the bottom stop layer, and excessive over-etching will damage the bottom substrate, affecting the device performance.

Therefore, there is a need to propose a new three-dimensional memory structure and a method for manufacturing the same, which solve the above-mentioned problems.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for manufacturing the same, which are used for solving the problem of poor uniformity of etching of gate line gap trenches of the three-dimensional memory structure in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory structure, comprising the steps of:

providing a semiconductor substrate with a groove, defining a core region and a step region in the semiconductor substrate, wherein the groove is positioned in the core region;

forming a sacrificial layer and a first semiconductor layer in the groove in sequence;

forming a stacked structure over the semiconductor substrate and the first semiconductor layer, forming a channel structure in the core region through the stacked structure into the semiconductor substrate; the stacking structure is provided with a step structure in the step area;

forming a gate line gap groove penetrating through the stacked structure, wherein the gate line gap groove penetrates through the stacked structure to the sacrificial layer at the part of the core region;

removing the sacrificial layer and filling the second semiconductor layer;

and forming a grid line gap structure in the grid line gap groove.

As an alternative of the present invention, the method of sequentially forming the sacrificial layer and the first semiconductor layer in the recess includes the steps of:

sequentially depositing the sacrificial layer and the first semiconductor layer over the semiconductor substrate;

and removing the sacrificial layer and the first semiconductor layer in other areas except the grooves on the semiconductor substrate.

As an alternative of the present invention, an isolation dielectric layer is further formed between the sacrificial layer and the first semiconductor layer.

As an alternative of the present invention, the isolation medium layer includes a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer comprises a polysilicon layer; the first semiconductor layer and the second semiconductor layer include doped polysilicon layers.

As an alternative scheme of the invention, after the gate line gap groove is formed, the method further comprises the steps of forming a side wall dielectric layer on the side wall of the gate line gap groove and removing the isolation dielectric layer at the bottom of the gate line gap groove.

As an alternative of the present invention, the method further comprises a step of forming an insulating dielectric layer on the semiconductor substrate before forming the sacrificial layer; and after the sacrificial layer is removed, the method further comprises the step of removing the isolation dielectric layer and the insulation dielectric layer.

As an alternative of the present invention, the gate line gap trench penetrates the stacked structure to the semiconductor substrate at a portion of the step region.

As an alternative of the present invention, the junction between the core region and the step region is defined as a junction region; before forming the grid line gap groove in the stacking structure, the method further comprises the step of forming a dummy channel structure in the interface area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

As an alternative of the present invention, the stacked structure is formed by alternately stacking gate sacrificial layers and isolation layers; and after the grid line gap groove is formed in the stacked structure, removing the grid sacrificial layer and forming a grid layer.

As an alternative of the present invention, after the gate line gap structure is formed in the gate line gap trench, a step of forming a metal connection structure is further included.

As an alternative of the present invention, the wafer on which the semiconductor substrate is located is defined as an array wafer, and after the metal connection structure is formed, the method further includes: providing a control wafer and bonding the array wafer and the control wafer through a bonding structure.

As an alternative of the present invention, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, wherein the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned at one side far away from the array wafer compared with the third surface; after the array wafer is bonded with the control wafer, the method further comprises the step of forming an electrical connection structure on the second surface and/or the fourth surface.

The invention also provides a three-dimensional memory structure, which is characterized by comprising:

a semiconductor substrate with a groove, wherein a core area and a step area are defined in the semiconductor substrate, the groove is positioned in the core area, and a second semiconductor layer and a first semiconductor layer are sequentially filled in the groove;

a stacked structure provided on the semiconductor substrate and the first semiconductor layer, including gate layers and isolation layers alternately stacked; the stacking structure is provided with a step structure in the step area;

a channel structure penetrating through the stacked structure, the first semiconductor layer, and the second semiconductor layer into the semiconductor substrate;

and the part of the grid line gap structure, which is positioned in the core region, penetrates through the stacked structure and the first semiconductor layer and contacts the second semiconductor layer.

As an alternative of the present invention, the first semiconductor layer and the second semiconductor layer comprise doped polysilicon layers.

As an alternative of the present invention, a dummy channel structure is further formed at an interface region of the core region and the step region; the dummy channel structure extends through the stack structure into the semiconductor substrate.

As an alternative of the present invention, the three-dimensional memory structure further comprises a metal connection structure.

As an alternative of the present invention, the wafer on which the semiconductor substrate is located is defined as an array wafer, and the three-dimensional memory structure further includes a control wafer bonded to the array wafer.

As an alternative of the present invention, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, wherein the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned at one side far away from the array wafer compared with the third surface; the second surface and/or the fourth surface are/is formed with an electrical connection structure

As an alternative of the present invention, the electrical connection structure includes a pad structure and a metal connection layer, where the pad structure and the metal connection layer are formed on the second surface and/or the fourth surface, and the metal connection layer is electrically connected to the semiconductor substrate.

As an alternative of the present invention, the electrical connection structure includes a pad structure, the pad structure is formed on the second surface and/or the fourth surface, and the semiconductor substrate is electrically led out through a conductive pillar structure disposed on one side of the first surface.

As described above, the invention provides a three-dimensional memory structure and a preparation method thereof, which have the following beneficial effects:

according to the invention, the grooves with the sacrificial layers, the isolation medium layers and the first semiconductor layers are formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap grooves of the stacked structure, the etching damage defect caused by the too high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory structure according to a first embodiment of the present invention.

FIG. 2 is a schematic top view of a three-dimensional memory design layout according to a first embodiment of the present invention.

Fig. 3 to 25 are schematic cross-sectional views illustrating steps of a method for fabricating a three-dimensional memory structure according to a first embodiment of the present invention.

Fig. 26 is a schematic cross-sectional view of a three-dimensional memory structure according to a second embodiment of the present invention.

Fig. 27 is a schematic cross-sectional view showing a three-dimensional memory structure provided in a third embodiment of the present invention.

Fig. 28 is a schematic cross-sectional view showing a three-dimensional memory structure provided in a fourth embodiment of the present invention.

Description of element reference numerals

1. Array wafer

100. Semiconductor substrate

100a core region

100b step area

100c well region

100d oxide layer

100e first backside via

100f second backside via

101. Groove

102. Sacrificial layer

103. Isolation dielectric layer

104. First semiconductor layer

105. Channel structure

105a channel gate dielectric layer

105b channel conductive layer

105c channel insulating layer

105d dummy channel structure

106. Grid line gap structure

106a gate line clearance trench

106b dielectric protective layer

107. Second semiconductor layer

108. Gate layer

108a gate sacrificial layer

109. Isolation layer

110. Dielectric barrier layer

111. Dielectric filling layer

112. Dielectric cover layer

113. Conductive column structure

114. Contact hole structure

115. Bonding structure

116. Backside dielectric layer

117. Dielectric layer

118. Backside metal layer

119. Metal connecting layer

120. Passivation layer

2. Control wafer

215. Bonding structure

305. Channel structure

307. Second semiconductor layer

313. Conductive column structure

319. Metal connecting layer

320. Passivation layer

419. Metal connecting layer

420. Passivation layer

519. Metal connecting layer

520. Passivation layer

605. Channel structure

607. Second semiconductor layer

613. Conductive column structure

619. Metal connecting layer

620. Passivation layer

S1-S6 Steps 1) -6)

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 28. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

Referring to fig. 1 to 25, the present embodiment provides a method for manufacturing a three-dimensional memory structure, which is characterized in that: the method comprises the following steps:

1) Providing a semiconductor substrate 100 with a groove 101, defining a core region 100a and a step region 100b in the semiconductor substrate 100, wherein the groove 101 is positioned in the core region 100a;

2) A sacrificial layer 102 and a first semiconductor layer 104 are sequentially formed in the recess 101;

3) Forming a stacked structure over the semiconductor substrate 100 and the first semiconductor layer 104, forming a channel structure 105 in the core region 100a penetrating the stacked structure into the semiconductor substrate 100; the stacking structure is provided with a step structure in the step area;

4) Forming a gate line gap trench 106a penetrating through the stacked structure, the gate line gap trench 106a penetrating through the stacked structure to the sacrificial layer 102 at a portion of the core region 100a;

5) Removing the sacrificial layer 102 and filling the second semiconductor layer 107;

6) A gate line gap structure 106 is formed in the gate line gap trench 106 a.

In step 1), referring to step S1 of fig. 1 and fig. 2 to 5, a semiconductor substrate 100 having a recess 101 is provided, a core region 100a and a step region 100b are defined in the semiconductor substrate 100, and the recess 101 is located in the core region 100a. As shown in fig. 2, a partial top view of the design layout of the three-dimensional memory structure provided in this embodiment is shown, where the three-dimensional memory structure is divided into a core region 100a and the step regions 100b located at two sides thereof, the channel structures 105 are distributed in the core region 100a, and the gate line gap structures 106 penetrate through the stacked structures of the core region 100a and the step regions 100b. Fig. 3 is a cross-sectional view of the semiconductor substrate 100, wherein the core region 100a is on the left side and the step region 100b is on the right side in fig. 3. Alternatively, the semiconductor substrate 100 includes a silicon substrate. The upper region of the semiconductor substrate 100 is further formed with a doped well region 100c. When the semiconductor substrate 100 is a P-type silicon substrate, the well region 100c is doped N-type. The well region 100c is formed by furnace tube diffusion or ion implantation. Optionally, an oxide layer 100d may be formed on the semiconductor substrate 100 before ion implantation to control channeling during ion implantation. As shown in fig. 3 to 4, the recess 101 is formed on the semiconductor substrate 100, and its coverage area coincides with the core region 100a, i.e., the recess 101 is formed on the semiconductor substrate 100 in the range of the core region 100a. The recess 101 may be formed by photolithography and dry etching. Optionally, the step region 100b is covered by a photoresist etching mask, and in the core region 100a, the oxide layer 100d in this region is removed by dry etching, and a portion of the doped well region 100c is further etched away to form the recess 101. Optionally, as shown in fig. 5, after forming the recess 101, a step of forming an oxide layer in the recess 101 by a thermal oxidation process is further included. The thermal oxidation process forms an oxide layer only on the silicon material of the semiconductor substrate 100, which newly formed oxide layer will be in one piece with the original oxide layer 100d, which in this embodiment is defined as an insulating dielectric layer on the semiconductor substrate 100. Alternatively, the insulating dielectric layer may be formed of other material layers besides oxide layers.

In step 2), referring to step S2 of fig. 1 and fig. 5 to 7, a sacrificial layer 102 and a first semiconductor layer 104 are sequentially formed in the recess 101.

Optionally, an isolation dielectric layer 103 is further formed between the sacrificial layer 102 and the first semiconductor layer 104.

Alternatively, as shown in fig. 5 to 7, the method of sequentially forming the sacrificial layer 102, the isolation dielectric layer 103, and the first semiconductor layer 104 in the recess 101 includes the steps of:

sequentially depositing the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 above the semiconductor substrate 100;

the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 are removed from the semiconductor substrate 100 in the other areas except the recess 101 by chemical mechanical polishing.

As shown in fig. 5 to 6, the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 are sequentially deposited over the semiconductor substrate 100, including in the recess 101, by a thin film deposition process such as a Chemical Vapor Deposition (CVD) process. The isolation dielectric layer 103 comprises a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer 102 comprises a polysilicon layer and the first semiconductor layer 104 comprises a doped polysilicon layer.

As shown in fig. 6 to 7, chemical Mechanical Polishing (CMP) is performed on the semiconductor substrate 100 on which the above material layers are deposited, and the oxide layer 100d on the surface of the semiconductor substrate 100 is used as a polishing stop layer, so that the sacrificial layer 102, the isolation dielectric layer 103, and the first semiconductor layer 104 remain only in the recess 101 after chemical mechanical polishing. Through the above process, the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 of the L-shape will be formed in the region of the core region 100a near the step region 100b.

In step 3), referring to step S3 of fig. 1 and fig. 8 to 10, a stacked structure is formed over the first semiconductor layer 104 of the semiconductor substrate 100, and a channel structure 105 penetrating the stacked structure into the semiconductor substrate 100 is formed in the core region 100a; the stacked structure has a step structure in the step region.

As shown in fig. 8, a stacked structure is formed over the semiconductor substrate 100, the stacked structure being composed of gate sacrificial layers 108a and isolation layers 109 alternately stacked, wherein the gate sacrificial layers 108a may be silicon nitride layers and the isolation layers 109 may be silicon dioxide layers.

As shown in fig. 9, the step structure of the step region 100b is formed in the left area in fig. 9 by a multi-step dry etching of trimming the photoresist, and the core region 100a is formed in the right area. The step structure is also covered with a dielectric isolation layer 110 and a dielectric fill layer 111.

As shown in fig. 10, a plurality of channel structures 105 are formed in the stacked structure. Specifically, the channel structure 105 is sequentially from outside to inside: a channel gate dielectric layer 105a, a channel conductive layer 105b, and a channel insulating layer 105c. A dielectric cap layer 112 is also formed over the entire area. The process of forming the channel structure 105 includes: a channel via hole is formed in the stacked structure by dry etching, and a channel gate dielectric layer 105a, a channel conductive layer 105b, and a channel insulating layer 105c are sequentially formed in the channel via hole by thin film deposition and etching.

As shown in fig. 11, in addition to forming the channel structure 105 in the stacked structure, a plurality of dummy channel structures 105d are formed in the stacked structure, and the positions of the dummy channel structures 105d are not in the cross section in the AA' direction in fig. 2, and are distributed at the interface between the core region 100a and the step region 100b, which is not shown in fig. 2. Specifically, the interface of the core region 100a and the step region 100b is defined as an interface region, and the dummy channel structure 105d is formed in the interface region. Alternatively, in the present embodiment, the interface region may include a part of the core region 100a and the step region 100b. In other embodiments of the invention, it may also include only a portion of the core region 100a, or only the step region 100b. As shown in fig. 11, a portion of the dummy channel structure 105d located in the step region 100b extends through the stacked structure of the step region 100b to the doped well region 100c. The portion of the dummy channel structure 105d located in the core region 100a extends through the stacked structure of the core region 100a, the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 to the doped well region 100c. Only a partial cross section of the semiconductor substrate 100 is shown in fig. 11. The process of forming the dummy channel structure 105d includes: a dummy channel via is first formed by dry etching and refilled with an insulating dielectric material, such as silicon dioxide, to form the dummy channel structure 105d. The dummy channel structure 105d may be distributed in a region where the gate line clearance trench 106a passes at the interface of the core region 100a and the step region 100b. By introducing the dummy channel structure 105d, non-uniformity of the gate line clearance trench etch in the core region 100a and the step region 100b may be further balanced. In addition, the introduction of the dummy channel through hole can also improve the etching uniformity of the channel through hole etching process, and the etching uniformity of the channel through hole positioned at the edge of the core region and close to the step region can be improved.

In step 4), referring to step S4 of fig. 1 and fig. 12 to 13, a gate line gap trench 106a is formed through the stacked structure, and the gate line gap trench 106a penetrates the stacked structure to the sacrificial layer 102 at a portion of the core region 100a. The gate line clearance trench 106a is located throughout the stacked structure to the semiconductor substrate 100 at a portion of the step region 100b.

It should be noted that, in this embodiment, in order to fully and clearly show the main structures such as the channel and the gate line gap in the same cross-sectional schematic diagram, the left side portion represents the cross-section in the AA 'direction in fig. 2, the right side portion represents the cross-section in the BB' direction in fig. 2, and the subsequent cross-sectional diagrams of this embodiment are identical to those of fig. 12, and will not be repeated.

In fig. 12, a gate line gap trench 106a is formed in the stacked structure by anisotropic dry etching, the gate line gap trench 106a penetrating the stacked structure and the first semiconductor layer 104, and etching stopping on the isolation dielectric layer 103. In the dry etching process, the etching gas and the process conditions can be switched correspondingly according to the material difference of different film layers reached by etching, and a higher etching selection ratio of the isolation dielectric layer 103 below is ensured in the etching process of the first semiconductor layer 104. When the dry etching directly acts on the semiconductor substrate, the substrate is often damaged (plasma damage) under the action of plasma, and the generated damaged layer is extremely easy to cause lattice defects such as dislocation and the like, so that adverse effects are caused on performances such as electric leakage of devices. Since the present embodiment introduces the film structure such as the groove 101 and the isolation dielectric layer 103 formed therein as an etching stop layer, an etching process window is increased. Even if the gate line gap trench is etched in the core region 100a and the step region 100b with different etching rates, the etching rate in the core region 100a is faster, and the gate line gap trench can also be etched and stopped on the isolation dielectric layer 103, thereby avoiding damage to the substrate structure and ensuring that the device performance is not affected.

As shown in fig. 13, after the gate line gap trench 106a is formed, a dielectric protection layer 106b is further formed on a sidewall thereof to protect the stacked structure from etching during a subsequent wet etching process for removing other dielectric layers. In this embodiment, the dielectric protection layer 106b may be a multilayer composite structure composed of a silicon nitride layer and a silicon oxide layer. Optionally, the process of forming the dielectric protection layer 106b includes: dielectric protection material layers such as a silicon dioxide layer and a silicon nitride layer are deposited on the surfaces of the gate line clearance groove 106a and the dielectric covering layer 112, and then the dielectric protection material layers on other areas except the side wall of the gate line clearance groove 106a are removed through anisotropic dry etching, so that the dielectric protection layer 106b, namely a side wall dielectric layer, is formed. As can also be seen from fig. 13, the dry etching process also simultaneously removes part of the isolation dielectric layer 103 at the bottom of the gate line gap trench 106a, the etching process stops at the sacrificial layer 102, and the isolation dielectric layer 103 in the non-removed part of the other area is defined as a residual isolation dielectric layer.

In step 5), referring to step S5 of fig. 1 and fig. 14 to 16, the sacrificial layer 102 is removed and the second semiconductor layer 107 is filled.

As shown in fig. 14, the sacrificial layer 102 is removed by isotropic wet etching. Since the sacrificial layer 102 at the bottom of the gate line clearance trench 106a has been exposed during the formation of the dielectric protection layer 106 b. The whole sacrificial layer 102 can be etched and removed from this position by using a wet etching liquid in this embodiment. The sacrificial layer 102 is a polysilicon layer, and wet etching of the polysilicon material does not damage other dielectric material layers.

As shown in fig. 15, the remaining portion of the isolation dielectric 103 (i.e., the remaining isolation dielectric defined above) is removed by wet etching, and the exposed portion of the oxide layer 100d on the semiconductor substrate 100 and the portion of the trench gate dielectric 105a of the trench structure 105 are also removed. The dielectric protection layer 106b may protect the different material layers of the stacked structure of the sidewall of the gate line clearance trench 106a from the corresponding etching during the etching process. In fig. 15, the dielectric protection layer 106b is also depleted during etching. In other embodiments of the present invention, the dielectric protection layer 106b may be removed by wet etching before the subsequent process.

As shown in fig. 16, a second semiconductor layer 107 is filled in the position originally occupied by the sacrificial layer 102, and the second semiconductor layer 107 includes a polysilicon layer. The second semiconductor layer 107 is electrically connected to the channel conductive layer 105b of the channel structure 105 after being formed. After the second semiconductor layer 107 is formed, the gate sacrificial layer 108a is also removed by wet etching.

In step 6), referring to step S6 of fig. 1 and fig. 17, a gate line gap structure 106 is formed in the gate line gap trench 106 a. In this embodiment, the gate line gap structure 102 is filled with a silicon dioxide material. Optionally, before forming the gate line gap structure 106, a gate layer 108 is also formed in the original position of the gate sacrificial layer 108a, and the gate layer 108 may be filled with a conductive material such as metal tungsten.

As shown in fig. 18, after step 6), a metal connection structure is further formed. Optionally, the metal connection structure includes a conductive pillar structure 113 and a contact hole structure 114. The conductive pillar structure 113 is connected to the semiconductor substrate 100 or to the gate layer 108 in a step structure, and the contact hole structure 114 is connected to the conductive pillar structure 113 or the channel structure 105, and electrically leads out to the upper surface of the wafer. A bonding structure 115 is further formed above the contact hole structure 114.

As an example, as shown in fig. 18 to 19, the wafer on which the semiconductor substrate 100 is located is defined as an array wafer, that is, the structure shown in fig. 18 is a part of the array wafer. In fig. 19, the array wafer 1 is inverted and bonded to the underlying control wafer 2. Specifically, the bonding structures 215 of the CMOS device and the upper surface are formed in the control wafer 2, and the bonding structures of the array wafer 1 and the control wafer 2 are aligned and bonded to obtain the bonding wafer in fig. 19.

As shown in fig. 19 to 20, the bonded wafer is thinned from the semiconductor substrate 100 side, so that the thickness of the array wafer 1 is thinned to the design specification. In fig. 21, a back dielectric layer 116 is formed on the back surface of the thinned substrate, and the back dielectric layer 116 is an insulating dielectric layer.

As shown in fig. 22, a back dry etching process is performed on the thinned substrate, and the formed first back via hole 100e is conducted to the conductive pillar structure 113.

As shown in fig. 23, a dielectric layer 117 is deposited in the first backside via 100e and on the surface of the backside dielectric layer 116, and a second backside via 100f is formed by dry etching. The second backside via 100f is etched into the semiconductor substrate at a location near the channel structure 105.

As shown in fig. 24, the bottom substrate region of the second backside via 100f is subjected to backside ion implantation to form a doped region that improves the conductive properties. After the implantation process, a backside metal layer 118 is deposited on the backside and chemically mechanically polished to the backside dielectric layer 116 to form conductive structures in the first backside via 100e and the second backside via 100f.

As shown in fig. 25, a metal connection layer 119 and a passivation layer 120 are formed on the surface of the array wafer. The metal connection layer 119 is connected to each conductive structure exposed on the surface of the array wafer, and forms a pad structure in the opening area of the passivation layer 120.

As an example, as shown in fig. 25, the semiconductor substrate 100 includes a first surface and a second surface that are disposed opposite to each other, and the recess 101 and the stacked structure are formed on the first surface side of the semiconductor substrate 100; the control wafer 2 includes a control wafer substrate including a third surface and a fourth surface disposed opposite to each other, and the fourth surface is located on a side away from the array wafer 1 than the third surface when the control wafer 2 is bonded to the array wafer 1.

In this embodiment, the electrical connection structure is formed on the surface of one side of the array wafer, and the source of the channel structure of the three-dimensional memory is electrically led out through the conductive structure formed by the second backside via 100f on the semiconductor substrate 100.

According to the embodiment, the core region with the grooves is introduced in the preparation process of the three-dimensional memory device, the sacrificial layer, the isolation medium layer and the first semiconductor layer are formed in the grooves, the etching rate difference between the core region and the step region is balanced in the gate line gap groove etching process of the stacked structure, etching damage defects caused by the fact that the etching rate of the core region is too high are prevented, and the performance and the yield of the three-dimensional memory are improved. Compared with the prior art, the invention only needs to add the photoetching/etching process for introducing a groove, does not need to add other extra processes, has better compatibility with the existing process, and has the obvious advantages of simple and convenient implementation and low process cost.

Referring to fig. 2 and 25, the present embodiment further provides a three-dimensional memory structure, which includes:

a semiconductor substrate 100 having a recess 101, in which a core region 100a and a step region 100b are defined, the recess 101 being located in the core region 100a, the recess 101 being filled with a second semiconductor layer 107 and a first semiconductor layer 104 in this order;

a stacked structure provided on the semiconductor substrate 100 and the first semiconductor layer 104, including gate layers 108 and isolation layers 109 alternately stacked; the stacked structure has a step structure in the step region 100 b;

a channel structure 105 penetrating the stacked structure, the first semiconductor layer, and the second semiconductor layer into the semiconductor substrate 100;

a gate line gap structure 106, which is located in a portion of the core region 100a, penetrates the stacked structure and the first semiconductor layer 104 and contacts the second semiconductor layer 107.

As an example, as shown in fig. 25, the first semiconductor layer 104 and the second semiconductor layer 107 include doped polysilicon layers.

As an example, as shown in fig. 11, the junction of the core region and the step region is defined as an interface region; a dummy channel structure 105d is also formed in the interface region; the dummy channel structure 105d extends through the stacked structure into the semiconductor substrate 100.

As an example, as shown in fig. 25, the three-dimensional memory structure further includes a metal connection structure. The specific structure of the metal connection structure can be described with reference to the preparation method. A metal connection layer 119 and a passivation layer 120 are also formed on the surface of the array wafer. The metal connection layer 119 is connected to each conductive structure exposed on the surface of the array wafer, and forms a pad structure in the opening area of the passivation layer 120. In addition, the wafer on which the semiconductor substrate 100 is located is defined as an array wafer 1, and the three-dimensional memory structure further includes a control wafer 2 bonded to the array wafer 1.

Example two

The difference between the three-dimensional memory structure provided in this embodiment and the first embodiment is that the source contact of the channel structure of the three-dimensional memory in the first embodiment is electrically led out from the back surface of the substrate through the conductive structure formed by the second back surface through hole 100f on the semiconductor substrate 100, and the electrical connection structure includes a metal connection layer and a pad structure formed by the exposed region; in this embodiment, the source contact of the channel structure of the three-dimensional memory is electrically led out from the front surface through the semiconductor substrate, and the electrical connection structure only includes the pad structure.

Specifically, as shown in fig. 26, in the present embodiment, the channel structure 305 of the three-dimensional memory is electrically connected to the semiconductor substrate through the second semiconductor layer 307, and is further electrically led out from the front surface thereof to the underlying control wafer through the conductive pillar structure 313. In contrast to the first embodiment, the metal connection layer 319 protected by the passivation layer 320 on the surface of the array wafer is not directly electrically connected to the semiconductor substrate.

Other embodiments of this embodiment are the same as those of embodiment one, and will not be described here again.

Example III

The present embodiment provides a three-dimensional memory structure, which is different from the first embodiment in that in the present embodiment, electrical connection structures are formed on the surfaces of the array wafer and the control wafer, and the electrical connection structures include a metal connection layer and a pad structure.

Specifically, as shown in fig. 27, in the present embodiment, the metal connection layer 419 formed on the surface of the underlying array wafer is completely covered and protected by the passivation layer 420, and no pad structure is formed. And a portion of the metal connection layer 519 forms a pad structure at the opening of the passivation layer 520 on the surface of the control wafer above. According to the embodiment, the electric connection structures can be formed on the two sides of the array wafer and the control wafer, and the flexibility of device design is improved.

Example IV

The present embodiment provides a three-dimensional memory structure, which differs from the third embodiment similarly to the differences between the second embodiment and the first embodiment. In this embodiment, the source electrode of the channel structure of the three-dimensional memory is also electrically led out from the front surface thereof through the semiconductor substrate, and the electrical connection structure thereof only includes the pad structure.

Specifically, as shown in fig. 28, in the present embodiment, the channel structure 605 of the three-dimensional memory is electrically connected to the semiconductor substrate through the second semiconductor layer 607, and is further electrically led out from the front surface thereof to the upper control wafer through the conductive pillar structure 613. Therefore, compared to the third embodiment, the metal connection layer 419 and the passivation layer 420 on one side of the array wafer in the third embodiment are not required to be introduced, and only the metal connection layer 619 and the passivation layer 620 are required to be formed on the surface of the control wafer to form the pad structure.

Other embodiments of this example are the same as the three embodiments of this example, and will not be described here again.

In summary, the present invention provides a three-dimensional memory structure and a method for preparing the same, wherein the method for preparing the same includes the following steps: providing a semiconductor substrate with a groove, defining a core region and a step region in the semiconductor substrate, wherein the groove is positioned in the core region; forming a sacrificial layer and a first semiconductor layer in the groove in sequence; forming a stacked structure over the semiconductor substrate and the first semiconductor layer, forming a channel structure in the core region through the stacked structure into the semiconductor substrate; the stacking structure is provided with a step structure in the step area; forming a gate line gap groove penetrating through the stacked structure, wherein the gate line gap groove penetrates through the stacked structure to the sacrificial layer at the part of the core region; removing the sacrificial layer and filling the second semiconductor layer; and forming a grid line gap structure in the grid line gap groove. According to the invention, the grooves with the sacrificial layers, the isolation medium layers and the first semiconductor layers are formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap grooves of the stacked structure, the etching damage defect caused by the too high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A method for fabricating a three-dimensional memory structure, comprising the steps of:

removing the sacrificial layer and filling the second semiconductor layer;

and forming a grid line gap structure in the grid line gap groove.

2. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the method for sequentially forming the sacrificial layer and the first semiconductor layer in the groove comprises the following steps:

3. The method of fabricating a three-dimensional memory structure of claim 1, wherein: an isolation medium layer is further formed between the sacrificial layer and the first semiconductor layer.

4. A method of fabricating a three-dimensional memory structure according to claim 3, wherein: the isolation medium layer comprises a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer comprises a polysilicon layer; the first semiconductor layer and the second semiconductor layer include doped polysilicon layers.

5. A method of fabricating a three-dimensional memory structure according to claim 3, wherein: after the grid line gap groove is formed, the method further comprises the steps of forming a side wall dielectric layer on the side wall of the grid line gap groove and removing the isolation dielectric layer at the bottom of the grid line gap groove.

6. The method of manufacturing a three-dimensional memory structure of claim 5, wherein: the method further comprises the step of forming an insulating medium layer on the semiconductor substrate before forming the sacrificial layer; and after the sacrificial layer is removed, the method further comprises the step of removing the isolation dielectric layer and the insulation dielectric layer.

7. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the gate line clearance groove penetrates through the stacked structure to the semiconductor substrate at the part of the step area.

8. The method of fabricating a three-dimensional memory structure of claim 1, wherein: defining the junction of the core region and the step region as a junction region; before forming the grid line gap groove in the stacking structure, the method further comprises the step of forming a dummy channel structure in the interface area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

9. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the stacked structure is formed by alternately stacking gate sacrificial layers and isolation layers; and after the grid line gap groove is formed in the stacked structure, removing the grid sacrificial layer and forming a grid layer.

10. The method of fabricating a three-dimensional memory structure of claim 1, wherein: and after the grid line gap structure is formed in the grid line gap groove, the method further comprises the step of forming a metal connection structure.

11. The method of fabricating a three-dimensional memory structure of claim 10, wherein: defining the wafer of the semiconductor substrate as an array wafer, and after forming the metal connection structure, further comprising: providing a control wafer and bonding the array wafer and the control wafer through a bonding structure.

12. The method of fabricating a three-dimensional memory structure of claim 11, wherein: the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, and the stacking structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, wherein the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned at one side far away from the array wafer compared with the third surface; after the array wafer is bonded with the control wafer, the method further comprises the step of forming an electrical connection structure on the second surface and/or the fourth surface.

13. A three-dimensional memory structure, comprising:

14. The three-dimensional memory structure of claim 13 wherein: the first semiconductor layer and the second semiconductor layer include doped polysilicon layers.

15. The three-dimensional memory structure of claim 13 wherein: a dummy channel structure is formed in the junction area of the core area and the step area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

16. The three-dimensional memory structure of claim 13 wherein: also includes a metal connection structure.

17. The three-dimensional memory structure of claim 13 wherein: the wafer where the semiconductor substrate is located is defined as an array wafer, and the three-dimensional memory structure further comprises a control wafer bonded with the array wafer.

18. The three-dimensional memory structure of claim 17 wherein: the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, and the stacking structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, wherein the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned at one side far away from the array wafer compared with the third surface; the second surface and/or the fourth surface is/are formed with an electrical connection structure.

19. The three-dimensional memory structure of claim 18 wherein: the electrical connection structure comprises a welding pad structure and a metal connection layer, the welding pad structure and the metal connection layer are formed on the second surface and/or the fourth surface, and the metal connection layer is electrically connected with the semiconductor substrate.

20. The three-dimensional memory structure of claim 18 wherein: the electrical connection structure comprises a welding pad structure, the welding pad structure is formed on the second surface and/or the fourth surface, and the semiconductor substrate is electrically led out through a conductive column structure arranged on one side of the first surface.