CN112614849A

CN112614849A - Three-dimensional memory structure and preparation method thereof

Info

Publication number: CN112614849A
Application number: CN202011466325.0A
Authority: CN
Inventors: 张坤
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2021-04-06
Anticipated expiration: 2040-12-14
Also published as: CN112614849B

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate; the core area is provided with a groove; forming a sacrificial layer and a first semiconductor layer in the groove; forming a stacked structure and a channel structure over the semiconductor substrate and the first semiconductor layer; forming a gate line gap trench penetrating through the stacked structure, wherein part of the gate line gap trench penetrates through the stacked structure to the sacrificial layer in the core region; removing the sacrificial layer and the isolation dielectric layer, and filling the second semiconductor layer; and forming a grid line gap structure in the grid line gap groove. According to the invention, the groove with the sacrificial layer, the isolation dielectric layer and the first semiconductor layer is formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap groove of the stacked structure, the defect of etching damage caused by the over-high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

Description

Three-dimensional memory structure and preparation method thereof

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a three-dimensional memory structure and a preparation method thereof.

Background

The 3D NAND memory has a three-dimensional stacked structure, and has a higher storage density per unit area than a common two-dimensional memory device, and is a mainstream development direction of the memory with great innovation.

At present, in the process of manufacturing a 3D NAND memory, the number of layers of a device stack structure is also increasing continuously based on the requirement for improving the device performance, which provides a new challenge for the etching process of structures such as gate line gap trenches or channel holes penetrating through the stack structure, and especially, the non-uniformity of etching in regions having different film structures such as a core region and a step region tends to be more remarkable. In order to prevent the device structure from being damaged by over-etching caused by non-uniformity of etching, it is necessary to adjust the processes such as etching and to adjust the film structures in different regions in a targeted manner.

However, in the conventional 3D NAND memory process, the device structure defect caused by the non-uniformity of etching cannot be overcome only by adjusting the etching process and the film structure. For example, when etching a gate line gap trench, the core region is mainly composed of alternating stacked silicon nitride layers and silicon oxide layers, and the silicon oxide layers occupy a larger proportion in the step region, which results in a faster etching rate in the core region during the same etching process. When the step region is still etched, the etching process of the core region already touches the bottom stop layer, and excessive over-etching damages the bottom substrate and affects the performance of the device.

Therefore, there is a need for a new three-dimensional memory structure and a method for fabricating the same to solve the above-mentioned problems.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for fabricating the same, which are used to solve the problem of poor etching uniformity of a gate line gap trench of the three-dimensional memory structure in the prior art.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory structure, comprising the steps of:

providing a semiconductor substrate with a groove, wherein a core area and a step area are defined in the semiconductor substrate, and the groove is positioned in the core area;

sequentially forming a sacrificial layer and a first semiconductor layer in the groove;

forming a stacked structure above the semiconductor substrate and the first semiconductor layer, and forming a channel structure penetrating the stacked structure into the semiconductor substrate in the core region; the stacked structure has a step structure in the step region;

forming a gate line gap trench through the stacked structure, a portion of the gate line gap trench in the core region penetrating through the stacked structure to the sacrificial layer;

removing the sacrificial layer and filling a second semiconductor layer;

and forming a grid line gap structure in the grid line gap groove.

As an alternative of the present invention, a method of sequentially forming the sacrificial layer and the first semiconductor layer in the groove includes the steps of:

depositing the sacrificial layer and the first semiconductor layer above the semiconductor substrate in sequence;

and removing the sacrificial layer and the first semiconductor layer in other areas except the groove on the semiconductor substrate.

As an alternative of the present invention, an isolation dielectric layer is further formed between the sacrificial layer and the first semiconductor layer.

As an alternative of the present invention, the isolation dielectric layer includes a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer comprises a polysilicon layer; the first semiconductor layer and the second semiconductor layer include a doped polysilicon layer.

As an alternative of the present invention, after the gate line gap trench is formed, a step of forming a sidewall dielectric layer on the sidewall of the gate line gap trench and removing the isolation dielectric layer located at the bottom of the gate line gap trench is further included.

As an alternative of the invention, the method further comprises the step of forming an insulating medium layer on the semiconductor substrate before forming the sacrificial layer; and after the sacrificial layer is removed, the method also comprises the step of removing the isolation dielectric layer and the insulating dielectric layer.

As an alternative of the present invention, the gate gap trench penetrates the stacked structure to the semiconductor substrate at a portion of the step region.

As an alternative of the present invention, a boundary between the core area and the step area is defined as a boundary area; before forming the grid line gap groove in the stacked structure, forming a dummy channel structure in the junction area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

As an alternative of the present invention, the stacked structure is formed by alternately stacking gate sacrificial layers and isolation layers; and after the grid line gap groove is formed in the stacked structure, the method also comprises the steps of removing the grid sacrificial layer and forming a grid layer.

As an alternative of the present invention, after the gate gap structure is formed in the gate gap trench, a step of forming a metal connection structure is further included.

As an alternative of the present invention, the wafer on which the semiconductor substrate is located is defined as an array wafer, and after the forming the metal connection structure, the method further includes: and providing a control wafer, and bonding the array wafer and the control wafer through a bonding structure.

As an alternative of the present invention, the semiconductor substrate includes a first surface and a second surface which are oppositely arranged, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned on one side far away from the array wafer compared with the third surface; after the array wafer is bonded with the control wafer, the method further comprises the step of forming an electrical connection structure on the second surface and/or the fourth surface.

The present invention also provides a three-dimensional memory structure, comprising:

the semiconductor device comprises a semiconductor substrate with a groove, wherein a core area and a step area are defined in the semiconductor substrate, the groove is positioned in the core area, and a second semiconductor layer and a first semiconductor layer are sequentially filled in the groove;

a stack structure provided on the semiconductor substrate and the first semiconductor layer, including gate layers and isolation layers alternately stacked; the stacked structure has a step structure in the step region;

a channel structure penetrating through the stacked structure, the first semiconductor layer and the second semiconductor layer into the semiconductor substrate;

and a gate line gap structure, a portion of which is located in the core region, penetrates the stacked structure and the first semiconductor layer and contacts the second semiconductor layer.

As an alternative of the invention, the first semiconductor layer and the second semiconductor layer comprise doped polysilicon layers.

As an alternative of the present invention, a dummy channel structure is further formed at an interface area between the core area and the step area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

As an alternative of the present invention, the three-dimensional memory structure further comprises a metal connection structure.

As an alternative of the present invention, the wafer on which the semiconductor substrate is located is defined as an array wafer, and the three-dimensional memory structure further includes a control wafer bonded to the array wafer.

As an alternative of the present invention, the semiconductor substrate includes a first surface and a second surface which are oppositely arranged, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned on one side far away from the array wafer compared with the third surface; the second surface and/or the fourth surface are/is provided with an electrical connection structure

As an alternative of the present invention, the electrical connection structure includes a pad structure and a metal connection layer, the pad structure and the metal connection layer are formed on the second surface and/or the fourth surface, and the metal connection layer is electrically connected to the semiconductor substrate.

As an alternative of the present invention, the electrical connection structure includes a pad structure, the pad structure is formed on the second surface and/or the fourth surface, and the semiconductor substrate is electrically extracted through a conductive pillar structure disposed on one side of the first surface.

As described above, the present invention provides a three-dimensional memory structure and a method for manufacturing the same, which have the following advantages:

according to the invention, the groove with the sacrificial layer, the isolation dielectric layer and the first semiconductor layer is formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap groove of the stacked structure, the defect of etching damage caused by the over-high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a three-dimensional memory structure according to a first embodiment of the invention.

FIG. 2 is a schematic top view of a portion of a three-dimensional memory design layout according to a first embodiment of the invention.

Fig. 3 to 25 are schematic cross-sectional views illustrating steps of a method for fabricating a three-dimensional memory structure according to a first embodiment of the invention.

Fig. 26 is a schematic cross-sectional view illustrating a three-dimensional memory structure according to a second embodiment of the invention.

Fig. 27 is a schematic cross-sectional view of a three-dimensional memory structure according to a third embodiment of the invention.

Fig. 28 is a schematic cross-sectional view illustrating a three-dimensional memory structure according to a fourth embodiment of the invention.

Description of the element reference numerals

1 array wafer

100 semiconductor substrate

100a core region

100b step area

100c well region

100d oxide layer

100e first backside via

100f second backside via

101 groove

102 sacrificial layer

103 isolating dielectric layer

104 first semiconductor layer

105 channel structure

105a channel gate dielectric layer

105b channel conductive layer

105c channel insulating layer

105d dummy channel structure

106 grid line gap structure

106a grid line gap groove

106b dielectric protective layer

107 second semiconductor layer

108 Gate layer

108a gate sacrificial layer

109 barrier layer

110 dielectric isolation layer

111 dielectric fill layer

112 dielectric capping layer

113 conductive pillar structure

114 contact hole structure

115 bonding structure

116 back side dielectric layer

117 dielectric layer

118 back side metal layer

119 metal connection layer

120 passivation layer

2 control wafer

215 bonding structure

305 channel structure

307 second semiconductor layer

313 conductive pillar structure

319 metal connection layer

320 passivation layer

419 metal connecting layer

420 passivation layer

519 metal connecting layer

520 passivation layer

605 channel structure

607 second semiconductor layer

613 conductive pillar structure

619 Metal connection layer

620 passivation layer

S1-S6 Steps 1) -6)

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 28. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

Referring to fig. 1 to 25, the present embodiment provides a method for manufacturing a three-dimensional memory structure, which is characterized in that: the method comprises the following steps:

1) providing a semiconductor substrate 100 having a groove 101, defining a core region 100a and a step region 100b in the semiconductor substrate 100, wherein the groove 101 is located in the core region 100 a;

2) sequentially forming a sacrificial layer 102 and a first semiconductor layer 104 in the groove 101;

3) forming a stacked structure over the semiconductor substrate 100 and the first semiconductor layer 104, and forming a channel structure 105 penetrating the stacked structure into the semiconductor substrate 100 in the core region 100 a; the stacked structure has a step structure in the step region;

4) forming a gate-gap trench 106a through the stacked structure, the gate-gap trench 106a penetrating the stacked structure to the sacrificial layer 102 at a portion of the core region 100 a;

5) removing the sacrificial layer 102 and filling the second semiconductor layer 107;

6) a gate gap structure 106 is formed in the gate gap trench 106 a.

In step 1), please refer to step S1 of fig. 1 and fig. 2 to 5, a semiconductor substrate 100 having a groove 101 is provided, a core region 100a and a step region 100b are defined in the semiconductor substrate 100, and the groove 101 is located in the core region 100 a. As shown in fig. 2, which is a partial top view of the design layout of the three-dimensional memory structure provided in this embodiment, the three-dimensional memory structure is divided into a core region 100a and the step regions 100b located at two sides of the core region, channel structures 105 are distributed in the core region 100a, and gate line gap structures 106 penetrate through the stacked structure of the core region 100a and the step regions 100 b. Fig. 3 is a cross-sectional view of the semiconductor substrate 100, in which the core region 100a is on the left side and the stepped region 100b is on the right side in fig. 3. Alternatively, the semiconductor substrate 100 includes a silicon substrate. The upper region of the semiconductor substrate 100 is also formed with a doped well region 100 c. When the semiconductor substrate 100 is a P-type silicon substrate, the well region 100c is doped N-type. The well region 100c is formed by furnace diffusion or ion implantation. Optionally, an oxide layer 100d may be formed on the semiconductor substrate 100 before ion implantation to control channeling during ion implantation. As shown in fig. 3 to 4, the groove 101 is located on the semiconductor substrate 100, and the coverage of the groove coincides with the core region 100a, that is, the groove 101 is formed on the semiconductor substrate 100 within the core region 100 a. The groove 101 may be formed by photolithography and dry etching. Optionally, a photoresist etching mask covers the non-etched step region 100b, and in the core region 100a, the oxide layer 100d in the region is removed by dry etching, and a part of the doped well region 100c is further etched away to form the groove 101. Optionally, as shown in fig. 5, after the groove 101 is formed, a step of forming an oxide layer in the groove 101 by a thermal oxidation process is further included. The thermal oxidation process forms an oxide layer only on the silicon material of the semiconductor substrate 100, and the newly formed oxide layer will be connected with the original oxide layer 100d to form a piece, which is defined as an insulating dielectric layer on the semiconductor substrate 100 in this embodiment. Optionally, the insulating medium layer may be formed by other material layers besides the oxide layer.

In step 2), referring to step S2 of fig. 1 and fig. 5 to 7, the sacrificial layer 102 and the first semiconductor layer 104 are sequentially formed in the groove 101.

Optionally, an isolation dielectric layer 103 is further formed between the sacrificial layer 102 and the first semiconductor layer 104.

Optionally, as shown in fig. 5 to 7, the method for sequentially forming the sacrificial layer 102, the isolation dielectric layer 103, and the first semiconductor layer 104 in the groove 101 includes the following steps:

depositing the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 above the semiconductor substrate 100 in sequence;

removing the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 on the semiconductor substrate 100 except the groove 101 by chemical mechanical polishing.

As shown in fig. 5 to 6, the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 are sequentially deposited above the semiconductor substrate 100, including in the groove 101, by a thin film deposition process such as a Chemical Vapor Deposition (CVD) process. The isolation dielectric layer 103 comprises a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer 102 comprises a polysilicon layer and the first semiconductor layer 104 comprises a doped polysilicon layer.

As shown in fig. 6 to 7, the semiconductor substrate 100 deposited with the material layers is subjected to Chemical Mechanical Polishing (CMP), and the oxide layer 100d on the surface of the semiconductor substrate 100 is used as a polishing stop layer, so that the sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 are only left in the groove 101 after the CMP. Through the above process, the L-shaped sacrificial layer 102, the isolation dielectric layer 103 and the first semiconductor layer 104 are formed in the core region 100a near the step region 100 b.

In step 3), referring to step S3 of fig. 1 and fig. 8 to 10, a stacked structure is formed over the first semiconductor layer 104 of the semiconductor substrate 100, and a channel structure 105 penetrating the stacked structure into the semiconductor substrate 100 is formed in the core region 100 a; the stacked structure has a step structure in the step region.

As shown in fig. 8, a stacked structure is formed above the semiconductor substrate 100, and the stacked structure is formed by alternately stacking a gate sacrificial layer 108a and an isolation layer 109, wherein the gate sacrificial layer 108a may be a silicon nitride layer, and the isolation layer 109 may be a silicon dioxide layer.

As shown in fig. 9, a stepped structure of the stepped region 100b is formed in the left region of fig. 9, and the right region is the core region 100a, by a multi-step dry etching of trimming photoresist. The step structure is further covered with a dielectric isolation layer 110 and a dielectric filling layer 111.

As shown in fig. 10, a plurality of channel structures 105 are formed in the stacked structure. Specifically, the channel structure 105 is, in order from outside to inside: a channel gate dielectric layer 105a, a channel conductive layer 105b, and a channel insulating layer 105 c. A dielectric cap layer 112 is also formed over the entire area. The process of forming the channel structure 105 includes: a channel through hole is formed in the stacked structure by dry etching, and a channel gate dielectric layer 105a, a channel conductive layer 105b and a channel insulating layer 105c are sequentially formed in the channel through hole by thin film deposition and etching.

As shown in fig. 11, in addition to forming the channel structure 105 in the stacked structure, a plurality of dummy channel structures 105d are also formed in the stacked structure, and the positions of the dummy channel structures 105d are not in the cross section along the AA' direction in fig. 2, and are distributed at the boundary between the core region 100a and the step region 100b, which is not shown in fig. 2. Specifically, the boundary between the core region 100a and the step region 100b is defined as a boundary region, and the dummy channel structure 105d is formed in the boundary region. Optionally, in this embodiment, the interface region may include a portion of the core region 100a and the step region 100 b. In other embodiments of the present invention, it may also include only a portion of the core region 100a, or only the step region 100 b. As shown in fig. 11, a portion of the dummy channel structure 105d located in the step region 100b penetrates through the stacked structure of the step region 100b to the doped well region 100 c. The dummy channel structure 105d is located in a portion of the core region 100a, and penetrates through the stacked structure of the core region 100a, the sacrificial layer 102, the isolation dielectric layer 103, and the first semiconductor layer 104 to the doped well region 100 c. Only a partial cross-section of the semiconductor substrate 100 is shown in fig. 11. The process of forming the dummy channel structure 105d includes: a dummy channel via is formed by dry etching and filled with an insulating dielectric material, such as silicon dioxide, to form the dummy channel structure 105 d. The dummy channel structures 105d may be distributed at the intersection of the core region 100a and the step region 100b in a region through which the gate line gap trench 106a passes. By introducing the dummy channel structure 105d, the non-uniformity of the gate-line-gap trench etching in the core region 100a and the step region 100b can be further balanced. In addition, the introduction of the dummy channel through hole can also improve the etching uniformity of the channel through hole etching process, and can improve the etching uniformity of the channel through hole which is positioned at the edge of the core area and is close to the step area.

In step 4), please refer to step S4 of fig. 1 and fig. 12 to 13, a gate-line-gap trench 106a penetrating through the stacked structure is formed, and the gate-line-gap trench 106a penetrates through the stacked structure to the sacrificial layer 102 in a portion of the core region 100 a. The gate-gap trench 106a is located through the stacked structure to the semiconductor substrate 100 at a portion of the stepped region 100 b.

It should be noted that, in this embodiment, in order to completely and clearly show the main structures such as the channel and the gate line gap in the same cross-sectional diagram, a dotted line is used as a boundary in fig. 12, a left portion represents a cross section in the AA 'direction in fig. 2, a right portion represents a cross section in the BB' direction in fig. 2, and the situation represented by the subsequent cross-sectional diagrams of this embodiment is also consistent with fig. 12, and will not be described again.

In fig. 12, a gate line gap trench 106a is formed in the stacked structure by anisotropic dry etching, the gate line gap trench 106a penetrates through the stacked structure and the first semiconductor layer 104, and the etching stops on the isolation dielectric layer 103. In the dry etching process, etching gas and process conditions can be correspondingly switched according to the material difference of different films obtained by etching, and a higher etching selection ratio of the isolation dielectric layer 103 below is ensured in the etching process of the first semiconductor layer 104. When the dry etching is directly applied to a semiconductor substrate, the substrate is often damaged (plasma Damage) under the action of plasma, and the generated damaged layer is very likely to cause formation of lattice defects such as dislocation and the like, thereby causing adverse effects on the performance of devices such as electric leakage and the like. Since the groove 101 and the film structures such as the isolation dielectric layer 103 serving as an etching stop layer and the like formed therein are introduced in the embodiment, an etching process window is increased. Even if the gate line gap trench has different etching rates in the core region 100a and the step region 100b, the etching rate in the core region 100a is faster, and the gate line gap trench can be etched and stopped on the isolation dielectric layer 103, so that the damage to the substrate structure is avoided, and the performance of the device is not affected.

As shown in fig. 13, after the gate gap trench 106a is formed, a dielectric protection layer 106b is further formed on the sidewall thereof to protect the stacked structure from being etched in a subsequent wet etching process for removing other dielectric layers. In this embodiment, the dielectric protection layer 106b may be a multi-layer composite structure composed of a silicon nitride layer and a silicon dioxide layer. Optionally, the process of forming the dielectric protection layer 106b includes: first, a dielectric protection material layer such as a silicon dioxide layer and a silicon nitride layer is deposited on the surfaces of the gate line gap trench 106a and the dielectric covering layer 112, and then the dielectric protection material layer on the other region except the side wall of the gate line gap trench 106a is removed by anisotropic dry etching to form the dielectric protection layer 106b, i.e., a side wall dielectric layer. As can also be seen from fig. 13, the dry etching process also removes a portion of the isolation dielectric layer 103 at the bottom of the gate gap trench 106a, the etching process is stopped at the sacrificial layer 102, and the unremoved portion of the isolation dielectric layer 103 in other regions is defined as a residual isolation dielectric layer.

In step 5), referring to step S5 of fig. 1 and fig. 14 to 16, the sacrificial layer 102 is removed and the second semiconductor layer 107 is filled.

As shown in fig. 14, the sacrificial layer 102 is removed by isotropic wet etching. Since the sacrificial layer 102 at the bottom of the gate slit trench 106a is exposed during the formation of the dielectric protection layer 106 b. The entire sacrificial layer 102 may be etched away from this location using a wet etching solution in this embodiment. The sacrificial layer 102 is a polysilicon layer, and wet etching of the polysilicon material does not damage other dielectric material layers.

As shown in fig. 15, a remaining portion of the isolation dielectric layer 103 (i.e., the above-defined remaining isolation dielectric layer) is removed by wet etching, and the exposed portion of the oxide layer 100d on the semiconductor substrate 100 and a portion of the channel gate dielectric layer 105a of the channel structure 105 are also removed. The dielectric protection layer 106b may protect different material layers of the stacked structure on the sidewall of the gate gap trench 106a from being affected by the corresponding etching in the above etching process. In fig. 15, the dielectric protection layer 106b is also depleted during the etching process. In other embodiments of the present invention, the dielectric protection layer 106b may also remain after etching, and is removed by wet etching or the like before subsequent processes are performed.

As shown in fig. 16, a second semiconductor layer 107 is formed by filling in the position occupied by the sacrificial layer 102, and the second semiconductor layer 107 includes a polysilicon layer. The second semiconductor layer 107 is electrically connected to the channel conductive layer 105b of the channel structure 105 after being formed. After the second semiconductor layer 107 is formed, the gate sacrificial layer 108a is also removed by wet etching.

In step 6), referring to step S6 of fig. 1 and fig. 17, the gate gap structure 106 is formed in the gate gap trench 106 a. In this embodiment, the gate line gap structure 102 is formed by filling a silicon dioxide material. Optionally, before forming the gate line gap structure 106, a gate layer 108 is also formed in situ of the gate sacrificial layer 108a, and the gate layer 108 may be formed by filling a conductive material such as metal tungsten.

As shown in fig. 18, after step 6), a metal connection structure is further formed. Optionally, the metal connection structure includes a conductive pillar structure 113 and a contact hole structure 114. The conductive pillar structure 113 is connected to the semiconductor substrate 100 or to the gate layer 108 in a step structure, and the contact hole structure 114 is connected to the conductive pillar structure 113 or the trench structure 105, so as to electrically lead the conductive pillar structure or the trench structure 105 to the upper surface of the wafer. A bonding structure 115 is further formed above the contact hole structure 114.

As an example, as shown in fig. 18 to 19, a wafer on which the semiconductor substrate 100 is located is defined as an array wafer, that is, the structure shown in fig. 18 is a part of the array wafer. In fig. 19, the array wafer 1 is inverted and bonded to the underlying control wafer 2. Specifically, the control wafer 2 has formed therein a CMOS device and a bonding structure 215 on the upper surface, and the bonding structures of the array wafer 1 and the control wafer 2 are aligned and bonded to obtain the bonding wafer in fig. 19.

As shown in fig. 19 to 20, the bonded wafer is thinned from the semiconductor substrate 100 side, and the thickness of the array wafer 1 is thinned to a design specification. In fig. 21, a back dielectric layer 116 is formed on the back surface of the thinned substrate, and the back dielectric layer 116 is an insulating dielectric layer.

As shown in fig. 22, a backside dry etching process is performed on the thinned substrate, and the formed first backside via hole 100e is conducted to the conductive pillar structure 113.

As shown in fig. 23, a dielectric layer 117 is deposited in the first backside via hole 100e and on the surface of the backside dielectric layer 116, and a second backside via hole 100f is formed by dry etching. The second backside via 100f is etched to a position in the semiconductor substrate near the channel structure 105.

As shown in fig. 24, a back side ion implantation is performed on the bottom substrate region of the second back side via 100f to form a doped region for improving the conductivity. After the implantation process, a backside metal layer 118 is deposited on the backside and chemically and mechanically polished to the backside dielectric layer 116 to form conductive structures in the first backside via 100e and the second backside via 100 f.

As shown in fig. 25, a metal connection layer 119 and a passivation layer 120 are formed on the surface of the array wafer. The metal connection layer 119 is connected to each exposed conductive structure on the surface of the array wafer, and forms a pad structure in the opening region of the passivation layer 120.

As an example, as shown in fig. 25, the semiconductor substrate 100 includes a first surface and a second surface which are oppositely disposed, and the groove 101 and the stacked structure are formed on the first surface side of the semiconductor substrate 100; the control wafer 2 includes a control wafer substrate, the control wafer substrate includes a third surface and a fourth surface which are oppositely arranged, and when the control wafer 2 is bonded with the array wafer 1, the fourth surface is located at a side far away from the array wafer 1 compared with the third surface.

In the present embodiment, the electrical connection structure is formed on one side surface of the array wafer, and the source of the channel structure of the three-dimensional memory is electrically led out through the conductive structure formed by the second backside via 100f on the semiconductor substrate 100.

In the embodiment, the core region with the groove is introduced in the preparation process of the three-dimensional memory device, the sacrificial layer, the isolation dielectric layer and the first semiconductor layer are formed in the groove, the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap groove of the stacked structure, the etching damage defect caused by the over-high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved. Compared with the prior art, the invention only needs to add the photoetching/etching process for introducing the groove without adding other additional processes, has better compatibility with the existing process, and has the obvious advantages of simple and convenient implementation and low process cost.

Referring to fig. 2 and fig. 25, the present embodiment further provides a three-dimensional memory structure, which includes:

a semiconductor substrate 100 having a groove 101, in which a core region 100a and a step region 100b are defined, the groove 101 being located in the core region 100a, the groove 101 being sequentially filled with a second semiconductor layer 107 and a first semiconductor layer 104;

a stack structure provided on the semiconductor substrate 100 and the first semiconductor layer 104, including gate layers 108 and isolation layers 109 alternately stacked; the stacked structure has a step structure in the step region 100 b;

a channel structure 105 penetrating through the stacked structure, the first semiconductor layer and the second semiconductor layer into the semiconductor substrate 100;

a gate-line-gap structure 106, a portion of which is located in the core region 100a, penetrates the stacked structure and the first semiconductor layer 104 and contacts the second semiconductor layer 107.

As an example, as shown in fig. 25, the first semiconductor layer 104 and the second semiconductor layer 107 include a doped polysilicon layer.

As an example, as shown in fig. 11, a boundary between the core region and the step region is defined as a boundary region; a dummy channel structure 105d is also formed in the junction region; the dummy channel structure 105d extends through the stack structure into the semiconductor substrate 100.

As an example, as shown in fig. 25, the three-dimensional memory structure further includes a metal connection structure. The specific structure of the metal connection structure can be referred to the preparation method. A metal connection layer 119 and a passivation layer 120 are also formed on the surface of the array wafer. The metal connection layer 119 is connected to each exposed conductive structure on the surface of the array wafer, and forms a pad structure in the opening region of the passivation layer 120. In addition, the wafer on which the semiconductor substrate 100 is located is defined as an array wafer 1, and the three-dimensional memory structure further includes a control wafer 2 bonded to the array wafer 1.

Example two

The present embodiment provides a three-dimensional memory structure, which is different from the first embodiment in that the source contact of the channel structure of the three-dimensional memory in the first embodiment is electrically led out from the back surface of the substrate through the conductive structure formed by the second back surface via hole 100f on the semiconductor substrate 100, and the electrical connection structure thereof includes a metal connection layer and a pad structure formed by an exposed region; in the present embodiment, the source contact of the channel structure of the three-dimensional memory is electrically led out from the front surface through the semiconductor substrate, and the electrical connection structure only includes the pad structure.

Specifically, as shown in fig. 26, in the present embodiment, the channel structure 305 of the three-dimensional memory is electrically connected to the semiconductor substrate through the second semiconductor layer 307, and further electrically led out from the front surface thereof to the underlying control wafer through the conductive pillar structure 313. In contrast to the first embodiment, in the present embodiment, the metal connection layer 319 protected by the passivation layer 320 on the surface of the array wafer is not directly electrically connected to the semiconductor substrate.

Other embodiments of this embodiment are the same as the first embodiment, and are not described herein again.

EXAMPLE III

The present embodiment provides a three-dimensional memory structure, which is different from the first embodiment in that in the present embodiment, an electrical connection structure is formed on the surface of both the array wafer and the control wafer, and the electrical connection structure includes a metal connection layer and a pad structure.

Specifically, as shown in fig. 27, in the present embodiment, the metal connection layer 419 formed on the surface of the underlying array wafer is completely covered and protected by the passivation layer 420, and no pad structure is formed. On the surface of the upper control wafer, a portion of the metal connection layer 519 forms a bonding pad structure at the opening of the passivation layer 520. According to the embodiment, the electrical connection structures can be formed on the two sides of the array wafer and the control wafer, so that the flexibility of device design is improved.

Example four

This embodiment provides a three-dimensional memory structure, which is similar to the difference between the second embodiment and the first embodiment. In the embodiment, the source of the channel structure of the three-dimensional memory is also electrically led out from the front surface of the three-dimensional memory through the semiconductor substrate, and the electrical connection structure only comprises the pad structure.

Specifically, as shown in fig. 28, in the present embodiment, the channel structure 605 of the three-dimensional memory is electrically connected to the semiconductor substrate through the second semiconductor layer 607, and further electrically led out from the front surface thereof to the upper control wafer through the conductive pillar structure 613. Therefore, compared with the third embodiment, in the third embodiment, the metal connection layer 419 and the passivation layer 420 on one side of the array wafer in the third embodiment do not need to be introduced, and only the metal connection layer 619 and the passivation layer 620 need to be formed on the surface of the control wafer to form the pad structure.

Other embodiments of this embodiment are the same as those of the embodiment, and are not described herein again.

In summary, the present invention provides a three-dimensional memory structure and a method for fabricating the same, wherein the method comprises the following steps: providing a semiconductor substrate with a groove, wherein a core area and a step area are defined in the semiconductor substrate, and the groove is positioned in the core area; sequentially forming a sacrificial layer and a first semiconductor layer in the groove; forming a stacked structure above the semiconductor substrate and the first semiconductor layer, and forming a channel structure penetrating the stacked structure into the semiconductor substrate in the core region; the stacked structure has a step structure in the step region; forming a gate line gap trench through the stacked structure, a portion of the gate line gap trench in the core region penetrating through the stacked structure to the sacrificial layer; removing the sacrificial layer and filling a second semiconductor layer; and forming a grid line gap structure in the grid line gap groove. According to the invention, the groove with the sacrificial layer, the isolation dielectric layer and the first semiconductor layer is formed in the core region, so that the etching rate difference between the core region and the step region is balanced in the etching process of the grid line gap groove of the stacked structure, the defect of etching damage caused by the over-high etching rate of the core region is prevented, and the performance and the yield of the three-dimensional memory are improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a three-dimensional memory structure is characterized by comprising the following steps:

removing the sacrificial layer and filling a second semiconductor layer;

and forming a grid line gap structure in the grid line gap groove.

2. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the method for sequentially forming the sacrificial layer and the first semiconductor layer in the groove comprises the following steps:

3. The method of fabricating a three-dimensional memory structure of claim 1, wherein: an isolation dielectric layer is further formed between the sacrificial layer and the first semiconductor layer.

4. The method of fabricating a three-dimensional memory structure according to claim 3, wherein: the isolation medium layer comprises a silicon oxynitride layer or a silicon nitride layer; the sacrificial layer comprises a polysilicon layer; the first semiconductor layer and the second semiconductor layer include a doped polysilicon layer.

5. The method of fabricating a three-dimensional memory structure according to claim 3, wherein: after the grid line gap groove is formed, a side wall dielectric layer is formed on the side wall of the grid line gap groove, and the isolation dielectric layer located at the bottom of the grid line gap groove is removed.

6. The method of fabricating a three-dimensional memory structure according to claim 5, wherein: before the sacrificial layer is formed, forming an insulating medium layer on the semiconductor substrate; and after the sacrificial layer is removed, the method also comprises the step of removing the isolation dielectric layer and the insulating dielectric layer.

7. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the gate gap trench penetrates through the stacked structure to the semiconductor substrate at a portion of the step region.

8. The method of fabricating a three-dimensional memory structure of claim 1, wherein: defining the boundary of the core area and the step area as a boundary area; before forming the grid line gap groove in the stacked structure, forming a dummy channel structure in the junction area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

9. The method of fabricating a three-dimensional memory structure of claim 1, wherein: the stacked structure is formed by alternately stacking grid sacrificial layers and isolating layers; and after the grid line gap groove is formed in the stacked structure, the method also comprises the steps of removing the grid sacrificial layer and forming a grid layer.

10. The method of fabricating a three-dimensional memory structure of claim 1, wherein: and forming a metal connecting structure after the grid gap structure is formed in the grid gap groove.

11. The method of fabricating a three-dimensional memory structure of claim 10, wherein: defining the wafer on which the semiconductor substrate is positioned as an array wafer, and after the metal connection structure is formed, further comprising: and providing a control wafer, and bonding the array wafer and the control wafer through a bonding structure.

12. The method of fabricating a three-dimensional memory structure of claim 11, wherein: the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned on one side far away from the array wafer compared with the third surface; after the array wafer is bonded with the control wafer, the method further comprises the step of forming an electrical connection structure on the second surface and/or the fourth surface.

13. A three-dimensional memory structure, comprising:

14. The three-dimensional memory structure of claim 13, wherein: the first semiconductor layer and the second semiconductor layer include a doped polysilicon layer.

15. The three-dimensional memory structure of claim 13, wherein: a dummy channel structure is further formed in the boundary area of the core area and the step area; the dummy channel structure extends through the stack structure into the semiconductor substrate.

16. The three-dimensional memory structure of claim 13, wherein: also includes a metal connection structure.

17. The three-dimensional memory structure of claim 13, wherein: and defining the wafer on which the semiconductor substrate is positioned as an array wafer, wherein the three-dimensional memory structure further comprises a control wafer bonded with the array wafer.

18. The three-dimensional memory structure of claim 17, wherein: the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, and the stacked structure is formed on the first surface of the semiconductor substrate; the control wafer comprises a control wafer substrate, the control wafer substrate comprises a third surface and a fourth surface which are oppositely arranged, and when the control wafer is bonded with the array wafer, the fourth surface is positioned on one side far away from the array wafer compared with the third surface; the second surface and/or the fourth surface are/is provided with an electrical connection structure.

19. The three-dimensional memory structure of claim 18, wherein: the electric connection structure comprises a welding pad structure and a metal connection layer, the welding pad structure and the metal connection layer are formed on the second surface and/or the fourth surface, and the metal connection layer is electrically connected with the semiconductor substrate.

20. The three-dimensional memory structure of claim 18, wherein: the electric connection structure comprises a welding pad structure, the welding pad structure is formed on the second surface and/or the fourth surface, and the semiconductor substrate is electrically led out through the conductive column structure arranged on one side of the first surface.