CN108649033B

CN108649033B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN108649033B
Application number: CN201810231866.1A
Authority: CN
Inventors: 隋翔宇; 陆智勇; 赵新梅; 王恩博; 霍宗亮; 王孝进
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-03-20
Filing date: 2018-03-20
Publication date: 2021-07-13
Anticipated expiration: 2038-03-20
Also published as: CN108649033A

Abstract

The invention discloses a semiconductor device, comprising a substrate; the conductor/insulator lamination is arranged on the substrate, is formed by alternately stacking conducting layers and insulating layers along a first direction and comprises a core area and a step area which are arranged side by side along a second direction, the thickness of the core area along the first direction is constant, and the thickness of the step area along the first direction is gradually reduced along with the increase of the distance from the core area along the second direction; the first direction is a direction vertical to the surface of the substrate, and the second direction is a direction parallel to the surface of the substrate; a plurality of memory channel regions vertically penetrating the core region of the conductor/insulator stack along a first direction; a plurality of dummy channel regions vertically penetrating the step region of the conductor/insulator stack in the first direction, contacting the substrate; the plurality of dummy channel regions are formed of an insulating material. The invention utilizes the mask to respectively etch and fill the core area and the step area, thereby avoiding the growth defect of the epitaxial layer at the bottom of the step area and improving the reliability of the device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a three-dimensional nand memory cell transistor and a method for fabricating the same.

Background

In order to improve the density of the memory device, extensive efforts have been made to develop a method of reducing the size of the memory cells arranged in two dimensions. As the memory cell size of two-dimensional (2D) memory devices continues to shrink, signal collision and interference may increase significantly, making it difficult to perform a multi-level cell (MLC) operation. To overcome the limitations of the 2D memory device, a memory device having a three-dimensional (3D) structure has been developed in the industry to increase integration density by arranging memory cells three-dimensionally over a substrate.

Cross-sectional views in the fabrication process of a typical 3D NAND device structure are shown in fig. 1a to 1D, where a spacer layer 1s (e.g., silicon oxide) is preferably formed on a substrate, typically Si (corresponding to the core region 1C and the dummy (dummy) region 1D, respectively), a stacked structure of a plurality of dielectric layer stacks, e.g., a structure in which a first layer 2A of nitride and a second layer 2B of oxide are alternately deposited on the spacer layer 1s, and preferably, the bottommost one oxide layer 2B is thicker to improve the insulating isolation effect between the bottom drive transistor and the upper NAND transistor string. In the core region 1C of the memory array, the number of sub-units is larger, so the number of layers 2A/2B is larger, and the number of sub-units in the step region 1D is smaller, and the super-peripheral region is gradually reduced to 0, so the number of layers 2A/2B is gradually reduced, so that the step distribution shown in fig. 1a exists in the layer structure 2A/2B in the step region 1D. A protective/passivation layer 3 of an oxide or low-k material, such as silicon oxide prepared from TEOS (abbreviated as TEOS), is deposited over the entire device. Preferably, the protective layer 3 comprises a plurality of sub-layers (not shown), such as a denser TEOS prepared by a bottom HDPCVD process covering the entire dielectric layer stack 2A/2B, a looser TEOS prepared by a middle LPCVD process, and a denser PECVD prepared silicon oxide, silicon nitride or silicon oxynitride on the top.

As shown in the top mask view of fig. 1B and the cross-sectional device view of fig. 1C, different mask patterns, e.g., 3C and 3D, respectively, are used for the core region and the mesa regions, and the multi-layer stack 2A/2B on the substrate is etched by an anisotropic etching process to form a plurality of trench vias, which are distributed along the extension direction of the Word Lines (WL) of the memory cells and are perpendicular to the substrate surface, including a core region trench hole 3HC and a mesa region trench hole 3HD (which may be up to the substrate surface or have some over-etching).

As shown in fig. 1d, in order to improve the film quality of the subsequently deposited vertical channel and to improve the driving capability of the bottom driving transistor, it is usually necessary to epitaxially grow a mesa (or silicon island) of single crystal material at the bottom of the channel hole, including the mesa 1EC in the core region and the mesa 1ED in the step region. In this process, to increase the drive capability of the bottom select transistor of the core region while further increasing the charge storage capability of the transistors in the NAND transistor string, the top of the core region mesa 1EC preferably exceeds the top of the bottom first dielectric layer 2A (e.g., nitride) and continues beyond the bottom second dielectric layer 2B (e.g., oxide) by at least 1/3 in height, preferably flush with the middle of the bottom second dielectric layer 2B. In the peripheral step region 1D, in order to ensure that a gate insulating layer with good film formation quality is formed around the step region boss 1ED after the first dielectric layer 2A is removed to be insulated from the gate conductive layer and prevent leakage, the top of the boss 1ED should be at least flush with the top of the bottom first dielectric layer 2A (or the bottom of the bottom second dielectric layer 2B) and preferably over, or even as same as, the core region 1 EC.

The formation of vertical channel layers and preferably channel fill layers in the channel holes then continues on a mesa basis, followed by the formation of deep holes in the regions between adjacent channel holes that expose the substrate and the sidewalls of the stack 2A/2B, the removal of the first or second layer in the stack structure by deep hole lateral etching leaving a lateral recess in the other, the formation of a gate insulating layer (which may contain multiple sub-layers, such as ONO, to enhance charge storage capability) by oxidation or deposition in the lateral recess, and then the deposition of metal or doped polysilicon to form the gate conductive layer. Thus, the bottom semiconductor mesa 1EC with its lateral gate stack forms a bottom select transistor, while the vertical channel layer with its lateral gate stack forms a NAND transistor string, leaving the dielectric layer 2B as an insulating spacer between adjacent transistors.

However, as shown in fig. 1D, in the actual process of removing the first dielectric layer 2A by etching, as the distance between the dummy memory channel region 1D and the core region 1C increases, the number of sub-units in the transistor string decreases, and the number of stacked layers 2A/2B decreases, so the number of the first dielectric layer 2A also decreases correspondingly, that is, the distance between the dielectric layer stack and the top of the device increases and the height thereof decreases. While the etching speed of the etchant for the protective layer 3 is much higher than that of the dielectric layer stack 2A/2B. Within the same etching time, the etchant will penetrate the protective layer 3 and the dielectric layer stack 2A/2B to the substrate faster in the step region 1D than in the core region 1C, so that the substrate is over-etched in advance, and finally the depth of the channel hole 3HD of the step region 1D is greater than the depth of the channel hole 3HC of the core region 1C.

During the later epitaxial growth of the semiconductor mesa 1EC/1ED, the mesa 1EC height in the core region (and the portion of the step region near the core region) still satisfies the requirement at least higher than the top of the bottom first dielectric layer 2A under the same deposition process conditions. However, in the partial step region (left side in fig. 1d) far from the core region, due to the increase of the over-etching amount of the substrate, the semiconductor layer grown by deposition is not enough to meet the above requirement, so that in the process of forming the gate stack by removing the layer 2A subsequently, the gate dielectric layer is not enough to completely fill the gap between the boss 1ED and the second dielectric layer 2B, and the gate conductive layer may directly contact and electrically connect with the boss 1ED, thereby causing the device failure.

In addition, as the etchant penetrates through the dielectric stack 2A/2B to reach the substrate earlier in the step region, more etchant can laterally erode the dielectric stack before the etching of the core region is completed, which causes a large amount of hole defects on the sidewall of the channel hole 3HD in the step region, which affects the film quality and reduces the reliability of the device when extending the boss or the vertical channel layer subsequently.

Disclosure of Invention

It is therefore an object of the present invention to overcome the above-mentioned drawbacks and to improve the reliability of the device.

To this end, the present invention provides a semiconductor device comprising:

a substrate;

a conductor/insulator stack disposed on the substrate, formed by alternately stacking conductive layers and insulating layers along a first direction, and including a core region and a stepped region disposed side by side along a second direction, wherein a thickness of the core region along the first direction is constant, and a thickness of the stepped region along the first direction decreases with increasing distance from the core region along the second direction; the first direction is a direction perpendicular to the surface of the substrate, and the second direction is a direction parallel to the surface of the substrate;

a plurality of storage channel regions vertically penetrating a core region of the conductor/insulator stack along the first direction;

a plurality of dummy channel regions vertically penetrating the step region of the conductor/insulator stack in the first direction, in contact with the substrate; the plurality of dummy channel regions are comprised of an insulating material.

Wherein the bottom of each memory channel region has a raised epitaxial layer.

Wherein the top of the epitaxial layer is raised at least 1/3 above the height of the lowest dielectric layer.

Further comprising a protective layer covering the core region and the stepped region of the conductor/insulator stack.

The invention also provides a semiconductor device manufacturing method, which comprises the following steps:

forming a plurality of first dielectric layers and second dielectric layers which are alternately stacked along a first direction on a substrate to form a dielectric stack, wherein the dielectric stack comprises a core area and a step area which are arranged side by side along a second direction; the thickness of the core region along the first direction is constant, and the thickness of the step region along the first direction is gradually reduced along with the distance from the core region along the second direction; the first direction is a direction perpendicular to the surface of the substrate, and the second direction is a direction parallel to the surface of the substrate;

etching the dielectric lamination layer in the core area of the device by adopting a first photoresist pattern to form a plurality of channel holes exposing the substrate;

forming a storage channel region in the plurality of channel holes;

etching the dielectric lamination layer in the device step area by adopting a second photoresist pattern to form a plurality of openings for exposing the substrate;

and filling an insulating material in the plurality of openings to form a dummy channel region.

Wherein, before forming the storage channel region, the method further comprises forming a raised epitaxial layer at the bottom of the plurality of channel holes.

Wherein forming the dielectric stack further comprises forming a protective layer on the dielectric stack.

The step of forming the storage channel region comprises the steps of depositing a semiconductor material to fill the plurality of channel holes and carrying out planarization treatment until the protective layer is exposed; and/or, the step of forming the insulating layer comprises depositing an insulating material to fill the plurality of openings and planarizing until the protective layer is exposed.

The storage channel region comprises a grid insulation stack, a semiconductor channel layer and a channel filling layer.

According to the semiconductor device and the manufacturing method thereof, the mask is used for etching and filling the core region and the step region respectively, so that the growth defect of the epitaxial layer at the bottom of the step region is avoided, and the reliability of the device is improved.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

FIGS. 1a to 1D show schematic diagrams of a prior art 3D memory process;

fig. 2a to 2f are cross-sectional views showing a semiconductor device manufacturing process according to an embodiment of the present invention; and

FIG. 3 shows a flow chart of a method of manufacturing according to an embodiment of the invention.

Detailed Description

Features of the technical solution of the present invention and technical effects thereof are described in detail below with reference to the accompanying drawings in conjunction with exemplary embodiments, disclosing a semiconductor device and a method of manufacturing the same that can effectively improve reliability of a 3D NAND memory device. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.

As shown in FIG. 2a, a substrate 10 is provided, which may comprise bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate, such as SiGe, Si: C, SIGeC, GaN, GaAs, InP, etc., as well as combinations thereof. The substrate is preferably a silicon-containing substrate such as Si, SOI, SiGe, Si: C, SiGeC, etc., for compatibility with existing IC fabrication processes. The substrate includes a portion corresponding to the core region 10C of the semiconductor device, and a portion corresponding to the step region 10D of the semiconductor device. Preferably, an isolation layer 10s of, for example, silicon oxide is formed on the substrate 10 by LPCVD, PECVD, or the like.

The dielectric layer stack in which the first dielectric layer 20A and the second dielectric layer 20B are alternately stacked is sequentially formed on the isolation layer 10s by using conventional processes including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxidation, chemical oxidation, and the like. The materials of layer 20A and layer 20B are different from each other to provide greater etch selectivity, such as any one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride doped with carbon, silicon nitride doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with fluorine, amorphous carbon, diamond-like amorphous carbon (DLC), germanium oxide, aluminum nitride. In a preferred embodiment of the present invention, the first dielectric layer 20A is silicon nitride and the second dielectric layer 20B is silicon oxide. In another preferred embodiment of the present invention, the bottom-most second dielectric layer 20B is thicker than the remaining second dielectric layers 20B (not shown), and is also further thicker than all of the other first dielectric layers 20A, to achieve good isolation of the bottom select transistor from the upper cell transistor string. In some embodiments, the dielectric layer stack is stepped in the device step region 10D, and the step height thereof decreases to 0 with increasing distance from the core region.

A protective layer 30 of silicon oxide (e.g., doped B, P, C, F, such as TEOS silicon oxide) or a low-k material is formed over the entire device by CVD, spin coating, spray coating, screen printing, and the like. Wherein the low-k material includes, but is not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials (e.g., amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers).

A photoresist pattern 31P is formed on the protective layer 30 to expose only the protective layer 30 of the core region. The photoresist pattern 31P is an array of a plurality of opening patterns, similar to the right portion 3C of fig. 1 b. The shape in plan view may be a variety of geometric shapes such as a rectangle, square, diamond, circle, semicircle, oval, triangle, pentagon, hexagon, octagon, and the like.

As shown in fig. 2B, the resist layer 30, the dielectric layer stack 20A/20B, and the isolation layer 10s are sequentially etched using the photoresist pattern 31P as a mask to form an open array of a plurality of channel holes 30HC (referred to as core region channel holes) exposing the substrate of the core region 10C. Preferably using an anisotropic etching process, e.g. (using C)_xH_yF_zIsofluorocarbon etching gases, or SF₆、NF₃、Cl₂HBr, etc. carbon-free etching gas) plasma dry etching or reactive ion etching, etc. Preferably, a slight over-etching is performed, for example 0.2 to 1nm deep into the substrate surface, to ensure complete removal of various defects of the substrate surface, such as native oxides, cracks, contaminant particles, etc. It is further preferred that a wet etching process (e.g., TMAH for Si) is used to etch the substrate surface to form a plurality of periodic micro-pits or micro-protrusions (not shown) for use as nucleation structures for subsequent CVD deposition or epitaxial growth, further improving the film growth quality.

As shown in fig. 2C, a semiconductor epitaxial layer (or mesa) 10EC is selectively epitaxially grown on the substrate exposed at the bottom of the trench hole 30HC in the core region 10C. Growth processes such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, etc., and deposition processes in which conformality and step coverage are good are preferred. The material of the semiconductor layer 10EC may be the same as or different from that of the substrate 10C, and may be, for example, a group IV element such as silicon or germanium, or a group IV, III-V or II-VI compound semiconductor such as SiGe, Si: C, SiGe: C, Ge, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, or the like, or a combination thereof. Preferably, the semiconductor layer 10EC is made of a different material from the substrate to apply stress to the memory channel region using lattice mismatch, thereby improving the driving capability of the selection transistor. Preferably, the semiconductor layer 10EC is directly deposited as a single crystal structure to improve the film formation quality of future panels, or a polycrystalline layer is formed in a low-temperature film formation process and then laser rapid annealing is performed to recrystallize the irradiated region (e.g., the bottom of the channel hole) into a local single crystal or a polycrystalline structure with large crystal domains, so as to avoid the problem of thermal budget for other devices on the wafer due to excessive process temperature during the film formation of the single crystal. Preferably, the photoresist pattern 31P is removed using a wet etching or oxygen plasma dry etching (ashing) process.

As shown in fig. 2d, a vertical memory channel region is formed in the core region channel hole 30 HC. Optionally, a gate insulating layer stack (not shown, uniformly deposited and then etched to expose the bottom epitaxial layer 10EC) is formed on the sidewalls of the channel hole 30HC using a well-conformal deposition process such as HDPCVD, MOCVD, UHVCVD, MBE, ALD, and the like, for example, including an interfacial layer, a barrier layer, a charge storage layer, a tunneling layer, and combinations thereof, for improving memory transistor performance. The gate insulation layer stack may be made of silicon oxide (different deposition process parameters and thicknesses may be controlled to achieve different functions), silicon nitride, or other high-k materials. High-k materials include, but are not limited to, materials selected from HfO₂、HfSiO_x、HfSiON、HfAlO_x、HfTaO_x、HfLaO_x、HfAlSiO_x、HfLaSiO_xOr a hafnium-based material selected from ZrO₂、La₂O₃、LaAlO₃、Ta₂O₅、TiO₂、Y₂O₃、CeO₂Or the rare earth-based high-K dielectric material comprises SiN, AlSiN, AlN and Al₂O₃And a composite layer of the above materials. In a preferred embodiment of the present invention, the gate insulating layer stack is an ONO (silicon oxide-silicon nitride-silicon oxide) stack structure. The memory channel region is then selectively epitaxially grown with a vertical channel layer 40CC based on the epitaxial layer mesa 10 EC. The material of the channel layer 40CC is preferably the same as or similar to that of the epitaxial layer 10EC (with a lattice constant similar to that of the epitaxial layer, with a difference of 15% or less), and may be selected from group IV elementary substances such as silicon and germanium, group IV, group III-V or group II-VI compound semiconductors such as SiGe, Si: C, SiGe: C, Ge, and SiGe,GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, and the like, and combinations thereof. Preferably, the vertical channel layer 40CC is grown while in-situ doping is performed to provide or change the channel layer conductivity type. In some embodiments of the present invention, the gate insulation layer stack is not formed prior to forming the vertical channel layer, but is deposited in a lateral recess left after subsequent etching to remove the first dielectric layer 20A. In a preferred embodiment of the present invention, the epitaxial layer 40CC does not completely fill the core region channel hole 30HC, but the channel isolation layer 40FC is formed by depositing an insulating material or filling an inert gas (with an insulating isolation plug on top). Subsequently, a planarization process such as CMP, etch back, etc. is performed until the protective layer 30 is exposed.

As shown in fig. 2e, the dielectric layer stack 20A/20B in the stepped region 10D is etched using the second photoresist pattern 32P to form a plurality of stepped region recesses or openings 30HD exposing the substrate. The second photoresist pattern 32P completely covers the core region, leaving an array of openings similar to that shown in the left region 3D of fig. 1b only in the step region. The etching process is similar to the process shown in fig. 2b, preferably an anisotropic dry etch. Preferably, as the etch approaches the bottom of the recess (e.g., to the last 3 or 5 dielectric layer 2A/2B combination units), the amount of etch gas is reduced and the amount of oxidizing gas (e.g., O) is increased₂、O₃、H₂O or COS) to form a silicon oxide based pad layer on the sidewall of the deep hole for improving the adhesion of the subsequent filling insulating material.

As shown in fig. 2f, the step-region deep hole 30HD is filled with an insulating material to form an insulating filling layer 50. The deposition process is preferably a process having excellent conformality and good film formation quality such as ALD and MBE, and a thermal oxidation process may be used. Insulating material 50 is, for example, a silicon oxide-based material, including but not limited to SiO₂、SiON、SiOC、SiOF、Si(OCH)_xBSG (B-doped silica glass), PSG (P-doped silica glass), BPSG (B, P-doped silica glass), and the like. The insulating material is then planarized using a process such as CMP until the protective layer 30 is exposed.

Subsequently, a subsequent process (not shown in subsequent drawings) is performed. For example, etching the dielectric layer stack between the vertical storage channel regions to form an exposed substrate andand removing the first dielectric layer 20A by utilizing deep hole isotropic etching to leave a transverse recess in the deep hole on the side wall of the dielectric layer. And implanting at the bottom of the deep hole to form a common source region. A gate insulating layer of silicon oxide or high-k material is conformally formed in the lateral recess using a process such as thermal oxidation, chemical oxidation, CVD deposition, or the like. Then, by using deposition processes such as MOCVD, MBE, ALD, HDPCVD, etc., the gate conductive layer is filled in the remaining portion of the lateral recess, and the material of the gate conductive layer may be polysilicon, poly-silicon-germanium, or metal, wherein the metal may include simple metal such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc., or alloy of these metals, or conductive nitride or conductive oxide of these metals, and may be doped with elements such as C, F, N, O, B, P, As, etc. to adjust the work function. A nitride barrier layer (not shown) is preferably formed between the gate conductive layer and the gate insulating layer by PVD, CVD, ALD, etc., and the barrier layer is preferably M_xN_y、M_xSi_yN_z、M_xAl_yN_z、M_aAl_xSi_yN_zWherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. A drain region is then formed atop the memory channel region 40 CC.

The finally formed semiconductor device includes: the memory channel regions are distributed vertically to the substrate and are positioned in the device core region; a plurality of gate stacks and a plurality of dielectric layers (remaining second dielectric layers) between adjacent gate stacks, orthogonally distributed horizontally to the memory channel region; and a plurality of dummy channel regions distributed vertically to the substrate and positioned in the device step region, and penetrating the plurality of gate stacks and the plurality of dielectric layers to the substrate. Wherein the bottom of each memory channel region has a semiconductor mesa. Preferably, the top of the semiconductor mesa is at least 1/3 above the height of the lowermost dielectric layer. Wherein a protective layer is also present on top of the entire device. The remaining structure, layout and material selection of the semiconductor device, as described in the previous manufacturing method, are not described in detail herein.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of dummy channel regions vertically penetrating the step region of the conductor/insulator stack in the first direction, in contact with the substrate; the dummy channel regions are made of silicon oxide-based insulating materials prepared by ALD (atomic layer deposition), MBE (moving bed epitaxy) and thermal oxidation processes, a silicon oxide-based cushion layer is further arranged between the dummy channel regions and the conductor/insulator lamination, and when the deep hole is formed in the etching step region and the position close to the bottom of the deep hole is close to the deep hole, the content of etching gas is reduced, and the oxidizing gas is increased so that the silicon oxide-based cushion layer is formed on the side wall of the deep hole and used for improving the adhesion of the follow-up filling of the silicon oxide.

2. The semiconductor device of claim 1, wherein a bottom of each memory channel region has a raised epitaxial layer.

3. The semiconductor device of claim 2 wherein the top of the epitaxial layer is raised at least 1/3 above the height of the lowermost dielectric layer.

4. The semiconductor device of claim 1, further comprising a protective layer covering the core region and the step region of the conductor/insulator stack.

5. A semiconductor device manufacturing method, comprising:

forming a storage channel region in the plurality of channel holes;

in the process of forming the plurality of openings, when the openings are close to the bottom of the deep hole, the content of etching gas is reduced, and oxidizing gas is increased to form a silicon oxide base cushion layer on the side wall of the deep hole for improving the adhesive force of the subsequent filling of the silicon oxide base insulating material;

and filling a silicon oxide-based insulating material prepared by ALD, MBE and thermal oxidation processes into the plurality of openings to form a dummy channel region.

6. The manufacturing method of a semiconductor device according to claim 5, wherein the forming of the memory channel region further comprises etching the substrate to form a periodic pattern and/or performing over-etching.

7. The semiconductor device manufacturing method according to claim 5, wherein the forming of the memory channel region further comprises forming a raised epitaxial layer at the bottom of the plurality of channel holes.

8. A method for fabricating a semiconductor device according to claim 5, wherein forming the dielectric stack further comprises forming a protective layer on the dielectric stack.

9. The manufacturing method of a semiconductor device according to claim 8, wherein the step of forming the memory channel region comprises depositing a semiconductor material to fill the plurality of channel holes and planarizing until the protective layer is exposed; and/or, the step of forming the insulating layer comprises depositing an insulating material to fill the plurality of openings and planarizing until the protective layer is exposed.

10. The semiconductor device manufacturing method according to claim 5, wherein the storage channel region comprises a gate insulation stack, a semiconductor channel layer, a channel filling layer.