CN108630691B - Three-dimensional memory and manufacturing method thereof - Google Patents

Three-dimensional memory and manufacturing method thereof Download PDF

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CN108630691B
CN108630691B CN201810249952.5A CN201810249952A CN108630691B CN 108630691 B CN108630691 B CN 108630691B CN 201810249952 A CN201810249952 A CN 201810249952A CN 108630691 B CN108630691 B CN 108630691B
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hard mask
mask layer
layer
semiconductor
vertical channel
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CN108630691A (en
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刘隆冬
王猛
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention discloses a three-dimensional memory and a manufacturing method thereof, comprising the steps of forming a hard mask layer on a substrate and patterning the hard mask layer; forming a semiconductor bump on a substrate using a hard mask pattern; forming a doped region on the top of the semiconductor boss; forming a dielectric layer stack on the hard mask pattern and the semiconductor boss; and etching the dielectric layer stack to form a vertical channel hole exposing the semiconductor boss. According to the manufacturing method of the three-dimensional memory, the doping lug boss is firstly formed on the substrate by using the hard mask pattern, and then the channel hole in the dielectric layer stack is formed, so that the film forming quality, the height and the uniformity of doping concentration of the lug boss at the bottom of the channel hole are improved, the growth defect of a vertical channel region is reduced, and the reliability of a device is improved.

Description

Three-dimensional memory and manufacturing method thereof
Technical Field
The present invention relates to a three-dimensional memory and a method for manufacturing the same, and more particularly, to a three-dimensional nand memory cell transistor and a method for manufacturing the same.
Background
In order to improve the density of the memory device, extensive efforts have been made to develop a method of reducing the size of the memory cells arranged in two dimensions. As the memory cell size of two-dimensional (2D) memory devices continues to shrink, signal collision and interference may increase significantly, making it difficult to perform a multi-level cell (MLC) operation. To overcome the limitations of the 2D memory device, a memory device having a three-dimensional (3D) structure has been developed in the industry to increase integration density by arranging memory cells three-dimensionally over a substrate.
A typical 3D NAND fabrication process as shown in fig. 1a, a stacked structure 2 of a stack of multiple dielectric layers (e.g., an alternating oxide and nitride structure) is deposited on a substrate 1, typically Si; etching the multilayer laminated structure 2 on the substrate 1 by an anisotropic etching process to form a plurality of channel holes 2H (which can reach the substrate surface directly or have a certain over-etching) which are distributed along the extension direction of the Word Line (WL) of the memory unit and are vertical to the substrate surface; depositing a material such as polysilicon in the trench hole 2H to form a pillar-shaped trench (not shown below); etching the multilayer laminated structure 2 along the WL direction to form a groove reaching the substrate, and exposing the multilayer laminated layer surrounding the columnar channel; wet removing a certain type of material in the stack (e.g., hot phosphoric acid to remove silicon nitride, or HF to remove silicon oxide), leaving laterally distributed raised structures around the pillar trench; depositing a gate dielectric layer (e.g., a high-k dielectric material) and a gate conductive layer (e.g., Ti, W, Cu, Mo, etc.) on sidewalls of the protruding structures in the trenches to form a gate conductive layer, e.g., including a bottom select gate line, a dummy gate line, a word line, a top select gate line; removing the grid conducting layer outside the plane of the protrusion side by vertical anisotropic etching until the grid dielectric layer on the protrusion side is exposed; and etching the laminated structure to form source-drain contact and finish the back end manufacturing process.
In this process, in order to improve the driving capability of the bottom driving transistor, it is generally required to increase the overlapping area between the bottom select gate line and the active region, especially the channel region, of the bottom select transistor. A typical scheme is shown in fig. 1b, after etching to form the channel hole 2H, cleaning, over-etching the exposed surface of the substrate 1 to remove defects of amorphous material or native oxide at the bottom of the channel hole 2H, then epitaxially growing a plurality of mesas 1E (e.g., silicon islands) of preferably single crystal material in the channel hole 2H and then ion implantation doping (as shown by the dashed box in fig. 1 b) to serve as vertical channel regions for the select transistor having a height exceeding several sublayers at the bottom of the dielectric stack 2 (e.g., to 1/3 the thickness of the bottom thick silicon oxide layer) to increase the overlap area with future select gate lines.
However, in the actual process, since the aspect ratio of the channel hole 2H is too large (for example, 10 or more and 20 or more), the difficulty of removing the defect at the bottom is high, the film formation quality of the epitaxially grown mesa 1E is not good, the heights of the mesas are not consistent as shown in fig. 1b, a void exists at the bottom, or the defect of the vertical channel layer formed after the defect at the top of the mesa 1E is caused is too large. In addition, in the ion implantation doping process, since the aspect ratio of the channel hole 2H is too large and the ion implantation range is far, if the verticality control of the implantation process is not good, a considerable portion of ions will be incident on the sidewall of the stacked structure 2, thereby affecting the etching selectivity between the sub-layers of the stacked structure 2, so that the active region of the bottom selection transistor deviates from the design layout, or cannot reach the boss 1E at the bottom of the channel hole 2H due to insufficient implantation energy.
Disclosure of Invention
Therefore, the invention aims to overcome the defects, improve the film forming quality, the height and the uniformity of doping concentration of a boss at the bottom of a channel hole, reduce the growth defect of a vertical channel region and improve the reliability of a device.
To this end, the invention provides a method for manufacturing a three-dimensional memory, comprising the following steps:
forming a patterned hard mask layer on a substrate, wherein the patterned hard mask layer is provided with a first vertical channel hole exposing the substrate, and a semiconductor boss is formed in the first vertical channel hole;
forming a doped region on the top of the semiconductor boss;
forming a dielectric layer laminated structure on the patterned hard mask layer and the semiconductor boss;
and etching the dielectric layer laminated structure to form a second vertical channel hole exposing the semiconductor boss.
Wherein the hard mask layer at least comprises a first hard mask layer and a second hard mask layer; optionally, the hard mask layer further comprises a third hard mask layer on the first and/or second hard mask layer; preferably, the material of the first hard mask layer and/or the second hard mask layer and/or the third hard mask layer is selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, amorphous silicon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, low-k material, or a combination thereof.
Wherein a top of the patterned hard mask layer is higher than a top of the semiconductor mesa.
Wherein the step of forming the semiconductor mesa further comprises:
etching the hard mask layer to form a first vertical channel hole exposing the substrate;
depositing a semiconductor layer in the first vertical channel hole and on the patterned hard mask layer;
planarizing the semiconductor layer until the patterned hard mask layer is exposed.
After forming the first vertical channel hole and before depositing the semiconductor layer, etching the substrate to form a periodic pattern and/or performing over-etching.
Wherein the step of forming the semiconductor mesa further comprises:
forming a stop layer on the hard mask layer;
etching the hard mask layer and the stop layer to form a first vertical channel hole exposing the substrate;
depositing a semiconductor layer in the first vertical channel hole and on the patterned stop layer;
planarizing the semiconductor layer until the patterned stop layer is exposed;
removing the stop layer;
planarizing the semiconductor mesa such that the semiconductor layer is flush with the patterned hard mask layer.
Wherein the step of forming the doped region further comprises:
in-situ doping is carried out while a semiconductor boss is formed; or
And carrying out ion implantation doping after the semiconductor lug boss is formed.
Wherein the width of the vertical channel hole is smaller than that of the semiconductor boss.
The material of the semiconductor boss is different from or the same as that of the substrate; optionally, the semiconductor mesa is a single crystal structure, or a recrystallization process is performed after the semiconductor mesa of a polycrystalline structure is formed and before the doped region is formed to convert to a single crystal structure.
Wherein the surface of the semiconductor boss is cleaned after the semiconductor boss is formed and before the doped region is formed.
And the bottom of the dielectric layer laminated structure is made of the same material as the top of the graphical hard mask layer. First vertical channel hole the present invention also provides a three-dimensional memory, which is characterized by comprising:
a patterned hard mask layer stack on the substrate;
a gate/dielectric layer stack structure on the patterned hard mask layer stack, including a plurality of gate stacks stacked in sequence and a dielectric layer stack between adjacent gate stacks;
a first vertical channel hole through the patterned hard mask layer stack, a semiconductor mesa formed in the first vertical channel hole;
and a second vertical channel hole passing through the gate/dielectric layer stack structure, the vertical channel layer being located in the second vertical channel hole.
Wherein the semiconductor mesa is wider than the vertical channel layer.
Wherein the patterned hard mask layer stack comprises at least a first hard mask layer and a second hard mask layer; optionally, the patterned hardmask layer stack further comprises a third hardmask layer on the first and/or second hardmask layers; preferably, the material of the first hard mask layer and/or the second hard mask layer and/or the third hard mask layer is selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, amorphous silicon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, low-k material, or a combination thereof.
Wherein a top of the patterned hard mask layer stack is higher than a top of the semiconductor mesa.
Wherein the top of the semiconductor boss has a doped region.
The material of the semiconductor boss is different from or the same as that of the substrate; optionally, the semiconductor mesa is a single crystal structure.
And the bottom of the grid/dielectric layer laminated structure is made of the same material as the top of the graphical hard mask layer.
According to the manufacturing method of the three-dimensional memory, the doping lug boss is firstly formed on the substrate by using the hard mask pattern, and then the channel hole in the dielectric layer stack is formed, so that the film forming quality, the height and the uniformity of doping concentration of the lug boss at the bottom of the channel hole are improved, the growth defect of a vertical channel region is reduced, and the reliability of a device is improved.
The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.
Drawings
The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:
FIGS. 1a and 1b are schematic cross-sectional views illustrating a prior art process for fabricating a 3D memory;
FIGS. 2a to 2i are schematic cross-sectional views illustrating respective steps of a semiconductor device manufacturing process according to an embodiment of the present invention; and
fig. 3 shows a schematic flow diagram of a semiconductor device fabrication process according to an embodiment of the present invention.
Detailed Description
The features and technical effects of the technical scheme of the invention are described in detail below with reference to the accompanying drawings and the exemplary embodiments, and a novel three-dimensional memory manufacturing method capable of effectively improving the film forming quality of a channel region of a 3D NAND memory device is disclosed. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.
As shown in fig. 3, a schematic flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the invention is described. Firstly, forming a hard mask on a substrate and patterning, then forming a boss on the substrate by using the patterned hard mask, doping the boss during and/or after the boss is formed to form a vertical active region of a bottom selection transistor, then forming a stack consisting of a plurality of dielectric sub-layers on the hard mask pattern and the boss, and then etching the dielectric layer stack to form a plurality of channel holes distributed vertically to the substrate. And then depositing polycrystalline or single crystal materials in the channel holes to form a vertical channel layer of the 3D NAND device, forming deep holes in the dielectric layer stack between the vertical channels, selectively etching part of molecular layers in the dielectric layer stack through the deep holes to leave transverse depressions, forming a gate dielectric layer and a gate conducting layer in the transverse depressions, forming a common source region at the bottoms of the deep holes, and forming a drain at the top of the vertical channel layer, thereby finally completing the manufacture of the 3D memory.
Thus, in the basic process shown in fig. 3, the boss is doped to form the active region, and then the vertical channel is formed in the stacked dielectric layer, so that the epitaxial and/or injection process is not required to be performed through the channel hole with the large aspect ratio, the film forming quality of the boss is improved, and the process cost is reduced.
The specific process flow described in fig. 3 is described in detail below in conjunction with fig. 2 a-2 i.
As shown in fig. 2a, a hard mask layer stack is formed on a substrate 10. Substrate 10 is provided and may comprise bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate such as SiGe, Si: C, SIGeC, GaN, GaAs, InP, and the like, as well as combinations thereof. Substrate 10 is preferably a silicon-containing substrate such as Si, SOI, SiGe, Si: C, SiGeC, etc., for compatibility with existing IC fabrication processes.
A hard mask layer stack is formed on the substrate 10 using conventional processes including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxidation, chemical oxidation, and the like. In a preferred embodiment of the present invention, the hard mask layer stack comprises a plurality of sub-layers, including at least a first hard mask layer 11a and preferably also at least a second hard mask layer 11b, the materials of the layers 11a and 11b being different from each other to provide a larger etch selectivity, for example selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, amorphous silicon, diamond-like amorphous carbon (DLC), germanium oxide, aluminum oxide or a combination thereof. In a preferred embodiment, the first hard mask layer 11a is made of silicon oxide, preferably formed by a thermal oxidation process, and has a small thickness, for example, only 0.2 to 1nm, and is used as a pad protection layer for etching the substrate; the second hard mask layer 11b is made of, for example, silicon nitride, preferably formed by a PECVD process, and has a relatively thick thickness of, for example, 5 to 50nm, and is used as a main hard mask layer for etching the substrate.
In a modification of the present invention, the hardmask layer stack optionally (i.e., may not) further comprises at least one third hardmask layer 11c, which is a different material than the adjacent second hardmask layer 11b (if there is no layer 11b, layer 11c is a different material than layer 11a), preferably, the third hardmask layer is softer to absorb stress during CMP planarization and promote concentration of defects in the third hardmask layer to avoid mesa damage, e.g., silicon oxide or low-k materials. Wherein the low-k material includes, but is not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials (e.g., amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers). The third hard mask layer 11c serves to protect the top of the mesa from being excessively polished in the subsequent planarization process, and thus its deposition thickness needs to be controlled so that the top is higher than the top of the finally formed mesa, for example, the sum of the thickness of the third hard mask layer 11c and the thickness of the hard mask layers 11a and/or 11b is equal to or greater than the final height of the mesa 10a (see fig. 2 f). In a preferred embodiment of the present invention, the third hard mask layer 11c has a thickness of 20 to 200nm, preferably 30 to 150nm, preferably 50 to 100 nm.
In another refinement, the top of the hardmask layer stack further optionally (i.e., may not include) includes at least one polish stop layer or antireflective layer 11 d. The layer 11d is made of a hard material, such as silicon nitride, silicon oxynitride, DLC, etc., and is used to protect the underlying soft third hard mask layer 11c or sub-mask layers 11a/11b during the subsequent CMP planarization process, and also can be used to absorb excessive light radiation during the subsequent photolithography process to improve the exposure and development accuracy. The layer 11d is thin, for example 1 to 10 nm.
A photoresist layer is formed on top of the hard mask layer stack and exposed and developed to form a photoresist pattern 12. The gaps or openings between the patterns 12 control the topography of the future mesas, i.e., the vertical active regions of the bottom selection transistors, and may be, for example, rectangular, square, diamond, circular, semicircular, elliptical, triangular, pentagonal, hexagonal, octagonal, and the like in top view.
As shown in fig. 2b, the photoresist pattern 12 is used as a mask to sequentially etch each hard mask sub-layer of the hard mask layer stack to form a patterned hard mask layer stack, exposing a plurality of first vertical channel holes 11e on the surface of the substrate 10. Preferably using an anisotropic etching process, e.g. (using C)xHyFzIsoflurane etching gas) plasma dry etching or reactive ion etching. Preferably, a slight over-etching is performed, for example 0.2 to 1nm deep into the surface of the substrate 10, to ensure complete removal of various defects such as native oxides, cracks, contaminant particles, etc., from the surface of the substrate 10. It is further preferred that the substrate 10 surface is etched using a wet etching process (e.g., TMAH for Si) to form a plurality of periodic patterns (e.g., periodic micro-pits or micro-bumps (not shown), such as an array of bumps or pits, with individual pattern dimensions of, for example, 0.1 to 1.5nm, and with a spacing between the patterns of, for example, 3 to 10nm) to serve as nucleation structures for subsequent CVD deposition or epitaxial growth, further improving the film growth quality. Subsequently, the photoresist pattern 12 is removed by wet etching or dry oxidation to expose the top of the hard mask stack.
As shown in fig. 2c, a semiconductor layer 10a is formed on the entire device, completely filling the plurality of first vertical channel holes 11e and covering the hard mask stack. The semiconductor layer 10a is preferably deposited in the first vertical channel hole 11e and on top of the hard mask stack by a process such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, and preferably a deposition process wherein conformality and step coverage are good. The material of the semiconductor layer 10a may be the same as or different from that of the substrate 10, and may be a group IV element such as silicon or germanium, or may be selected from group IV, III-V or II-VI compound semiconductors such as SiGe, Si: C, SiGe: C, Ge, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, and the like, and combinations thereof. Preferably, the semiconductor layer 10a is made of a different material from the substrate 10 to apply stress to the channel region by using lattice mismatch, thereby improving the driving capability of the selection transistor. Preferably, the semiconductor layer 10a is directly deposited as a single crystal structure to improve the film-forming quality of future panels, or a polycrystalline layer is formed in a low-temperature film-forming process and then laser rapid annealing is performed to recrystallize the irradiated region (e.g., the region between patterned hard mask stacks) into a local single crystal or a polycrystalline structure with large crystal domains to avoid the thermal budget problem of excessive process temperature during single crystal film-forming for other devices already on the wafer. As shown in fig. 2c, due to the presence of the hard mask stack pattern, the deposited semiconductor layer 10a will have protrusions on top of the patterned hard mask stack and depressions between the patterns.
Therefore, a planarization process, such as a Chemical Mechanical Polishing (CMP) or etch back process, as shown in fig. 2d, is preferably employed such that the semiconductor layer 10a is flush with, i.e., exposes, the top of the patterned hard mask layer stack. In case the patterned hard mask layer stack comprises a polish stop layer 11d, the CMP process will automatically stop on top of layer 11 due to the significantly higher hardness of layer 11d than the semiconductor layer 10 a. In this way, the non-uniformity of the filling of the semiconductor layer 10a between different regions on the wafer can be advantageously reduced.
Subsequently, optionally, as shown in fig. 2e, the polishing stop layer 11d is removed by wet etching. For example, the layer 11d of silicon nitride is removed with hot phosphoric acid, the layer 11d of silicon oxynitride or DLC is removed with a combination of strong acids (nitric acid, sulfuric acid) and strong oxidants (hydrogen peroxide, deionized water containing ozone), and so on, until the structures below the layer 11d, such as the third hard mask layer 11c (if any), are exposed. In this manner, the top and a portion of the sidewalls of the semiconductor layer 10a are re-exposed so as to reduce the top defects thereof later.
Then, optionally, as shown in fig. 2f, a planarization process such as CMP is employed to bring the top of the semiconductor layer 10a flush with the top of the remaining patterned hardmask layer stack (e.g., the top of layer 11 c). In this way, the grinding removes a portion of the top of the semiconductor layer 10a that may have some voids due to premature closing of the fill during film growth or some pores left over by excessive erosion due to the CMP process shown in fig. 2 d. In this process, since the third hard mask layer 11c is made of a soft material, local unevenness of stress or defects such as impurities and cracks are preferably present in the third hard mask layer 11c and are not concentrated on the semiconductor layer 10a, thereby improving the film quality of the semiconductor layer 10 a. In this process, a portion of the top of the third hard mask layer 11c is also removed, so the thickness of the third hard mask layer 11c needs to be larger in the initial step shown in fig. 2a so that the top of the entire hard mask layer stack is higher than the top of the semiconductor layer 10a that is finally left in fig. 2 f.
Preferably, the chemical cleaning removes impurities remaining on top of the semiconductor layer 10 a. For example, a thin layer of oxide formed or grown during a previous process, or contaminant particles left from a previous planarization process, is removed using dHF (dilute hydrofluoric acid). Thereby leaving the semiconductor layer 10a over the surface of the substrate 10 to form a plurality of mesa structures that serve as vertical active regions for subsequent select transistors.
Then, as shown in fig. 2g, an ion implantation process is performed to form a doped region 10b (e.g., a portion above the dotted line) on top of the semiconductor mesa 10 a. The energy of the implanted ions is controlled, and the defect density is improved by preventing ions with overlarge kinetic energy from bombarding the surface. The dose and species of the implanted ions are controlled to obtain active regions of different doping types. In another embodiment of the present invention, the dopant is added into the raw material gas during the deposition process shown in fig. 2c to perform in-situ doping, so that the ion implantation process shown in fig. 2g is not required, thereby avoiding the defect increase caused by the plasma bombardment on the top of the mesa doped region 10 b.
Thereafter, as shown in FIG. 2h, a dielectric layer stack 13a/13b is formed over the entire device, particularly on top of the semiconductor mesa 10b and the patterned hard mask layer stack 11a/11b/11 c. The dielectric layer stack, including the first dielectric layers 13a and the second dielectric layers 13b stacked alternately, is deposited by conventional processes including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., preferably for a number of times equal to or greater than 2 (e.g., 8, as required by the number of cells in the cell string). The first dielectric layer 13a and the second dielectric layer 13b are made of different materials, and are selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like carbon (DLC), germanium oxide, aluminum oxide, and the like, and combinations thereof. Preferably, the material of the lowermost first dielectric layer 13a is the same as the material of the top of the patterned hard mask layer stack (e.g., the third hard mask layer 11c), so as to improve the bonding strength and the film formation uniformity of the dielectric layers around the active region of the select transistor, and avoid the influence of defect state absorption charges on the interface between different materials on the on/off of the select transistor.
Finally, as shown in fig. 2i, the dielectric layer stack is etched to form a second vertical channel hole 13c until the substrate is exposed. By an anisotropic etching process, e.g. (by C)xHyFzPlasma etch gas) or reactive ion etch, to form openings 13c through the dielectric layer stacks 13a/13b, eventually exposing the tops of the semiconductor mesas 10b and the sidewalls of the dielectric layer stacks. The cross-sectional shape of the second vertical channel hole 13c in the plan view may be a rectangular shape, a square shape, a diamond shape, a circular shape, a semicircular shape, an oval shape, a triangular shape, a pentagonal shape, a hexagonal shape, an octagonal shape, or the like. Preferably, the aspect ratio of the second vertical channel hole 13c is equal to or greater than 5:1, preferably equal to or greater than 10:1, and most preferably 20: 1. In a preferred embodiment of the present invention, the second vertical channel hole 13c has a width smaller than that of the first vertical channel hole 11e, i.e., the semiconductor mesa 10b, so that it is possible to ensure that the channel region of the transistor string of the memory cell is electrically connected to the channel region of the selection transistor even if there is an overlay error.
Thereafter, a vertical channel may be deposited in the second vertical channel hole 13c by using a similar process, a deep hole exposing the substrate 10 is formed in the dielectric layer stack on the top of the third hard mask layer 11c, a common source region is formed at the bottom of the deep hole, a recess is left by etching one of the first or second dielectric layers 13a/13b on the sidewall of the deep hole, a gate dielectric and a gate conductor are filled in the recess to form a control gate line (i.e., a plurality of stacked gate stack structures, and the first or second dielectric layer stack structure is left between adjacent gate stack structures to form a gate/dielectric layer stack structure together), a drain is formed on the top of the channel region in the second vertical channel hole 13c, and finally the device manufacturing is completed.
According to the manufacturing method of the three-dimensional memory, the doping lug boss is firstly formed on the substrate by using the hard mask pattern, and then the channel hole in the dielectric layer stack is formed, so that the film forming quality, the height and the uniformity of doping concentration of the lug boss at the bottom of the channel hole are improved, the growth defect of a vertical channel region is reduced, and the reliability of a device is improved.
While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims (15)

1. A method of fabricating a three-dimensional memory, comprising:
forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer is provided with a first vertical channel hole exposing the substrate, and the sum of the thicknesses of the hard mask layer is equal to the final height of a semiconductor boss to be formed subsequently;
forming a semiconductor boss in the first vertical channel hole, wherein the semiconductor boss is flush with the top of the patterned hard mask layer stack;
forming a doped region on the top of the semiconductor boss;
forming a dielectric layer laminated structure on the patterned hard mask layer and the semiconductor boss;
and etching the dielectric layer laminated structure to form a second vertical channel hole exposing the semiconductor boss.
2. The method of fabricating a three-dimensional memory of claim 1, wherein the hard mask layer comprises at least a first hard mask layer and a second hard mask layer.
3. The three-dimensional memory fabrication method of claim 2, the hard mask layer further comprising a third hard mask layer on the first and/or second hard mask layers.
4. The method of claim 3, wherein the first hard mask layer and/or the second hard mask layer and/or the third hard mask layer is made of a material selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, low-k material, or a combination thereof.
5. The method of fabricating a three-dimensional memory of claim 1, wherein the step of forming the semiconductor mesa further comprises:
etching the hard mask layer to form a first vertical channel hole exposing the substrate;
depositing a semiconductor layer in the first vertical channel hole and on the patterned hard mask layer;
planarizing the semiconductor layer until the patterned hard mask layer is exposed; alternatively, the first and second electrodes may be,
the step of forming the semiconductor mesa further includes:
forming a stop layer on the hard mask layer;
etching the hard mask layer and the stop layer to form a first vertical channel hole exposing the substrate;
depositing a semiconductor layer in the first vertical channel hole and on the patterned stop layer;
planarizing the semiconductor layer until the patterned stop layer is exposed;
removing the stop layer;
planarizing the semiconductor mesa such that the semiconductor layer is flush with the patterned hard mask layer.
6. The method of claim 1, wherein a bottom of the dielectric layer stack is the same as a top of the patterned hardmask layer.
7. A three-dimensional memory, comprising:
a patterned hard mask layer stack on the substrate;
a gate/dielectric layer stack structure on the patterned hard mask layer stack, including a plurality of gate stacks stacked in sequence and a dielectric layer stack between adjacent gate stacks;
a first vertical channel hole through the patterned hard mask layer stack, a semiconductor mesa formed in the first vertical channel hole, the semiconductor mesa being flush with a top of the patterned hard mask layer stack;
a second vertical channel hole passing through the gate/dielectric layer stack structure, a vertical channel layer in the second vertical channel hole,
wherein the sum of the thicknesses of the hard mask layer stacks is equal to the final height of a semiconductor mesa to be subsequently formed.
8. The three-dimensional memory of claim 7, wherein the semiconductor mesa is wider than the vertical channel layer.
9. The three-dimensional memory according to claim 7, wherein the patterned hard mask layer stack comprises at least a first hard mask layer and a second hard mask layer.
10. The three-dimensional memory of claim 9, the patterned hardmask layer stack further comprising a third hardmask layer on the first and/or second hardmask layers.
11. The three-dimensional memory according to claim 10, wherein the material of the first and/or second and/or third hard mask layers is selected from any one of silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, low-k material, or a combination thereof.
12. The three-dimensional memory according to claim 7, wherein the top of the semiconductor mesa has a doped region.
13. The three-dimensional memory according to claim 7, wherein the semiconductor mesa is made of a material different from or the same as a material of the substrate.
14. The three-dimensional memory of claim 13, the semiconductor mesa being a single crystal structure.
15. The three-dimensional memory according to claim 7, wherein the bottom of the gate/dielectric layer stack is the same as the top of the patterned hard mask layer.
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