CN108630691A - Three-dimensional storage and its manufacturing method - Google Patents
Three-dimensional storage and its manufacturing method Download PDFInfo
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- CN108630691A CN108630691A CN201810249952.5A CN201810249952A CN108630691A CN 108630691 A CN108630691 A CN 108630691A CN 201810249952 A CN201810249952 A CN 201810249952A CN 108630691 A CN108630691 A CN 108630691A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention discloses a three-dimensional storage and its manufacturing methods, including form hard mask layer and graphical on substrate；Using hard mask figure, semiconductor boss is formed on substrate；Doped region is formed at the top of semiconductor boss；Dielectric layer is formed on hard mask figure and semiconductor boss to stack；Etch media layer heap is folded, forms the vertical-channel hole of exposure semiconductor boss.According to the three-dimensional storage manufacturing method of the present invention, first form the raceway groove hole re-formed after doping boss during dielectric layer stacks on substrate using hard mask figure, improve the quality of forming film of raceway groove hole bottom boss, the uniformity of height and doping concentration, vertical channel region growth defect is reduced, the reliability of device is improved.
Description
Technical field
The present invention relates to a kind of three-dimensional storage and its manufacturing methods, more particularly to a kind of three-dimensional NAND gate memory list
First transistor and its manufacturing method.
Background technology
In order to improve the density of memory device, industry is dedicated to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
It writes and increases, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory devices, industry to grind
The memory device with three-dimensional (3D) structure has been sent out, it is integrated to improve by the way that memory cell is three-dimensionally disposed in substrate
Density.
Typical 3D NAND manufacturing process is as shown in Figure 1a, and multiple dielectric layers are deposited on the substrate 1 of usually Si and are stacked
The laminated construction 2 (such as oxide and the alternate structure of nitride) of composition；By anisotropic etching technics on substrate 1
Multi-layer laminate structure 2 is etched and is formed along the distribution of memory cell wordline (WL) extending direction, perpendicular to the more of substrate surface
A raceway groove hole 2H (can go directly substrate surface or have certain over etching)；The materials such as deposit polycrystalline silicon are formed in the 2H of raceway groove hole
Column raceway groove (is not shown) below；The groove that the substrate that goes directly is formed along the directions WL etching multi-layer laminate structure 2, exposes and surrounds
It is multilayer laminated around column raceway groove；Wet method remove in lamination a certain types of material (such as hot phosphoric acid removes silicon nitride, or
HF removes silicon), the raised structures of cross direction profiles are left around column raceway groove；The side wall deposition of raised structures in the trench
Gate dielectric layer (such as high K medium material) and grid conducting layer (such as Ti, W, Cu, Mo etc.) form grid conducting layer, example
Such as include bottom selection grid polar curve, dummy gate electrode line, wordline, top selection grid polar curve；Perpendicular magnetic anisotropy etching removal protrusion
Grid conducting layer except side plane, until exposing the gate dielectric layer of protrusion side；Etching stack structure forms source and drain contact
And complete back end fabrication.
Among this process, in order to improve the driving capability of bottom driving transistor, it usually needs increase bottom selection grid
Overlapping area between polar curve and bottom selection transistor active area especially channel region.A kind of typical scheme is as shown in Figure 1 b,
Etching formed after the 2H of raceway groove hole, cleaning, over etching exposure 1 surface of substrate with remove the raceway groove hole bottoms 2H non-crystalline material or
The defect of native oxide, be then epitaxially-formed in the 2H of raceway groove hole preferably monocrystal material multiple boss 1E (such as
Silicon island) and then ion implantation doping (as shown in the dotted line frame of Fig. 1 b), it is high for use as the vertical channel region of selection transistor
Degree more than several sublayers (such as to the 1/3 of bottom thick silicon oxide layer thickness at) of 2 bottom of dielectric stack to increase with not
To select the overlapping area between grid line.
However, in actual process manufacturing process, due to the depth-to-width ratio of raceway groove hole 2H it is excessive (be greater than equal to 10,
20), the Defect removal of bottom is difficult, and the quality of forming film of epitaxial growth boss 1E is not good enough, and boss height as shown in Figure 1 b is not
Unanimously, the defect in bottom in the presence of cavity, or at the top of boss 1E causes the vertical furrow channel layer growth defect mistake formed later
Greatly.In addition, during ion implantation doping, since raceway groove hole 2H depth-to-width ratios are excessive, ion implanting range farther out, if injection
The degree control of technique is bad, then considerable fraction of ion will be incident on 2 side wall of laminated construction, thus influences lamination knot
Etch selectivity between 2 each sublayer of structure so that the active area off-design of bottom selection transistor is laid out, or due to note
Enter energy not enough and the boss 1E of the raceway groove hole bottoms 2H can not be reached.
Invention content
Therefore, it is an object of the invention to overcome drawbacks described above, improve the quality of forming film of raceway groove hole bottom boss, height and
The uniformity of doping concentration reduces vertical channel region growth defect, improves the reliability of device.
For this purpose, the present invention provides a kind of three-dimensional storage manufacturing methods, including：
Patterned hard mask layer is formed on substrate, and the patterned hard mask layer has expose substrate first to hang down
Straight flute road hole, first vertical-channel are formed with semiconductor boss in hole；
Doped region is formed at the top of the semiconductor boss；
Dielectric layer laminated construction is formed on the patterned hard mask layer and the semiconductor boss；
The dielectric layer laminated construction is etched, the second vertical-channel hole of the exposure semiconductor boss is formed.
Wherein, hard mask layer includes at least the first hard mask layer and the second hard mask layer；Optionally, hard mask layer is further
It include the third hard mask layer on the first and/or second hard mask layer；Preferably, it the first hard mask layer and/or second covers firmly
The material of mold layer and/or third hard mask layer is selected from silica, silicon nitride, silicon oxynitride, amorphous carbon, non-crystalline silicon, diamond-like
Any one or combinations thereof of amorphous carbon, germanium oxide, aluminium oxide, low-k materials.
Wherein, the top of the patterned hard mask layer is higher than the top of the semiconductor boss.
Wherein, the step of forming semiconductor boss further comprises：
Etch hard mask layer forms the first vertical-channel hole of exposure substrate；
Deposited semiconductor layer in first vertical-channel hole and on patterned hard mask layer；
The semiconductor layer is planarized until the exposure patterned hard mask layer.
Further comprise after forming the first vertical-channel hole, before deposited semiconductor layer, corrosion substrate forms periodicity
Pattern and/or execution over etching.
Wherein, the step of forming semiconductor boss further comprises：
Stop-layer is formed on hard mask layer；
The hard mask layer and stop-layer are etched, the first vertical-channel hole of exposure substrate is formed；
Deposited semiconductor layer in first vertical-channel hole and on patterned stop-layer；
The semiconductor layer is planarized until the exposure patterned stop-layer；
Remove the stop-layer；
Planarizing the semiconductor boss makes the semiconductor layer be flushed with patterned hard mask layer.
Wherein, the step of forming doped region further comprises：
Doping in situ is carried out while forming semiconductor boss；Or
It forms semiconductor boss and carries out ion implantation doping later.
Wherein, the width in vertical-channel hole is less than the width of semiconductor boss.
Wherein, the material of semiconductor boss and the material of substrate are similar and different；Optionally, semiconductor boss is monocrystalline knot
Recrystallization processing is carried out after structure, or the semiconductor boss of formation polycrystalline structure, before forming doped region to be changed into monocrystalline
Structure.
Wherein, semiconductor boss surface is cleaned after formation semiconductor boss, before forming doped region.
Wherein, the bottom of the dielectric layer laminated construction is identical as the top material of patterned hard mask layer.The
The present invention also provides a kind of three-dimensional storage, feature exists in one vertical-channel hole the first vertical-channel hole the first vertical-channel hole
In, including：
Patterned hard mask layer stacks, and is located on substrate；
Grid/dielectric layer laminated construction, it is stacked on positioned at the patterned hard mask layer heap, including stack gradually multiple
Dielectric layer between gate stack and neighboring gates stack stacks；
First vertical-channel hole passes through the patterned hard mask layer to stack, and semiconductor boss is formed in described first
In vertical-channel hole；
Second vertical-channel hole passes through the grid/dielectric layer laminated construction, and it is vertical that vertical furrow channel layer is located at described second
In raceway groove hole.
Wherein, the semiconductor boss is than the vertical-channel slice width.
Wherein, the patterned hard mask layer, which stacks, includes at least the first hard mask layer and the second hard mask layer；Optionally
Ground, the patterned hard mask layer stacking further comprise the third hard mask layer on the first and/or second hard mask layer；
Preferably, the first hard mask layer and/or the material of the second hard mask layer and/or third hard mask layer be selected from silica, silicon nitride,
Any one or its group of silicon oxynitride, amorphous carbon, non-crystalline silicon, diamond-like amorphous carbon, germanium oxide, aluminium oxide, low-k materials
It closes.
Wherein, the top that the patterned hard mask layer stacks is higher than the top of the semiconductor boss.
Wherein, the top of the semiconductor boss has doped region.
Wherein, the material of the semiconductor boss and the material of substrate are similar and different；Optionally, the semiconductor boss
For mono-crystalline structures.
Wherein, the top material phase of the bottom of the grid/dielectric layer laminated construction and the patterned hard mask layer
Together.
According to the three-dimensional storage manufacturing method of the present invention, first formed on substrate using hard mask figure doping boss it
The raceway groove hole during dielectric layer stacks is re-formed afterwards, improves the equal of the quality of forming film of raceway groove hole bottom boss, height and doping concentration
Even property reduces vertical channel region growth defect, improves the reliability of device.
Purpose of the present invention, and other purposes unlisted herein, in the range of the application independent claims
It is satisfied.The embodiment of the present invention limits in the independent claim, and specific features limit in dependent claims thereto.
Description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 a and Fig. 1 b respectively illustrate the diagrammatic cross-section that the prior art makes 3D memory process；
Fig. 2 a to Fig. 2 i respectively illustrate cuing open for each step of process for fabrication of semiconductor device according to the ... of the embodiment of the present invention
Face schematic diagram；And
Fig. 3 shows the schematic flow chart of process for fabrication of semiconductor device according to the ... of the embodiment of the present invention.
Specific implementation mode
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the novel three-dimensional memory manufacturing that can effectively improve 3D nand memory part channel region quality of forming film.
It should be pointed out that similar reference numeral indicates similar structure, term use herein " first ", " second ",
"upper", "lower" etc. can be used for modifying various device architectures.These modifications do not imply that modified device junction unless stated otherwise
Space, order or the hierarchical relationship of structure.
As shown in figure 3, describing the schematic flow of three-dimensional storage manufacturing method according to an embodiment of the invention
Figure.It forms hard mask and graphical on substrate first, boss is formed on substrate followed by patterned hard mask, formed
The vertical active area to form bottom selection transistor is adulterated to boss during boss and/or after formation boss, then hard
The stacking that multiple medium sublayers are constituted is formed on mask graph and boss, then etch media layer heap is folded forms vertical substrates distribution
Multiple raceway groove holes.Hereafter the vertical furrow channel layer of deposit polycrystalline or monocrystal material composition 3D NAND devices in raceway groove hole, is hanging down
Dielectric layer between straight flute road forms deep hole in stacking, and the Part Sublayer during dielectric layer stacks is removed by deep hole selective etch
And lateral recesses are left, gate dielectric layer and grid conducting layer are formed in lateral recesses, and common source area is formed in deep hole bottom,
Drain electrode is formed at the top of vertical furrow channel layer, is finally completed the manufacture of 3D memories.
In this way, then basic procedure shown in Fig. 3 is formed by first adulterating boss formation active area in stacked media layer
Vertical-channel carries out extension and/or injection technology without the big raceway groove hole of depth-to-width ratio is needed guiding through, improves the quality of forming film of boss,
Reduce process costs.
The concrete technology flow process described in Fig. 3 is described in detail below in conjunction with Fig. 2 a- Fig. 2 i.
As shown in Figure 2 a, hard mask layer is formed on substrate 10 to stack.Substrate 10 is provided, material may include body silicon
(bulk Si), body germanium (bulk Ge), silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compounds are partly led
Body substrate, such as SiGe, Si:C, the combination of SIGeC, GaN, GaAs, InP etc. and these substances.In order to existing IC
Manufacturing process is compatible with, and substrate 10 is preferably the substrate containing silicon material, such as Si, SOI, SiGe, Si:C, SiGeC etc..
Using including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemistry
The common process such as oxidation form hard mask layer stacking on substrate 10.In a preferred embodiment of the invention, hard mask layer heap
Folded includes multiple sublayers, includes at least a first hard mask layer 11a, preferably further includes at least one second hard mask layer
The material of 11b, layer 11a and layer 11b are mutually different to provide larger Etch selectivity, such as selected from silica, silicon nitride, nitrogen
Either one or two of silica, amorphous carbon, non-crystalline silicon, diamond-like amorphous carbon (DLC), germanium oxide, aluminium oxide or combinations thereof.One
In a preferred embodiment, the material of the first hard mask layer 11a is, for example, silica, and preferably thermal oxidation technology is formed, thinner thickness
Such as only 0.2 to 1nm, it is used as the liner protective layer of etched substrate；The material of second hard mask layer 11b is, for example, silicon nitride, excellent
Pecvd process is selected to be formed, thickness is thicker by such as 5 to 50nm, is used as the main hard mask layer of etched substrate.
In an improvement to the present invention, hard mask layer stacking also optionally (also can not include) further packet
At least one third hard mask layer 11c is included, material is different from the second adjacent hard mask layer 11b (if any, if do not had
Have a layer 11b, then layer 11c materials are different from layer 11a), it is preferable that the material is soft for third hard mask layer to absorb cmp planarization mistake
Stress in journey simultaneously promotes defect to concentrate on avoiding boss impaired in third hard mask layer, such as its material is silica or low
K materials.Wherein low-k materials include but not limited to organic low-k materials (such as organic polymer containing aryl or polynary ring), nothing
Machine low-k materials (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material
(such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous silica, porous SiOCH, mix that C silica, to mix F porous
Amorphous carbon, porous diamond, porous organic polymer).Third hard mask layer 11c in subsequent planarization technique for protecting
Not by overmastication at the top of boss, it is therefore desirable to control its deposition thickness and make top higher than the top for ultimately forming boss, example
As the thickness of third hard mask layer 11c and the sum of the thickness of hard mask layer 11a and/or 11b are more than or equal to the final height of boss 10a
It spends (referring to Fig. 2 f).In a preferred embodiment of the invention, third hard mask layer 11c thickness be 20 to 200nm, preferably 30 to
150nm, preferably 50 to 100nm.
In an other improvement, it (also can not include) optionally further including that hard mask layer, which stacks top,
At least one polish stop layer or anti-reflecting layer 11d.Layer 11d materials are harder, for example, silicon nitride, silicon oxynitride, DLC etc., use
In the soft third hard mask layer 11c or sub- mask layer 11a/11b during subsequent CMP flatening process below protection, also may be used
With simultaneously for absorbing excessive light radiation during follow-up photoetching to improve exposure, development precision.Layer 11d materials are relatively thin,
Such as 1 to 10nm.
Photoresist layer is formed at the top of above-mentioned hard mask layer stacking and exposure imaging forms photoetching offset plate figure 12.Figure 12 it
Between gap or opening control the pattern of the following boss namely the vertical active area of bottom selection transistor, such as in a top view
Shape can be rectangle, rectangular, diamond shape, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, eight
The various geometries of side shape etc..
As shown in Figure 2 b, it is mask with photoetching offset plate figure 12, is sequentially etched each hard mask sublayer of hard mask layer stacking
It forms patterned hard mask layer to stack, multiple first vertical-channels hole 11e on 10 surface of exposure substrate.It is preferred that using each to different
Property etching technics, such as (use CxHyFzEqual fluorohydrocarbons etching gas) dry plasma etch or reactive ion etching etc. respectively to
Anisotropic dry etch process.Preferably, micro over etching is executed, such as gos deep into 10 surface 0.2 of substrate to 1nm, to ensure completely
The various defects on 10 surface of substrate are removed such as native oxide, crack, contaminant particle.It is further preferred that using wet
10 surface of method etching process (such as TMAH be directed to Si) etched substrate formed multiple periodic patterns (such as periodical micro-pits or
Microprotrusion (not shown), the array of such as raised or sunken composition, single pattern dimension such as 0.1 to 1.5nm, between pattern
Spacing such as 3 to 10nm) for use as follow-up CVD deposition or the nucleation structure of epitaxial growth, further increase film growth quality.
Then, wet etching or dry oxidation remove photoetching offset plate figure 12 to expose the top of hard mask lamination.
As shown in Figure 2 c, semiconductor layer 10a is formed on entire device, is filled up completely multiple first vertical-channels hole 11e
And cover hard mask stacking.Preferably, by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, simultaneously
And conformality and the good depositing operation of step coverage are in the first vertical-channel hole 11e preferably wherein and hard mask stacks
Deposited on top semiconductor layer 10a.Semiconductor layer 10a materials can be identical or different with substrate 10, for example, silicon, Zhe Deng IV races
Simple substance can also be selected from IV races, iii-v or II-VI group compound semiconductor, such as SiGe, Si:C、SiGe:C、Ge、
GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs etc. and combinations thereof.Preferably, semiconductor layer 10a materials and substrate 10
Difference applies stress to be mismatched using lattice to channel region, to improve the driving capability of selection transistor.Preferably, directly
It is mono-crystalline structures to improve the quality of forming film of the following boss to meet deposited semiconductor layer 10a, or is formed with film formation at low temp technique more
Crystal layer and then laser short annealing make illuminated region (such as region between patterned hard mask stacking) again
Crystallization become local monocrystalline or the larger polycrystalline structure of domain to during avoiding monocrystalline from forming a film excessively high technological temperature for crystalline substance
On piece has other devices and brings heat budget problem.As shown in Figure 2 c, since hard mask stacks the presence of figure, deposition is partly led
Body layer 10a will be at the top of patterned hard mask stacking with protrusion and with recess between figure.
It is therefore preferred that using flatening process shown in Fig. 2 d, such as chemically-mechanicapolish polish (CMP) or be etched back to work
Skill so that semiconductor layer 10a stacks top with patterned hard mask layer and flushes, namely exposes patterned hard mask layer and stack
Top.In the case where patterned hard mask layer stacking includes polish stop layer 11d, CMP processing will be due to the hardness of layer 11d
It is significantly higher than semiconductor layer 10a and is automatically stopped at 11 top of layer.So, it can be advantageous to reduce on chip between different zones
The inhomogeneities of semiconductor layer 10a fillings.
Then, optionally, as shown in Figure 2 e, using wet etching removal polish stop layer 11d.For example, using hot phosphoric acid
The layer 11d for removing silicon nitride, using the group of strong acid (nitric acid, sulfuric acid) and strong oxidizer (hydrogen peroxide, deionized water ozoniferous)
Removal silicon oxynitride or the layer 11d etc. of DLC are closed, until the structure below exposed surface 11d, such as third hard mask layer 11c is (such as
If fruit has).In this way, exposing top and the partial sidewall of semiconductor layer 10a again, lacked in order to reduce its top later
It falls into.
Then, optionally, as shown in figure 2f, using the flatening process such as CMP make at the top of semiconductor layer 10a with it is remaining
The folded top of patterned hard mask layer heap (such as at the top of layer 11c) flushes.In this way, grinding eliminates one at the top of semiconductor layer 10a
Part, which may too early be closed and there are some holes in thin film growth process due to filling, or by Fig. 2 d institutes
The CMP process shown and there are the micropores that some excessive erosions leave.In the process, due to third hard mask layer 11c materials compared with
Soft, the defects of part of stress is unbalanced or impurity, crack, can preferably occur in third hard mask layer 11c without to half
Conductor layer 10a aggregations, therefore improve the film quality of semiconductor layer 10a.In the process, at the top of third hard mask layer 11c
Also can be removed a part, thus in the initial step shown in Fig. 2 a the thickness of third hard mask layer 11c need it is larger so that
Entire hard mask layer is obtained to stack at the top of the semiconductor layer 10a that top finally leaves higher than Fig. 2 f.
Preferably, remaining impurity at the top of chemical cleaning removal semiconductor layer 10a.For example, by using dHF (dilute hydrofluoric acid)
The either primary thin oxide layer that is formed in technical process before removal or the pollutant that flatening process leaves before
Grain.As a result, semiconductor layer 10a is stayed on 10 surface of substrate and formd multiple boss structures, it is used as subsequently selected crystalline substance
The vertical active area of body pipe.
Then, as shown in Figure 2 g, ion implantation technology is executed, forms doped region 10b (examples at the top of semiconductor boss 10a
Such as part more than dotted line).The energy of control injection ion, avoids the ion bombardment surface of excessive kinetic energy and to improve defect close
Degree.The dosage and type of control injection ion are to obtain the active area of different doping types.In other embodiment of the present invention,
Doping in situ is carried out with regard to dopant is added in unstripped gas simultaneously in deposition process shown in Fig. 2 c, so without additional
Ion implantation technology shown in Fig. 2 g is carried out, it is scarce so as to avoid being increased by plasma bombardment at the top of boss doped region 10b
It falls into.
Hereafter, as shown in fig. 2h, on entire device, especially in semiconductor boss 10b and patterned hard mask
Layer heap is folded on the tops 11a/11b/11c, is formed dielectric layer and is stacked 13a/13b.Using including LPCVD, PECVD, HDPCVD,
The common process such as UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, metallization medium layer stack, including alternately stacked multiple the
One dielectric layer 13a and multiple second dielectric layer 13b, alternately stacked number are preferably greater than or equal to 2 (according in memory cell string
Unit number is needed and is set, for example, 8).First medium layer 13a and second dielectric layer 13b materials are mutually different, such as selected from
Silica, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC), germanium oxide, aluminium oxide etc. it is any and its
Combination.Preferably, the folded top of the first medium layer 13a materials of bottom and patterned hard mask layer heap (such as third hard mask
Layer 11c) material is identical, to improve the bond strength of selection transistor active region dielectric layer, at film uniformity, avoids not
The ON/OFF of selection transistor is influenced with the Defect density charge that interface between material has.
Finally, as shown in fig. 2i, etch media layer heap is folded forms the second vertical-channel hole 13c, until exposure substrate.Using
Anisotropic etch process, such as (use CxHyFzEqual fluorohydrocarbons etching gas) dry plasma etch or reactive ion etching
Etc. anisotropic dry etch process, etching formed across dielectric layer stack 13a/13b trepanning 13c, finally expose semiconductor
The side wall that the tops boss 10b and dielectric layer stack.In vertical view, the cross sectional shape of the second vertical-channel hole 13c can be square
Shape, rectangular, diamond shape, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. are various several
What shape.Preferably, the depth-to-width ratio of the second vertical-channel hole 13c is more than or equal to 5:1,10 are preferably greater than or equal to:1, most preferably 20:
1.In a preferred embodiment of the invention, the second vertical-channel hole 13c width is less than first vertical-channel hole 11e, Ye Jiban
The width of conductor boss 10b so that even if there are channel region and choosings that overlay error also ensures that the strings of transistors of storage unit
The channel region for selecting transistor realizes electrical connection.
Hereafter, similar technique deposited vertical raceway groove can be used in the second vertical-channel hole 13c, in third hard mask layer
Dielectric layer at the top of 11c forms the deep hole of exposure substrate 10 in stacking, common source area is formed in deep hole bottom, etching deep hole side wall
One of first or second dielectric layer 13a/13b leaves recess, fills gate dielectric in the valley and grid conductor forms control gate
(namely the gate stack structure of multiple stackings remains first or second dielectric layer stacking between neighboring gates stacked structure to line
Thus structure collectively forms grid/dielectric layer laminated construction), leakage is formed at the top of the channel region in the second vertical-channel hole 13c
Pole is finally completed device manufacture.
According to the three-dimensional storage manufacturing method of the present invention, first formed on substrate using hard mask figure doping boss it
The raceway groove hole during dielectric layer stacks is re-formed afterwards, improves the equal of the quality of forming film of raceway groove hole bottom boss, height and doping concentration
Even property reduces vertical channel region growth defect, improves the reliability of device.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the preferred forms for realizing the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacturing method is by all embodiments including falling within the scope of the present invention.
Claims (10)
1. a kind of three-dimensional storage manufacturing method, which is characterized in that including：
Patterned hard mask layer is formed on substrate, and the patterned hard mask layer has the first vertical furrow for exposing substrate
Road hole, first vertical-channel are formed with semiconductor boss in hole；
Doped region is formed at the top of the semiconductor boss；
Dielectric layer laminated construction is formed on the patterned hard mask layer and the semiconductor boss；
The dielectric layer laminated construction is etched, the second vertical-channel hole of the exposure semiconductor boss is formed.
2. three-dimensional storage manufacturing method as described in claim 1, which is characterized in that hard mask layer is covered firmly including at least first
Mold layer and the second hard mask layer；Optionally, hard mask layer further comprises that the third on the first and/or second hard mask layer is hard
Mask layer；Preferably, the first hard mask layer and/or the material of the second hard mask layer and/or third hard mask layer be selected from silica,
Any one of silicon nitride, silicon oxynitride, amorphous carbon, non-crystalline silicon, diamond-like amorphous carbon, germanium oxide, aluminium oxide, low-k materials
Or combinations thereof.
3. three-dimensional storage manufacturing method as described in claim 1, which is characterized in that the step of forming semiconductor boss is into one
Step includes：
Etch hard mask layer forms the first vertical-channel hole of exposure substrate；
Deposited semiconductor layer in first vertical-channel hole and on patterned hard mask layer；
The semiconductor layer is planarized until the exposure patterned hard mask layer；Alternatively,
The step of forming semiconductor boss further comprises：
Stop-layer is formed on hard mask layer；
The hard mask layer and stop-layer are etched, the first vertical-channel hole of exposure substrate is formed；
Deposited semiconductor layer in first vertical-channel hole and on patterned stop-layer；
The semiconductor layer is planarized until the exposure patterned stop-layer；
Remove the stop-layer；
Planarizing the semiconductor boss makes the semiconductor layer be flushed with patterned hard mask layer.
4. three-dimensional storage manufacturing method as described in claim 1, which is characterized in that wherein, the dielectric layer laminated construction
Bottom it is identical as the top material of patterned hard mask layer.
5. a kind of three-dimensional storage, which is characterized in that including：
Patterned hard mask layer stacks, and is located on substrate；
Grid/dielectric layer laminated construction is located at the patterned hard mask layer heap multiple grids that are stacked on, including stacking gradually
The dielectric layer stacked between neighboring gates stacking stacks；
First vertical-channel hole passes through the patterned hard mask layer to stack, and it is vertical that semiconductor boss is formed in described first
In raceway groove hole；
Second vertical-channel hole passes through the grid/dielectric layer laminated construction, vertical furrow channel layer to be located at second vertical-channel
Kong Zhong.
6. three-dimensional storage according to claim 5, which is characterized in that the semiconductor boss is than the vertical furrow channel layer
It is wide.
7. three-dimensional storage according to claim 5, which is characterized in that the patterned hard mask layer stacking is at least wrapped
Include the first hard mask layer and the second hard mask layer；Optionally, the patterned hard mask layer stacking further comprises first
And/or the second third hard mask layer on hard mask layer；Preferably, the first hard mask layer and/or the second hard mask layer and/or
The material of three hard mask layers is selected from silica, silicon nitride, silicon oxynitride, amorphous carbon, non-crystalline silicon, diamond-like amorphous carbon, oxygen
Change any one or combinations thereof of germanium, aluminium oxide, low-k materials.
8. three-dimensional storage according to claim 5, which is characterized in that the top of the semiconductor boss has doping
Area.
9. three-dimensional storage according to claim 5, which is characterized in that the material of the material and substrate of the semiconductor boss
Matter is similar and different；Optionally, the semiconductor boss is mono-crystalline structures.
10. three-dimensional storage according to claim 5, which is characterized in that the bottom of the grid/dielectric layer laminated construction
It is identical as the top material of patterned hard mask layer.
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