CN109727995A - Form the method and three-dimensional storage of three-dimensional storage - Google Patents
Form the method and three-dimensional storage of three-dimensional storage Download PDFInfo
- Publication number
- CN109727995A CN109727995A CN201910151716.4A CN201910151716A CN109727995A CN 109727995 A CN109727995 A CN 109727995A CN 201910151716 A CN201910151716 A CN 201910151716A CN 109727995 A CN109727995 A CN 109727995A
- Authority
- CN
- China
- Prior art keywords
- layer
- well region
- channel
- dimensional storage
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of methods and three-dimensional storage for forming three-dimensional storage, the three-dimensional storage includes a kind of three-dimensional storage, including substrate, doped well region, the stack layer on the substrate and the channel structure for passing perpendicularly through the stack layer and the arrival well region.The doped well region is located in the substrate, the well region and the substrate contact.The stack layer includes the grid layer at interval.The channel structure includes channel layer, wherein the part that the channel layer is located at the well region is exposed from the side of the channel structure, to contact with the well region.The present invention, can be to avoid the counter productive of this technology due to that need not form silicon epitaxy layer in channel hole bottom.
Description
Technical field
The invention mainly relates to semiconductor making methods, are particularly to the formation of the method and three-dimensional storage of three-dimensional storage
Device.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been researched and developed and scale of mass production has three-dimensional (3D) structure
Memory device, improve integration density by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core with channel structure
(core) area.Channel structure is formed in the channel hole for the stack layer (stack) for extending vertically through three-dimensional storage part.Channel bottom hole
Silicon epitaxy layer is arranged so as to connection ditch channel layer and substrate in portion.However in conventional technique, the etching in channel hole can be to the silicon of bottom
Material causes to damage, to affect the quality in the silicon epitaxy layer of bottom grown.Also, silicon epitaxy layer is easy by channel hole
The influence of distribution.
A kind of improved method but is exposed channel layer from channel hole side wall without using silicon epitaxy layer, is adulterated using N
Polysilicon channel layer side wall is electrically connected to array common source (ACS) as source electrode line.However, this structure is in source electrode line
Place is to use holes as majority carrier (majority-carrier), leads to not carry out FN (Fowler Nordheim again
Tunneling it) wipes.As such, it is desirable to be come using GIDL (Gate Induced Drain Leakage, the electric leakage of grid induced drain)
Induce hole erasing.This mode speed is slower, especially in the higher level of three-dimensional storage part.
Summary of the invention
The present invention provides a kind of method and three-dimensional storage for forming three-dimensional storage, it is not necessary to form silicon in channel hole
Epitaxial layer, and GIDL need not be used.
One aspect of the present invention proposes a kind of three-dimensional storage, including substrate, doped well region, is located at the substrate
On stack layer and pass perpendicularly through the stack layer and reach the channel structure of the well region.The doped well region is located at
In the substrate, the well region and the substrate contact.The stack layer includes the grid layer at interval.The channel structure includes
Channel layer, wherein the part that the channel layer is located at the well region is exposed from the side of the channel structure, thus with the trap
Area's contact.
In one embodiment of this invention, the part that the channel layer exposes from the side is cylindrical surface.
In one embodiment of this invention, the well region includes silicon epitaxy layer, and the channel layer connects with the silicon epitaxy layer
Touching.
In one embodiment of this invention, three-dimensional storage further includes the array common source for passing perpendicularly through the stack layer,
The well region and the array common source are electrically connected, wherein being equipped with contact zone between the well region and the array common source.
In one embodiment of this invention, the grid layer includes bottom selection grid, and the channel layer extends to the bottom
The position of portion's selection grid.
In one embodiment of this invention, the well region is p-type doping.
In one embodiment of this invention, the stack layer includes the storehouse of a storehouse or multiple stackings.
The present invention also proposes a kind of method for forming three-dimensional storage, comprising the following steps: semiconductor structure is provided, it is described
Semiconductor structure has substrate, doped initial well region, the sacrificial layer on the substrate, position in the substrate
In the stack layer on the sacrificial layer and pass perpendicularly through the channel structure of the stack layer, wherein the initial well region with it is described
Substrate contact, the channel structure reach the initial well region and have channel layer；Formation passes perpendicularly through the stack layer and arrives
Up to the grid line gap of the sacrificial layer；The sacrificial layer is removed, exposes the channel structure in the side wall of the part of the sacrificial layer,
Gap is formed between the stack layer and the initial well region；The channel structure is removed in the partial sidewall of the sacrificial layer
Thickness exposes a part of the channel layer；And the initial well region is expanded into the gap and becomes final well region, institute
State a part that final well region contacts the channel layer.
In one embodiment of this invention, the part that the channel layer exposes is cylindrical surface.
In one embodiment of this invention, the step of initial well region being expanded into the gap and becoming final well region
It include: some growth silicon epitaxy layer from the exposing of the initial well region and the channel layer.
In one embodiment of this invention, in the step of growing silicon epitaxy layer, the silicon epitaxy layer is at the grid line gap
With recess.
In one embodiment of this invention, the above method further include: form contact zone on the final well region；And
Array common source is formed in the grid line gap, the array common source contacts the contact zone.
In one embodiment of this invention, the stack layer includes the storehouse of a storehouse or multiple stackings.
In one embodiment of this invention, the well region is p-type doping.
In three-dimensional storage of the invention and forming method thereof, since silicon epitaxy layer need not be formed in channel hole bottom,
Can be bad to avoid the counter productive of this technology, such as channel hole bottom pattern, silicon epitaxy layer is easy by channel pore size distribution
Influence etc..Moreover, three-dimensional storage of the invention and forming method thereof is not using N impure source line but is adulterated with P
Well region is electrically connected, because of the GIDL without using erasing operation slower, to maintain erasing operation speed.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is a kind of core space diagrammatic cross-section of three-dimensional storage.
Fig. 2 is the core space diagrammatic cross-section of three-dimensional storage part according to an embodiment of the invention.
Fig. 3 is the core space diagrammatic cross-section of three-dimensional storage part according to another embodiment of the present invention.
Fig. 4 is the method flow diagram of the formation three-dimensional storage of one embodiment of the invention.
Fig. 5 A-5G is the diagrammatic cross-section in the example process of the formation three-dimensional storage of one embodiment of the invention.
Fig. 6 A-6C is in the example process of the initial semiconductor structure of the formation three-dimensional storage of one embodiment of the invention
Diagrammatic cross-section.
Fig. 7 A-7C is cuing open in the example process of the partial sidewall thickness of the removal channel structure of one embodiment of the invention
Face schematic diagram.
Fig. 8 A-8G is the diagrammatic cross-section in the example process of the formation three-dimensional storage of one embodiment of the invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
The embodiment of the present invention describes to form the method for three-dimensional storage and three-dimensional storage, it may not be necessary in channel hole
Middle formation silicon epitaxy layer, and GIDL need not be used.
The channel hole bottom of conventional three-dimensional memory is provided through outside the silicon of selective epitaxial growth (SEG) technique formation
Prolong layer, expect to have a kind of technique without the silicon epitaxy layer in channel hole, to avoid its negative effect.
Fig. 1 is a kind of core space diagrammatic cross-section of three-dimensional storage.Fig. 1 uses SCF (Single Channel
Formation) method, i.e., for the channel hole of Multilayer stack, the first channel hole etches and after the completion of interim sacrificial layer filling, shape
At conductive pattern between stack, then the etching in the second channel hole is carried out, after removing sacrificial layer, the first, second channel hole is filled simultaneously.Such as
Shown in Fig. 1, three-dimensional storage 100 may include substrate 11, lower stack 12 and upper layer stacks 13 in core space.Lower stack 12
It is stacked gradually on substrate 11 with upper layer stacks 13.Multiple (4 are shown in figure) pass through perpendicular to the channel structure 14 of substrate
Lower stack 12 and upper layer stacks 13.Channel structure 14 may include memory layer 14a and channel layer 14b.Here, memory layer
14a may include barrier layer, electric charge capture layer and tunnel layer.Channel structure 14 reaches substrate 11, but ditch after passing through lower stack 12
Channel layer 14b in road structure 14 no longer passes through silicon epitaxy layer and substrate 14 is electrically connected, but is stored by a layer 14a isolation.
As replacement, a load reservoir layer is eliminated in the side wall of channel structure 14 and exposes a part of channel layer 14b.E.g. N
Channel layer 14b is connected to array common source 16 by the source electrode line 15 that the polysilicon of doping is constituted.Source electrode line 15 passes through insulating layer 17
It is isolated with substrate 11.Although this structure need not form silicon epitaxy layer in channel hole bottom, it is the introduction of new problem.Source electrode
It is not available hole in line 15 as majority carrier (majority-carrier), leads to not carry out FN erasing again.In this way,
It needs to induce hole to wipe using GIDL (Gate Induced Drain Leakage, the electric leakage of grid induced drain), this side
The erasing speed of formula is slower compared with usual manner, such as FN erasing.
The embodiment of the present invention describes a kind of three-dimensional storage, can solve the problems, such as existing three-dimensional storage.
Three-dimensional storage may include array area (array), and array area may include core space (core) and wordline bonding pad.Core space is packet
The region of storage unit is included, wordline bonding pad is the region for including wordline connection circuit.Wordline bonding pad is typically ladder
(stair step, SS) structure.It is to be understood that the limitation of this and non-present invention.Wordline bonding pad can use other completely
Structure, such as flat structures.In terms of vertical direction, array area can have substrate and stack layer, the shape on the stack layer of core space
At there is channel hole array.Fig. 2 is the core space diagrammatic cross-section of three-dimensional storage 200 according to an embodiment of the invention.Such as Fig. 2
Shown, three-dimensional storage 200 may include substrate 201, well region 202 and stack layer 210.Well region 202 be located in substrate 201 and with lining
Bottom 201 contacts.Substrate 201 and well region 202 are all by the first doping.First doping e.g. p-type doping.Stack layer 210 is located at
On substrate 201.There are the position of well region 202, stack layer 210 can be located on well region 202.Stack layer 210 includes interval
Multiple grid layers 211.It can for example be separated by insulating layer 212 between adjacent grid layer in multiple grid layers 211.Grid layer
211 number of plies is related with the number of plies of three-dimensional storage 200.
There are multiple channel holes 213 in stack layer 210.There is channel layer 215 in each channel hole 213.For charge-trapping
For type flash memory (CTF), there are also memory layers 214 in each channel hole 213.Memory layer 214 may include along channel hole 213
Radial barrier layer, electric charge capture layer and the tunnel layer being arranged from outside to inside.Can also there are filled layer 216, position in each channel hole 213
In in channel layer 215.It will be understood, however, that filled layer 216 can be omitted.Such as channel layer 215 can be in the diameter in channel hole 213
Space occupied by current filled layer 216 is filled up to expanding to.Also there is conductive part 217 at each 213 top of channel hole.This leads
Electric portion 217 is located on channel layer 215, and contacts with channel layer 215.In an embodiment of the present invention, channel hole 213 can be circle
Cylindrical hole, although being not intended as limiting.
Structure formed in channel hole 213 is referred to here as channel structure.Entire channel structure passes perpendicularly through stack layer 210
And reach well region 202.The part 215a that channel layer 215 is located at well region 202 exposes from the side of channel structure, thus and well region
202 contacts.In the present embodiment, the part 215a that channel layer 215 exposes from channel structure side is cylindrical surface, can be risen in this way
To preferable contact effect.It will be appreciated that the part 215a of channel layer may be other profiles.On the other hand, three-dimensional
Memory 200 includes the array common source 220 for passing perpendicularly through stack layer 210, and array common source 220 is contacted with contact zone 203, connect
Touching area 203 is then contacted with well region 202.In this way, forming channel layer 215, well region 202, contact zone 203 when place gate turn-on
To the current path of array common source 220.Here, contact zone 203 is to be equipped with N between well region 202 and array common source 220
Adulterate contact zone.It is appreciated that array common source 220 can be completely cut off by the side wall of insulating layer 222 and stack layer 210.
In the present embodiment, well region 202 is p-type doping, is to be electrically connected between such channel layer 215 and well region 202.Cause
The memory of this present embodiment can provide hole as majority carrier, so as to carry out FN erasing.
With continued reference to shown in Fig. 2, include in grid layer 211 bottom selection grid (bottom select gate, BSG)
211a.In the present embodiment, the structure for the position for corresponding to bottom selection grid 211a in each channel hole 213 is channel layer 215.Also
It is to say, channel layer 215 extends downwardly into the position of bottom selection grid 211a.Since channel layer 215 is electrically to connect with well region 202
Connect, thus the channel of the transistor where the selection grid 211a of bottom be it is L-shaped, extend to well region 202 from channel layer 215.Phase
Than under, in traditional three-dimensional storage, the structure for the position for corresponding to bottom selection grid in each channel hole is silicon epitaxy layer.Fig. 1
Shown in three-dimensional storage, (need to select in bottom since N impure source line 15 can not be electrically connected with channel layer 14b
Can be just connected both when grid are connected), therefore its bottom selection grid is linear.
In an embodiment of the present invention, the exemplary materials of barrier layer and tunnel layer are silica, silicon oxynitride or both
Mixture, the exemplary materials of electric charge capture layer are the multilayered structure of silicon nitride or silicon nitride and silicon oxynitride.Barrier layer,
Electric charge capture layer, tunnel layer can form the multilayer knot for example with silicon oxynitride-silicon-nitride and silicon oxide (SiON/SiN/SiO)
Structure；215 exemplary materials of channel layer are polysilicon.It is to be understood that these layers can choose other materials.For example, barrier layer
Material may include high K (dielectric constant) oxide layer；The material of channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si:
C, the semiconductor materials such as SiGe:C, SiGe:H.
Fig. 2 show the three-dimensional storage with single storehouse.In another embodiment, it is multiple that the present invention, which can also be used,
The three-dimensional storage of storehouse.Fig. 3 is the core space diagrammatic cross-section of three-dimensional storage part according to another embodiment of the present invention.Such as
Shown in Fig. 3, three-dimensional storage 300 may include substrate 301, well region 302, the first storehouse 310 and the second storehouse 320.First storehouse
310 and second storehouse 320 be located on substrate 301 and stack gradually, form stack layer.It is appreciated that storehouse quantity here is only
For citing, there can be more storehouses in actual implementation.First storehouse 310 includes multiple first grid layers 311 at interval.It is multiple
It can for example be separated by the first insulating layer 312 between adjacent first grid layer 311 in first grid layer 311.Similarly, second
Storehouse 320 includes the second grid layer 321 at interval.In multiple second grid layers 321 between adjacent second grid layer 321 for example
It can be separated by second insulating layer 322.The layer of the number of plies of first grid layer 311 and second grid layer 321 and three-dimensional storage 300
Number is related.
There is multiple first channels hole 313 in first storehouse 310.There is multiple second channels hole in second storehouse 310
323, the corresponding first channel hole 313 in each second channel hole 323.Each second channel hole 323 substantially with one first
Channel hole 313 is aligned.However since technique and used litho machine precision are limited, the first channel hole 313 is relative to second
Channel hole 323 may exist a degree of offset on the extending direction (X-direction in figure) of substrate 301, as shown in Figure 3 that
Sample.Deviant is related with technique/board.There is channel layer 315 in each first channel hole 313 and the second channel hole 323.For electricity
For lotus trap-type flash memory (CTF), there are also memory layers 314 in each first channel hole 313 and the second channel hole 323.Storage
Device layer 314 may include barrier layer, electric charge capture layer and the tunnel layer that the radial direction along the second channel hole 323 is arranged from outside to inside.Often
Can also there be filled layer 316 in a first channel hole 313 and the second channel hole 323, be located in channel layer 315.It will be understood, however, that
Filled layer 316 can be omitted.Such as channel layer 315 can be arrived in the radial expansion in the first channel hole 313 and the second channel hole 323
Fill up space occupied by current filled layer 316.Also there is conductive part 317 at each 323 top of channel hole.This conductive part 317
It is contacted with channel layer 315.
In an embodiment of the present invention, the first channel hole 313 and the second channel hole 323 can be cylindrical hole, although not
As restriction.
With continued reference to Fig. 3, the part 315a that channel layer 315 is located at well region 302 exposes from the side of channel structure, thus with
Well region 302 contacts.On the other hand, three-dimensional storage 300 includes the array for passing perpendicularly through the first storehouse 310 and the second storehouse 320
Common source 330, well region 302 are contacted with contact zone 303, and contact zone 303 is then contacted with well region 302.In this way, working as place gate turn-on
When, form the current path that channel layer 315, well region 302, contact zone 303 arrive array common source 330.Here, contact zone 303 is
N doping contact zone between well region 202 and array common source 220 is appreciated that array common source 330 can pass through insulating layer
332 and first the side wall of storehouse 310 and the second storehouse 320 completely cut off.
In the present embodiment, well region 302 is p-type doping, is to be electrically connected between such channel layer 315 and well region 302.Cause
The memory of this present embodiment can provide hole as majority carrier, so as to carry out FN erasing.
With continued reference to shown in Fig. 3, include in grid layer 311 bottom selection grid (bottom select gate, BSG)
311a.In the present embodiment, the structure for the position for corresponding to bottom selection grid 311a in each channel hole 313 is channel layer 315.Also
It is to say, channel layer 315 extends downwardly into the position of bottom selection grid 311a.Since channel layer 315 is electrically to connect with well region 302
Connect, thus the channel of the transistor where the selection grid 311a of bottom be it is L-shaped, extend to well region 302 from channel layer 315.Phase
Than under, in traditional three-dimensional storage, the structure for the position for corresponding to bottom selection grid in each channel hole is silicon epitaxy layer.Fig. 1
Shown in three-dimensional storage, (need to select in bottom since N impure source line 15 can not be electrically connected with channel layer 14b
Can be just connected both when grid are connected), therefore its bottom selection grid is linear.
Fig. 2 and three-dimensional storage shown in Fig. 3 are charge trap-type memory (CTF), and wherein electric charge capture layer is to pass through
Dielectric layer realizes charge storage.It will be understood, however, that the embodiment of the present invention can also be implemented in floating gate type memory,
Middle electric charge capture layer is realized by floating grid.Electric charge capture layer is for example including polycrystalline silicon material.
Fig. 4 is the flow chart of the formation three-dimensional storage part of one embodiment of the invention.Fig. 5 A-5G is that the present invention first is implemented
The example process schematic diagram of the method for the formation three-dimensional storage part of example.The present embodiment is described below with reference to shown in Fig. 4-5G
The method for forming three-dimensional storage.
In step 402, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for follow-up process to ultimately form three-dimensional storage part.Partly lead
Body structure may include array area, and array area may include core space and wordline bonding pad.In terms of vertical direction, core space has lining
Bottom, in substrate first doping initial well region, the sacrificial layer on substrate, the stack layer on sacrificial layer and
Pass perpendicularly through the channel structure of stack layer.Here, initial well region and substrate contact, channel structure reaches initial well region and has ditch
Channel layer.It is appreciated that stack layer herein may include single or multiple storehouses.
Exemplified semiconductor structure 500a may include substrate 501, the first doping in substrate 501 in fig. 5
Initial well region 502, the sacrificial layer 503 on substrate and the stack layer on sacrificial layer 503 510.502 He of initial well region
There can be stop-layer 504 between sacrificial layer 503.Stack layer 510 can be 512 alternating layer of first material layer 511 and second material layer
Folded lamination.First material layer 511 can be grid layer or dummy gate layer.Second material layer 512 is dielectric layer.Stack layer stack 510
In be equipped with channel structure perpendicular to 501 surface of substrate, including channel layer 515 and conductive part 517, the two is electrically connected to each other.?
This, conductive part 517 can be the polysilicon plug (poly plug) in channel hole 513.Here, 515 bottom of channel layer is not
It is electrically connected by silicon epitaxy layer and initial well region 502.In addition, the bottom of stack layer 510 is for forming bottom selection later
The first material layer 511a of grid.As shown in Figure 5A, channel layer 515 can extend downwardly into the position of first material layer 511a, serve as
The channel of bottom selection grid.
Channel structure may additionally include to be arranged from outside to inside between the channel hole 513 where channel layer 516 and channel structure
Barrier layer, electric charge capture layer and tunnel layer.These layers constitute memory layer 514.Memory layer 514, which can not be, to be arranged in ditch
Dielectric layer in road hole, but the FGS floating gate structure in first material layer 511 in the lateral trench in the first channel hole is set.
Some example details of memory layer 514 are described further below.
In an embodiment of the present invention, the material of substrate 501 is, for example, silicon.The material of initial well region 502 is, for example, silicon.Lining
Bottom 501 and initial well region 502 all can be by the first doping, such as p-type doping.Sacrificial layer 503 may be selected and first material layer 511
There is the material of Etch selectivity with second material layer 512.Such as sacrificial layer 503 can be polysilicon or amorphous silicon.Stop-layer 504
Material is, for example, silica.First material layer 511 and second material layer 512 are, for example, the combination of silicon nitride and silica.With nitrogen
It, can be using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other are suitable for the combination of SiClx and silica
Deposition method successively replaces deposited silicon nitride and silica on substrate 501, forms stack layer 510.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.For example, can basis in substrate
Need to form various well regions；Filled layer 516 can be also equipped in channel layer 515.Filled layer 516 can play the role of supporter.
The material of filled layer 516 can be silica.Filled layer 516 can be it is solid, under the premise of not influencing device reliability
It is also possible to hollow.In addition, the material for each layer illustrated is only exemplary, such as substrate 501 can also be other
Siliceous substrate, such as SOI (silicon-on-insulator), SiGe, Si:C etc..
In step 404, the grid line gap for passing perpendicularly through stack layer and reaching sacrificial layer is formed.
In this step, can in the semiconductor structure, the side being formed in perpendicular to substrate extends upward through each of stack layer
Kind grid line gap (Gate Line Slit, GLS), so that core space is divided into multiple pieces of memory blocks and/or refers to memory block.
It is formd on semiconductor structure 500b in figure 5B in the grid line through stack layer 510 perpendicular to substrate 501
Gap 518.Grid line gap 518 reaches sacrificial layer 503, eliminates the segment thickness of sacrificial layer 503.Form the method packet of grid line gap 518
Include the etching to stack layer.Before etching, first the second material layer 512 at the top of stack layer 510 can be thickeied to protect channel
Structure.
In a step 406, sacrificial layer is removed, exposes channel structure in the side wall of the part of sacrificial layer, in stack layer and just
Gap is formed between beginning well region.
In this step, sacrificial layer is removed, forms gap between stack layer and initial well region.Channel structure is sacrificial at this time
The side wall of the part of domestic animal layer exposes in gap.
In semiconductor structure 500c in figure 5 c, removes sacrificial layer and form gap 505.Expose channel in gap 505
Structure the part of sacrificial layer side wall, and expose stop-layer 504.The method for removing sacrificial layer is, for example, wet etching.Here,
Second material layer, stop-layer 504 and the channel structure of the stack layer bottom are on the barrier layer of the lateral wall of the part of sacrificial layer
It can be used as the stop-layer of wet etching.
In a step 408, removal channel structure exposes a part of channel layer in the partial sidewall thickness of sacrificial layer.
In this step, by gap remove channel structure partial sidewall thickness, including barrier layer, electric charge capture layer and
Tunnel layer, to expose a part of channel layer.In this step, blocking can successively be removed by multiple wet etching
Layer, electric charge capture layer and tunnel layer, details are described further below.In this course, stop-layer can be also removed, to reveal
Out well region and the substrate of well region is not covered.In this course, wet etching is used so that well region and substrate exposing, are compared
Using the mode of plasma, the damage to well region and substrate is smaller.
In semiconductor structure 500d in figure 5d, a part of 515a of channel layer 515 is exposed, while exposing well region
502.In this example, the part 515a that channel layer 515 exposes from channel structure side is cylindrical surface.
In step 410, initial well region is expanded into gap and becomes final well region, one of final well region contact channel layer
Point.
In this step, using removal sacrificial layer and the gap that is formed extends initial well region, be allowed to fill up gap, become
The final well region of channel layer can be contacted.In one embodiment, growth technique can be used to extend initial well region.Such as from
The part of the exposing of initial well region and channel layer carry out selective epitaxial growth (Selective Epitaxial Growth,
SEG), silicon epitaxy layer is formed.In another embodiment, the mode of deposition can be used to extend initial well region.
In the semiconductor structure 500e in Fig. 5 E, the final well region 502 ' after extension has been filled with gap, to connect
The part 515a that touching channel layer 515 exposes from channel structure side.In this example, SEG technique can be used in initial well region
Upper growth silicon epitaxy layer, and obtain final well region.Final well region 502 ' has recess 502a at grid line gap 518.Fig. 5 E's
In example, the 502a that is recessed is in the size of substrate extending direction (horizontal direction in figure) and the characteristic size substantially phase of grid line gap 518
Together.In other examples, the silicon epitaxy layer of growth can not have recess 502a, but smooth；Or the silicon epitaxy of growth
Layer can protrude into grid line gap 518；In these examples, extra silicon epitaxy layer can be removed by additional technique.
In step 412, contact zone is formed on final well region.
In this step, the contact zone for being electrically connected with array common source is formed on final well region.Work as stack layer
In when having used dummy gate layer, dummy gate layer can be replaced with into grid layer in the process.
In the semiconductor structure 500f in Fig. 5 F, dummy gate layer is removed, thus between being formed between second material layer 512
Gap.In this step, can also the interface between the second material layer 512 to final well region 502 ' and stack layer bottom carry out
Of short duration heat treatment.In the semiconductor structure 500g in Fig. 5 G, grid layer 511 ' is formed.The material of grid layer is, for example, to nitrogenize
Titanium (TiN) or tungsten (W).High K (dielectric coefficient) oxide layer can be formed between grid layer 511 ' and channel structure.With continued reference to
Fig. 5 G forms contact zone 506 on final well region 502 '.
In step 414, array common source is formed in grid line gap, array common source contacts the contact zone.
In this step, array common source is formed by the path connection raceway groove of contact zone, final well region in grid line gap
Layer.
The semiconductor structure that this step is formed can refer to shown in Fig. 2.
So far, the technique of the channel structure of three-dimensional storage is basically completed.After the completion of these techniques, along with routine
The three-dimensional storage of the embodiment of the present invention can be obtained in technique.For example, when three-dimensional storage is floating gate type memory,
Stack layer 510 is stack, and the first material layer 511 in stack layer is grid layer, is not required to replace by material in step 412
The step of changing.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
Fig. 6 A-6C is in the example process of the initial semiconductor structure of the formation three-dimensional storage of one embodiment of the invention
Diagrammatic cross-section.This example process is described below with reference to Fig. 6 A-6C.
Semiconductor structure 600a as shown in Figure 6A is provided first comprising substrate 501, first in substrate 501
Initial well region 502, the sacrificial layer 503 on substrate and the stack layer on sacrificial layer 503 510 of doping.Initial trap
There can be stop-layer 504 between area 502 and sacrificial layer 503.Stack layer 510 can be first material layer 511 and second material layer 512
Alternately stacked lamination.First material layer 511 can be grid layer or dummy gate layer.Second material layer 512 is dielectric layer.
Then, channel hole 513 is formed in semiconductor structure 600a, as shown in the semiconductor structure 600b of Fig. 6 B.
Then, the channel structure including memory layer 514 and channel layer 515 is formed in channel hole 513, such as the half of Fig. 6 C
Shown in conductor structure 600c.Later, formed in the channel hole of semiconductor structure 600c filled layer 516 and conductive part 517 to get
To the semiconductor structure 500a of Fig. 5 A.
Fig. 7 A-7C is cuing open in the example process of the partial sidewall thickness of the removal channel structure of one embodiment of the invention
Face schematic diagram.This example process is described below with reference to Fig. 7 A-7C.
First as shown in Figure 7 A, the outermost barrier layer 514a of channel structure side wall is removed, to expose electric charge capture layer
514b.The step for can remove stop-layer 504 on initial well region 502 simultaneously, to expose initial well region 502.This step
Suddenly can be by wet etching treatment, in sidewall direction, wet etching can stop at electric charge capture layer 516b；In top surface, wet process
The second material layer 512 of 510 bottom of stack layer can be thinned for etching；In bottom surface, wet etching can leave thin stop-layer 504
Or completely remove stop-layer 504.
Then as shown in Figure 7 B, the electric charge capture layer 514b for removing channel structure side wall, to expose tunnel layer 514c.This
One step can be by wet etching treatment, and in sidewall direction, wet etching can stop at tunnel layer 514c；In top surface, wet process
Etching can rest at the second material layer 512 of 510 bottom of stack layer；In bottom surface, wet etching can rest on remaining stop
Only layer 504 (if there is residual) or rests on initial well region 502.
Then as shown in Figure 7 B, the tunnel layer 514c for removing channel structure side wall, to expose a part of channel layer
515a.The step for can be by wet etching treatment, in sidewall direction, wet etching can stop at a part of 515a of channel layer
Only；In top surface, the second material layer layer 512 of 510 bottom of stack layer is thinned in wet etching；In bottom surface, wet etching can be stopped
On initial well region 502.
Fig. 8 A-8F is the diagrammatic cross-section in the example process of the formation three-dimensional storage of one embodiment of the invention.This
Example process can be used to form the three-dimensional storage part shown in Fig. 3 comprising multiple storehouses.With reference to shown in Fig. 8 A-8F, first
There is provided semiconductor structure 800a as shown in Figure 8 A comprising substrate 801, the first initial trap adulterated in substrate 801
Area 802, the sacrificial layer 803 on substrate and the first storehouse 810 on sacrificial layer 803.Initial well region 802 and sacrifice
There can be stop-layer 804 between layer 803.First storehouse 810 can be alternately laminated for first material layer 811 and second material layer 812
Lamination.First material layer 811 can be grid layer or dummy gate layer.Second material layer 812 is dielectric layer.Here, each layer
The example of material can be with each layer shown in Fig. 6 A of material it is identical, it is not reinflated herein.
Then, it is formed in semiconductor structure 800a across the first channel hole 813 of the first storehouse 510, such as the half of Fig. 8 B
Shown in conductor structure 800b, passes through sacrificial layer 803 and reach initial well region 802.First can be etched in semiconductor structure 800a
Storehouse 810 forms the first channel hole 813.
Then as shown in Figure 8 C, barrier layer is formed in the part that channel hole 813 is located at sacrificial layer 803 and initial well region 802
805, obtain semiconductor structure 800c.Barrier layer 805 can be oxide layer, such as silica.
Later, as in fig. 8d, sacrificial layer 818 is formed in the first channel hole 813, obtains semiconductor structure 800d.It is sacrificial
The material of domestic animal layer 818 can be polysilicon or amorphous silicon.Then the second storehouse 820 is formed on the first storehouse 810.Second heap
Stack 820 is first material layer 821 and the alternately stacked lamination of second material layer 822.Later, it is formed across the second storehouse 820
Second channel hole 823 reaches sacrificial layer 817, and is substantially aligned with the first channel hole 813.
Later, as illustrated in fig. 8e, sacrificial layer 818 is removed, to expose the first channel hole 813, obtains semiconductor structure
800e。
Later, as shown in Figure 8 F, the channel structure including memory layer 814 and channel layer 815 is formed, semiconductor junction is obtained
Structure 800f.Later, filled layer 816 and conductive part 817 are formed in the first channel hole 813 and the second channel hole 823.Here, leading
Electric portion 817 can be polysilicon plug.Optionally, filled layer 816 can be formed in channel layer 815.Filled layer 816 can play support
The effect of object.The material of filled layer 816 can be silica.Filled layer 816 can be solid, be also possible to hollow.
Later, by similar Fig. 5 A-5F the step of, semiconductor structure 800g shown in Fig. 8 G, in this structure, ditch are obtained
The part 815a that channel layer 815 is located at final well region 802 ' exposes from the side of channel structure, to contact with well region 802 '.At this
In embodiment, the part 815a that channel layer 815 exposes from channel structure side is cylindrical surface, can play preferable contact in this way
Effect.It will be appreciated that the part 815a of channel layer may be other profiles.It is total that array is formed in grid line gap 818 later
Source electrode is to be electrically connected channel layer 815 by the path of contact zone 803, well region 802 '.The semiconductor structure that this step is formed can
With reference to shown in Fig. 3.
Other details of three-dimensional storage part, such as wordline bonding pad, periphery interconnection etc., and the emphasis of non-present invention,
This not reinflated description.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3D nand flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (14)
1. a kind of three-dimensional storage, comprising:
Substrate；
Doped well region is located in the substrate, the well region and the substrate contact；
Stack layer on the substrate, the stack layer include the grid layer at interval；
It passes perpendicularly through the stack layer and reaches the channel structure of the well region, the channel structure includes channel layer, wherein institute
It states channel layer and is located at the part of the well region and expose from the side of the channel structure, to be contacted with the well region.
2. three-dimensional storage as described in claim 1, which is characterized in that the channel layer is from the part that the side is exposed
Cylindrical surface.
3. three-dimensional storage as described in claim 1, which is characterized in that the well region includes silicon epitaxy layer, the channel layer
It is contacted with the silicon epitaxy layer.
4. three-dimensional storage as described in claim 1, which is characterized in that further include pass perpendicularly through the stack layer array it is total
Source electrode, the well region and the array common source are electrically connected, and are connect wherein being equipped between the well region and the array common source
Touch area.
5. three-dimensional storage as claimed in claim 3, which is characterized in that the grid layer includes bottom selection grid, the ditch
Channel layer extends to the position of the bottom selection grid.
6. three-dimensional storage as described in claim 1, which is characterized in that the well region is p-type doping.
7. three-dimensional storage as described in claim 1, which is characterized in that the stack layer includes a storehouse or multiple stackings
Storehouse.
8. a kind of method for forming three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure has substrate, the doped initial well region in the substrate, position
In the sacrificial layer on the substrate, the stack layer on the sacrificial layer and the channel junction for passing perpendicularly through the stack layer
Structure, wherein the initial well region and the substrate contact, the channel structure reaches the initial well region and has channel layer；
Form the grid line gap for passing perpendicularly through the stack layer and reaching the sacrificial layer；
The sacrificial layer is removed, exposes the channel structure in the side wall of the part of the sacrificial layer, in the stack layer and institute
It states and forms gap between initial well region；
The channel structure is removed in the partial sidewall thickness of the sacrificial layer, exposes a part of the channel layer；And
The initial well region is expanded into the gap and becomes final well region, the final well region contacts the one of the channel layer
Part.
9. method according to claim 8, which is characterized in that the part that the channel layer exposes is cylindrical surface.
10. method according to claim 8, which is characterized in that the initial well region is expanded to the gap and is become most
The step of whole well region includes:
From some growth silicon epitaxy layer of the exposing of the initial well region and the channel layer.
11. method as claimed in claim 10, which is characterized in that in the step of growing silicon epitaxy layer, the silicon epitaxy layer exists
There is recess at the grid line gap.
12. method according to claim 8, which is characterized in that further include:
Contact zone is formed on the final well region；And
Array common source is formed in the grid line gap, the array common source contacts the contact zone.
13. method according to claim 8, which is characterized in that the stack layer includes the heap of a storehouse or multiple stackings
Stack.
14. method according to claim 8, which is characterized in that the well region is p-type doping.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910151716.4A CN109727995A (en) | 2019-02-28 | 2019-02-28 | Form the method and three-dimensional storage of three-dimensional storage |
| CN201910969274.4A CN110676258B (en) | 2019-01-08 | 2019-10-12 | Three-dimensional memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910151716.4A CN109727995A (en) | 2019-02-28 | 2019-02-28 | Form the method and three-dimensional storage of three-dimensional storage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109727995A true CN109727995A (en) | 2019-05-07 |
Family
ID=66300061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910151716.4A Pending CN109727995A (en) | 2019-01-08 | 2019-02-28 | Form the method and three-dimensional storage of three-dimensional storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109727995A (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110364536A (en) * | 2019-07-23 | 2019-10-22 | 长江存储科技有限责任公司 | The manufacturing method and three-dimensional storage of three-dimensional storage |
| CN110600475A (en) * | 2019-08-26 | 2019-12-20 | 长江存储科技有限责任公司 | Through hole filling method and preparation method of three-dimensional memory |
| CN110896673A (en) * | 2019-06-17 | 2020-03-20 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device using support structure and resulting three-dimensional memory device |
| CN111146203A (en) * | 2019-12-27 | 2020-05-12 | 上海华力微电子有限公司 | Manufacturing method of 3D NOR flash memory and memory cell structure thereof |
| CN111162077A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN111180456A (en) * | 2020-01-03 | 2020-05-19 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111223872A (en) * | 2020-01-17 | 2020-06-02 | 长江存储科技有限责任公司 | 3D NAND memory and manufacturing method thereof |
| CN111370424A (en) * | 2020-04-16 | 2020-07-03 | 中国科学院微电子研究所 | Three-dimensional flash memory and manufacturing method thereof |
| CN111739891A (en) * | 2020-06-30 | 2020-10-02 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111771281A (en) * | 2020-01-17 | 2020-10-13 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN112331670A (en) * | 2020-07-24 | 2021-02-05 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device and 3D memory device thereof |
| CN112435936A (en) * | 2020-11-23 | 2021-03-02 | 长江存储科技有限责任公司 | Overlay precision detection method and semiconductor structure |
| TWI725633B (en) * | 2019-06-17 | 2021-04-21 | 大陸商長江存儲科技有限責任公司 | 3d memory device and method of forming the same |
| CN111341780B (en) * | 2020-03-03 | 2021-06-15 | 长江存储科技有限责任公司 | 3D NAND memory and manufacturing method thereof |
| US11094712B2 (en) | 2019-06-17 | 2021-08-17 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with support structures in slit structures and method for forming the same |
| CN113284842A (en) * | 2020-02-19 | 2021-08-20 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| US11114458B2 (en) | 2019-06-17 | 2021-09-07 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with support structures in gate line slits and methods for forming the same |
| TWI743836B (en) * | 2020-04-30 | 2021-10-21 | 大陸商長江存儲科技有限責任公司 | 3d memory device and manufacturing method thereof |
| CN113571522A (en) * | 2021-07-21 | 2021-10-29 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory and three-dimensional memory |
| US11251195B2 (en) | 2019-06-17 | 2022-02-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device without gate line slits and method for forming the same |
-
2019
- 2019-02-28 CN CN201910151716.4A patent/CN109727995A/en active Pending
Cited By (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11765897B2 (en) | 2019-06-17 | 2023-09-19 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device without gate line slits and method for forming the same |
| US11251195B2 (en) | 2019-06-17 | 2022-02-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device without gate line slits and method for forming the same |
| CN110896673A (en) * | 2019-06-17 | 2020-03-20 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device using support structure and resulting three-dimensional memory device |
| US11114458B2 (en) | 2019-06-17 | 2021-09-07 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with support structures in gate line slits and methods for forming the same |
| US11183512B2 (en) | 2019-06-17 | 2021-11-23 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory device with support structure and resulting three-dimensional memory device |
| US11094712B2 (en) | 2019-06-17 | 2021-08-17 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with support structures in slit structures and method for forming the same |
| US11716850B2 (en) | 2019-06-17 | 2023-08-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with support structures in gate line slits and methods for forming the same |
| US11963356B2 (en) | 2019-06-17 | 2024-04-16 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device without gate line slits and method for forming the same |
| TWI725633B (en) * | 2019-06-17 | 2021-04-21 | 大陸商長江存儲科技有限責任公司 | 3d memory device and method of forming the same |
| CN110364536A (en) * | 2019-07-23 | 2019-10-22 | 长江存储科技有限责任公司 | The manufacturing method and three-dimensional storage of three-dimensional storage |
| CN110600475A (en) * | 2019-08-26 | 2019-12-20 | 长江存储科技有限责任公司 | Through hole filling method and preparation method of three-dimensional memory |
| CN110600475B (en) * | 2019-08-26 | 2022-11-04 | 长江存储科技有限责任公司 | Through hole filling method and preparation method of three-dimensional memory |
| CN111146203A (en) * | 2019-12-27 | 2020-05-12 | 上海华力微电子有限公司 | Manufacturing method of 3D NOR flash memory and memory cell structure thereof |
| CN111162077A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN111162077B (en) * | 2020-01-02 | 2022-07-22 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN111180456B (en) * | 2020-01-03 | 2021-05-28 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN113314540A (en) * | 2020-01-03 | 2021-08-27 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111180456A (en) * | 2020-01-03 | 2020-05-19 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111223872A (en) * | 2020-01-17 | 2020-06-02 | 长江存储科技有限责任公司 | 3D NAND memory and manufacturing method thereof |
| CN111771281B (en) * | 2020-01-17 | 2021-07-20 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN111771281A (en) * | 2020-01-17 | 2020-10-13 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN113644077B (en) * | 2020-01-17 | 2023-09-26 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| US11723201B2 (en) | 2020-01-17 | 2023-08-08 | Yangtze Memory Technologies Co., Ltd. | Method of forming three-dimensional memory device with epitaxially grown layers |
| CN113644077A (en) * | 2020-01-17 | 2021-11-12 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN113284842A (en) * | 2020-02-19 | 2021-08-20 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN113284842B (en) * | 2020-02-19 | 2024-03-01 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN111341780B (en) * | 2020-03-03 | 2021-06-15 | 长江存储科技有限责任公司 | 3D NAND memory and manufacturing method thereof |
| CN111370424B (en) * | 2020-04-16 | 2022-09-27 | 中国科学院微电子研究所 | Three-dimensional flash memory and manufacturing method thereof |
| CN111370424A (en) * | 2020-04-16 | 2020-07-03 | 中国科学院微电子研究所 | Three-dimensional flash memory and manufacturing method thereof |
| TWI743836B (en) * | 2020-04-30 | 2021-10-21 | 大陸商長江存儲科技有限責任公司 | 3d memory device and manufacturing method thereof |
| CN111739891B (en) * | 2020-06-30 | 2021-05-07 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111739891A (en) * | 2020-06-30 | 2020-10-02 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112331670B (en) * | 2020-07-24 | 2022-01-04 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device and 3D memory device thereof |
| CN112331670A (en) * | 2020-07-24 | 2021-02-05 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device and 3D memory device thereof |
| CN112435936B (en) * | 2020-11-23 | 2022-03-15 | 长江存储科技有限责任公司 | Overlay precision detection method and semiconductor structure |
| CN112435936A (en) * | 2020-11-23 | 2021-03-02 | 长江存储科技有限责任公司 | Overlay precision detection method and semiconductor structure |
| CN113571522A (en) * | 2021-07-21 | 2021-10-29 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory and three-dimensional memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109727995A (en) | Form the method and three-dimensional storage of three-dimensional storage | |
| KR102585801B1 (en) | Multi-stack three-dimensional memory device and method of manufacturing same | |
| EP3420595B1 (en) | Within-array through-memory-level via structures | |
| KR101968856B1 (en) | A three-dimensional memory device having an epitaxial semiconductor pedestal for peripheral transistors | |
| CN110364536B (en) | Method for manufacturing three-dimensional memory and three-dimensional memory | |
| US11631691B2 (en) | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | |
| US8822322B2 (en) | Semiconductor devices and methods of fabricating the same | |
| JP7427685B2 (en) | Three-dimensional memory device with support structure in slit structure and method for forming the three-dimensional memory device | |
| US20170352678A1 (en) | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | |
| CN108565266A (en) | Form the method and three-dimensional storage of three-dimensional storage | |
| CN110176461A (en) | 3D nand memory and forming method thereof | |
| US20170154895A1 (en) | Three-Dimensional Semiconductor Device and Manufacturing Method Therefor | |
| CN110246846A (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN108140644A (en) | For replacing opening in the array of three dimensional memory device | |
| WO2016032838A2 (en) | Monolithic three dimensional nand strings and methods of fabrication thereof | |
| CN109786382A (en) | Three-dimensional storage and its manufacturing method | |
| CN108364954B (en) | Three-dimensional memory device and method of forming epitaxial structure in channel hole thereof | |
| CN110211966A (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN107958909A (en) | Flush memory device and its manufacture method | |
| CN108598085A (en) | Three-dimensional storage and preparation method thereof, the method that drain electrode is made on sunk structure | |
| CN109390344A (en) | Three-dimensional semiconductor device including vertical structure and the method for forming it | |
| CN109887920A (en) | Three-dimensional storage | |
| CN109887918A (en) | Form the method and three-dimensional storage of three-dimensional storage | |
| CN108878437B (en) | Method for forming three-dimensional memory and three-dimensional memory | |
| CN109686738A (en) | Form the method and three-dimensional storage of three-dimensional storage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190507 |