CN111739891B

CN111739891B - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN111739891B
Application number: CN202010619561.5A
Authority: CN
Inventors: 张坤
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-05-07
Anticipated expiration: 2040-06-30
Also published as: CN111739891A

Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof. The method comprises the following steps: providing a substrate, and forming a sacrificial layer on the substrate; locally doping the sacrificial layer to form doped regions and undoped regions alternating in a first direction, the doped regions and the undoped regions extending along a second direction perpendicular to the first direction; forming a stacked layer and a channel structure vertically penetrating the stacked layer and the sacrificial layer on the sacrificial layer, wherein the channel structure has a memory layer and a conductive portion surrounded by the memory layer, the conductive portion reaching the sacrificial layer; forming a gate line gap vertically through the stacked layers to the sacrificial layer; selectively removing the doped region or the undoped region, forming a gap between the stacked layer and the sacrificial layer, removing at least a part of the sidewall of the memory layer in the gap, and exposing at least a part of the sidewall of the conductive part; and filling a conductive layer in the gap, wherein the conductive layer is in contact with the conductive part.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention mainly relates to the field of semiconductor design and manufacture, in particular to a three-dimensional memory and a manufacturing method thereof.

Background

With the continuous development of 3D NAND technology, the three-dimensional memory can be stacked vertically with more and more layers, from 24 layers, 32 layers and 64 layers to a high-level stack structure with more than 100 layers, which can greatly increase the storage density and reduce the price of a unit memory cell.

In the three-dimensional memory manufacturing process, the silicon substrate serves as a carrier of the three-dimensional memory. As the number of memory layers increases, more dielectric films (e.g., silicon oxide, silicon nitride, or polysilicon) are required, and more dielectric needs to be filled in the step regions, channel holes, and gate regions in the memory. The thin film structure becomes taller and more complex. After the thermal process in the manufacturing process, the film is deformed, and the silicon substrate is difficult to support the wafer deformation caused by the film pressure. Eventually, the wafer is warped and cannot be processed in the machine.

Disclosure of Invention

The invention aims to provide a three-dimensional memory and a manufacturing method thereof, which can reduce the deformation of devices.

In order to solve the above technical problem, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps: providing a substrate, and forming a sacrificial layer on the substrate; locally doping the sacrificial layer to form doped regions and undoped regions alternating in a first direction, the doped regions and the undoped regions extending along a second direction perpendicular to the first direction; forming a stack layer and a channel structure vertically penetrating the stack layer and a sacrificial layer on the sacrificial layer, wherein the channel structure has a memory layer and a conductive portion surrounded by the memory layer, the conductive portion reaching the sacrificial layer; forming a gate line gap vertically through the stacked layers to the sacrificial layer; selectively removing the doped region or the non-doped region, forming a gap between the stacked layer and the sacrificial layer, removing at least a part of the sidewall of the memory layer in the gap, and exposing at least a part of the sidewall of the conductive part; and filling a conductive layer in the gap, wherein the conductive layer is contacted with the conductive part.

In an embodiment of the invention, the method further includes: and filling an insulating layer in the grid line gap.

In an embodiment of the invention, the method further includes: and filling an array common source in the grid line gap.

In an embodiment of the invention, the method further includes: forming a conductive contact in a stepped region of the substrate not covering the stack of layers; and forming a connection layer on the back of the substrate to electrically connect the substrate and the conductive contact.

In an embodiment of the invention, before removing the sacrificial layer, a spacer layer is formed on a sidewall of the gate line gap.

In an embodiment of the invention, the method further includes doping the substrate and the conductive layer with opposite types.

In an embodiment of the present invention, before forming a connection layer electrically connecting the substrate and the conductive contact on the back surface of the substrate, the method further includes: bonding the stacked layers to another device.

In an embodiment of the present invention, the step of forming a connection layer electrically connecting the substrate and the conductive contact on the back surface of the substrate includes: forming a protective layer on the back side of the substrate, and forming a first through hole exposing the conductive contact and a second through hole exposing the substrate from the back side of the protective layer; and forming a connection layer extending to the first via hole and the second via hole on the back surface of the protection layer.

The present invention further provides a three-dimensional memory, comprising: a substrate defining a core region and a word line connection region; a conductive layer on the substrate, the conductive layer including first and second regions alternating in a first direction, the first and second regions extending along a second direction perpendicular to the first direction; a stack layer on the conductive layer, the stack layer comprising spaced gate layers; and a channel structure vertically penetrating the stacked layers and reaching the substrate, the channel structure including a conductive portion, wherein a portion of the conductive portion located on the conductive layer is exposed from a side surface of the channel structure so as to be in contact with the conductive layer.

In an embodiment of the invention, the three-dimensional memory further includes a gate line gap vertically penetrating through the stacked layers to reach the conductive layer, and the gate line gap is filled with an insulating layer.

In an embodiment of the invention, the three-dimensional memory further includes a gate line gap vertically penetrating through the stacked layers to reach the conductive layer, and the gate line gap is filled with an array common source.

In an embodiment of the present invention, the substrate and the conductive layer are doped and the doping types are opposite.

In an embodiment of the invention, the three-dimensional memory further includes another device bonded to the front surface of the stack.

In an embodiment of the invention, the three-dimensional memory further includes: a conductive contact located on the substrate not overlying the word line connection region of the stack of layers; and a connection layer located on the back side of the substrate and electrically connecting the substrate and the conductive contact.

In an embodiment of the invention, the three-dimensional memory further includes a conductive contact located on the conductive layer, and the conductive contact contacts the array common source.

Compared with the prior art, when the sacrificial layer below the stacked layer is removed, a part of the structure of the sacrificial layer still remains, so that the structure can play a supporting role and still has excellent conductive characteristics.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the principle of the invention. In the drawings:

fig. 1 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.

Fig. 2A-2L are schematic cross-sectional views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application.

Fig. 3A-3G are top views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application.

Fig. 4A-4B are schematic cross-sectional views of an exemplary fabrication process for forming a gate layer in an embodiment of the present application.

Fig. 5 is a flowchart illustrating a method of forming a backside source connection layer according to an embodiment of the present disclosure.

Fig. 6A-6E are schematic cross-sectional views of an exemplary fabrication process for forming a backside source connection layer in an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of a three-dimensional memory in another embodiment of the present application.

Fig. 8 is a schematic cross-sectional view of a three-dimensional memory in yet another embodiment of the present application.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

Embodiments of the present disclosure describe a three-dimensional memory and a method of manufacturing the same, which may overcome problems in the existing three-dimensional memory. Fig. 1 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Fig. 2A-2L are schematic cross-sectional views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application. Fig. 3A-3G are top views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application. The method of forming the three-dimensional memory of the present embodiment is described below with reference to fig. 1 to 3G.

In step 102, a substrate is provided and a sacrificial layer is formed on the substrate.

Referring to fig. 2A and 3A, a substrate 201 is provided. In an embodiment of the present disclosure, the material of the substrate 201 is, for example, silicon. A portion of the substrate 201 may be doped with a first dopant, such as a P-type dopant or an N-type dopant, to become a well 201 a.

Referring to fig. 3B, a sacrificial layer 203 is formed on a substrate 201. Sacrificial layer 203 may be selected to be etch selective to material layers in a stack of layers to be subsequently formed. For example, the sacrificial layer 203 may be a silicon-containing material layer, such as polysilicon or amorphous silicon.

In one embodiment, an etch stop layer 202 may be formed over the well region 201a of the substrate 201 for stopping etching of the substrate 201 when the sacrificial layer 203 is subsequently removed. The material of the barrier layer 203 is, for example, silicon oxide.

In the embodiments of the present application, the materials of the illustrated layers are merely exemplary, and for example, the substrate 201 may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, and the like.

In step 104, the sacrificial layer is locally doped to form doped and undoped regions alternating in a first direction, the doped and undoped regions extending along a second direction perpendicular to the first direction.

Referring to fig. 2B and 3B, the sacrificial layer 203 is partially doped to form doped regions 203a and undoped regions 203B alternately arranged in the X direction. Here, the doping may be P-type doping or N-type doping. The doped region 203a and the undoped region 203b extend along the Y direction. The widths of the doped region 203a and the undoped region 203b may be the same or different.

At step 106, a stack layer and a channel structure vertically penetrating the stack layer and the sacrificial layer are formed on the sacrificial layer, wherein the channel structure has a memory layer and a conductive portion surrounded by the memory layer, the conductive portion reaching the sacrificial layer.

In this step, as shown with reference to fig. 2C and 3C, a core region 205 and a word line connection region 206 are defined on the substrate 201. A stack layer 210 and a plurality of channel structures vertically crossing the stack layer 210 are formed on the sacrificial layer 203 of the core region 205.

The stack layer 210 may be a stack in which first material layers 211 and second material layers 212 are alternately stacked. The first material layer 211 may be a gate layer or a dummy gate layer. The second material layer 212 is a dielectric layer. The first material layer 211 and the second material layer 212 are, for example, a combination of silicon nitride and silicon oxide. Taking a combination of silicon nitride and silicon oxide as an example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods may be used to alternately deposit silicon nitride and silicon oxide on the substrate 201 in sequence to form the stack layer 210. It is understood that the stacked layers herein may comprise a single or multiple stacks (deck).

A plurality of channel structures, including a memory layer 214, a channel layer 215, and a conductive portion 217, which are electrically connected to each other, are disposed in a channel hole 213 of the stacked layer stack 210, perpendicular to the surface of the substrate 201. Here, the conductive portion 217 may be silicon, such as polysilicon, located at the bottom of the channel hole 213. Here, the conductive portion 217 is surrounded by the memory layer 214, and reaches the sacrifice layer 203. In the example of fig. 2B, the conductive portion 217 penetrates the sacrificial layer 203 to reach the well region 201a of the substrate 201.

The memory layer 214 may include a blocking layer 214a, a charge trapping layer 214b, and a tunneling layer 214c disposed from the outside to the inside between the channel layer 215 and the channel hole 213 where the channel structure is located. These layers constitute a memory layer 214. The memory layer 214 may not be a dielectric layer disposed within the channel hole, but a floating gate structure disposed within a lateral trench in the first material layer 211 adjacent to the first channel hole 213. Some example details of the memory layer 214 will be described later.

It will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure shown in fig. 2C. For example, a fill structure 216 may also be disposed within channel layer 215. The filling structure 216 may function as a support. The material of the fill structure 216 may be silicon oxide. The fill structure 216 may be solid or hollow without affecting device reliability.

At step 108, a gate line gap is formed vertically through the stack of layers to the sacrificial layer.

In this step, various Gate Line Slits (GLS) may be formed through the stacked layers in a direction perpendicular to the substrate in the semiconductor structure, thereby dividing the core region into a plurality of block and/or finger memory regions.

A gate gap 218 is formed through the stacked layers 210 perpendicular to the substrate 201 on the semiconductor structure in fig. 2D and 3D. The gate line gap 218 reaches the sacrificial layer 203, removes a portion of the thickness of the sacrificial layer 203, or rests on the upper surface of the sacrificial layer 203. The method of forming gate line gap 218 includes etching stack 210.

As shown in fig. 2E, after the gate line gap 218 is formed, a spacer layer 219 may be further formed in the gate line gap 218. The spacer 219 may protect the sidewalls of the gate line gap 218 during subsequent removal of the sacrificial layer 203 and the memory layer 214 therein. The spacer layer 219 may be a multilayer material, such as shown in fig. 2E, including a first layer 219a on the inside (near the sidewalls of the gate line gap 218), a second layer 219b in the middle, and a third layer 219c on the outside. The sacrificial layer 203 has a high etch selectivity with respect to the third layer 219 c. In this way, the spacer 219 is not substantially damaged when the sacrificial layer 203 is etched. The material of the third layer 219c and the first layer 219a may be the same as the material of the charge trapping layer 214b in the memory layer 214, and the material of the second layer 219b may be the same as the material of the tunneling layer 214c in the memory layer 214. The barrier layer 214a in the memory layer 214 has a high etch selectivity relative to the third layer 219 c. The third layer 219c is not substantially damaged when the barrier layer 214a in the memory layer 214 is etched. The third layer 219c is etched away together when the charge trap layer 214b in the memory layer 214 is etched, thereby exposing the second layer 219 b. The second layer 219b is etched away together when the tunneling layer 214c in the memory layer 214 is etched, exposing the first layer 219 a.

The material of the first layer 219a and the third layer 219c may be silicon nitride, as opposed to the sacrificial layer 203, which is typically polysilicon or amorphous silicon. With respect to the memory layer 214, which is typically a silicon oxide-silicon nitride-silicon oxide, the material of the first layer 219a and the third layer 219c may be silicon nitride, and the material of the second layer 219b may be silicon oxide or silicon oxynitride.

In some embodiments, the spacer layer 219 may be a 2-layer material, e.g., the second layer may be the same material as the charge trapping layer 214b in the memory layer 214, and the first layer may be the same material as the tunneling layer 214c in the memory layer 214.

In some embodiments, the spacer 219 may be a single material, such as aluminum oxide or titanium nitride, which allows for a high etch selectivity ratio for both the sacrificial layer 203 and the memory layer 214 relative to the spacer 219. In this way, spacer 219 is not substantially damaged during etching of sacrificial layer 203 and memory layer 214.

In step 110, the doped region or the undoped region is selectively removed, a gap is formed between the stacked layer and the sacrificial layer, and at least a portion of the sidewall of the portion of the memory layer in the gap is removed to expose at least a portion of the sidewall of the conductive portion.

As shown in fig. 2F and 3E, taking the removal of the non-doped region 203b as an example, a gap 207 is formed between the stacked layer 210 and the substrate 201. Gap 207 exposes a portion of sidewall 214s of the portion of the memory layer in the sacrificial layer and exposes barrier layer 202. The memory layer is surrounded by the remaining doped region 203a at the other part of the sidewall of the portion of the sacrificial layer without being exposed. The method for removing the undoped region 203b is, for example, wet etching. Here, the barrier layer 203 may serve as a stop layer for wet etching. Since the doped region 203a remains, this structure can serve as a support while still having good conductive properties.

At step 112, the portion of the memory layer in the gap is removed, exposing at least a portion of the sidewalls of the conductive portion.

In this step, as shown in fig. 2G and 3F, a portion of the sidewall thickness of the channel structure, including the blocking layer 214a, the charge trapping layer 214b, and the tunneling layer 214c of the memory layer 214, is removed through the gap, thereby exposing a portion of the sidewall 217s of the conductive portion 217. In this step, the blocking layer 214a, the charge trapping layer 214b, and the tunneling layer 214c may be sequentially removed by a plurality of wet etches, a plurality of dry etches (e.g., gas etches), or a wet plus dry etch (e.g., gas etch).

In step 114, the gap is filled with a conductive layer, and the conductive layer contacts the conductive portion.

In this step, as shown in fig. 2H and 3G, the second conductive region 208a is formed by removing the gap formed by the sacrificial layer so as to fill the gap, thereby making it possible to contact the conductive portion 217. The doped region 203a previously remained as the first conductive region is merged with the second conductive region 208a to form the conductive layer 208. In one embodiment, the second conductive region 208a may be formed using deposition. The second conductive region 208a may be doped, for example, oppositely doped from the substrate 201. When the substrate 201 is P-doped, the second conductive region 208a is N-doped.

By contacting the conductive layer 208 through the side surface of the conductive portion 217, the difficulty in manufacturing the conductive portion 217, particularly, the difficulty in forming the conductive portion 217 in a channel hole with a high aspect ratio can be reduced.

After filling the second conductive region 208a, the dummy gate layer in the stack layer 210 may be replaced with a gate layer 211'. The material of the gate layer 211' is, for example, titanium nitride (TiN) or tungsten (W). An adhesive layer 211a and a high-K (dielectric constant) oxide layer 211b may be formed between the gate layer 211' and the channel structure.

In step 116, an insulating layer is filled in the gate line gap.

Referring to fig. 2I, an insulating layer 219 is filled in the gate line gap. The insulating layer 219 may fill the entire gate line gap so that the gate line gap is no longer filled with conductive contacts. The material of the insulating layer 219 may be silicon oxide. Because no conductive contact exists in the grid line gap, no capacitance exists between the grid line gap and the channel hole, and the potential leakage hazard between the grid line gap and the channel hole can be remarkably relieved. And the insulating layer is filled in the grid line gap, so that the supporting effect can be achieved, and the stress of the device can be relieved.

In another embodiment not shown, the gate line gap is filled with an array common source contact.

At step 118, conductive contacts are formed at the word line connection regions of the semiconductor structure not overlying the stack of layers.

Referring to fig. 2J, conductive contacts are formed in respective regions of the semiconductor structure, such as conductive contact 221 connecting respective channel structures, conductive contact 222 connecting respective gates in the word line connection regions covering the stacked layers, and

conductive contacts

223 and 224 in the word line connection regions not covering the stacked layers. The

conductive contacts

223 and 224 reach the substrate 201. And, a metal interconnect structure 228 is formed electrically connecting the conductive contacts 221-224.

At step 120, a connection layer is formed on the back side of the substrate, the connection layer connects to the substrate or the conductive layer, and connects to the conductive contact.

Referring to fig. 2K, conductive contacts 209 are first formed on the back side of the substrate. The conductive contacts 209 correspond to the locations of the insulating layer 219.

As shown with continued reference to fig. 2K, before forming the conductive contact 209 on the backside of the substrate 201, the method further includes: the semiconductor structure is bonded to another device 230. The other device 230 may be a CMOS device.

Referring to fig. 2L, a connection layer 225 is formed on the back surface of the substrate 201. The connection layer 225 connects the conductive contact 209 and the conductive contact 223. The connection layer 225 also pulls the conductive contact 224 from the back of the substrate 201. A protective layer 226 may be formed between the substrate 201 and the connection layer 225. The material of the protection layer 226 may be silicon oxide.

In other embodiments, the connecting layer 225 may instead contact the substrate 201 or the conductive layer 208 when the conductive contact 209 is not present.

In other embodiments, the source may not be led out from the back, but is led out to the front through the array common source of the gate line gap.

Referring to fig. 2L, a passivation layer 227 is covered over the protective layer 226, and then a conductive contact 226 connected to the conductive contact 224 is formed. The material of the passivation layer 227 may be silicon nitride.

So far, the process of the three-dimensional memory is basically finished. After these processes are completed, conventional processes are added to obtain the three-dimensional memory according to the embodiments of the present disclosure. Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 4A-4B are schematic cross-sectional views of an exemplary fabrication process for forming a gate layer in an embodiment of the present application. Referring to fig. 4A, the second conductive region 208a is first formed by removing the sacrificial layer to form a gap, so as to fill the gap, thereby making it possible to contact the conductive portion 217. Next, as shown in fig. 4B, the first layer 219a of the spacer layer and the dummy gate layer 211 are removed through the gate line gap 218, forming a recess 211 r. A high-K oxide layer 211b is then deposited on the surface of the stack 210, in the gate line gap and in the recess, and the bonding layer 211a and the gate layer 211' are sequentially filled in the recess 211 r. And then, removing the high-K oxide layer on the surface of the stack layer 210 and at the bottom of the gate line gap by dry etching, so as to obtain the semiconductor structure shown in fig. 2H.

Fig. 5 is a flowchart illustrating a method of forming a backside source connection layer according to an embodiment of the present disclosure. Fig. 6A and 6E are schematic cross-sectional views of an exemplary fabrication process for forming a backside source connection layer in an embodiment of the present application. The method of forming the back side source connection layer of the present embodiment is described below with reference to fig. 5 to 6E.

At step 502, the semiconductor structure formed in FIG. 2J is bonded to another device 230, as shown in FIG. 6A. The other device 230 is, for example, a CMOS device.

In step 504, the substrate 201 is thinned to become the well region 201a, as shown in fig. 6B.

At step 506, as shown in fig. 6C, a protective layer 226 is formed on the back side of the substrate 201, and a first via 226a exposing the conductive contact 223 is formed from the back side of the protective layer 226.

In step 508, as shown in fig. 6D, the spacer layer 229 is covered on the protective layer 226, and a second via hole 226b exposing the substrate 201 is formed from the backside of the spacer layer 220. At this time, the spacer layer 229 still covers the first through hole 226 a. The material of the spacer layer 229 is, for example, silicon oxide.

At step 510, as shown in fig. 6E, a connection layer 225 electrically connecting the conductive contact 223 and the well region 201a of the substrate 201 is deposited. The material of the connection layer 225 is a metal, such as tungsten (W). A bonding layer, such as titanium nitride (TiN), may be disposed between the tie layer 225 and other materials, such as the spacer layer 229.

The structure of a three-dimensional memory according to an embodiment of the present application is described below with reference to fig. 2L.

The three-dimensional memory 200 may include a substrate 201, a conductive layer 208, and a stack layer 210. A conductive layer 208 is located in the substrate 201 and is in contact with the substrate 201. The conductive layer 208 includes first and second

conductive regions

203a and 208a alternating in a first direction, the first and second

conductive regions

203a and 208a extending along a second direction perpendicular to the first direction. The substrate 201 is subjected to a first doping, for example a P-type doping. The conductive layer 208 is doped a second amount, such as N-type doping. The substrate 201 defines a core region and wordline connection regions. Stack layer 210 is situated over conductive layer 208 and forms a staircase structure at the word line connection regions. Stacked layer 210 includes a plurality of gate layers 211' that are spaced apart. Adjacent ones of the plurality of gate layers 211' may be separated therefrom by, for example, a dielectric layer (or insulating layer) 212. The number of layers of the gate layer 211 is related to the number of layers of the three-dimensional memory 200.

The stacked layers 210 of the core region have a plurality of channel holes therein. Each channel hole has a memory layer 214 and a channel layer 215 therein. For charge-trapping flash (CTF), there is also a memory layer 214 within each channel hole 213. The memory layer 214 may include a blocking layer, a charge trapping layer, and a tunneling layer disposed radially outward and inward of the channel hole. There may also be a fill structure 216 within each channel hole, located within channel layer 215. However, it is understood that the filling structure 216 may be omitted. For example, the channel layer 215 may expand in the radial direction of the channel hole to fill the space currently occupied by the fill structure 216. There is also a conductive portion 217 at the root of each channel hole 213. This conductive portion 217 is in contact with the channel layer 215 and reaches the substrate 201. In embodiments of the present disclosure, the channel hole may be a cylindrical hole, although not by way of limitation.

The structure formed in the channel hole is referred to herein as a channel structure. The entire channel structure passes vertically through stack layer 210 and to conductive layer 208. A part of a sidewall 217s of the portion of the conductive layer 217 located on the conductive layer 208 is exposed from the side surface of the channel structure, and is in contact with the conductive layer 208. The other part of the sidewall of the conductive portion 217 at the portion of the conductive layer 208 is still covered by the memory layer and is not exposed.

The stack 210 has a gate gap therein that extends vertically through the stack to the conductive layer 208, and the gate gap is filled with an insulating layer 219. From the top view of the three-dimensional memory, the insulating layers 219 are in the shape of lines, and divide the memory array of the three-dimensional memory into a plurality of memory areas.

Conductive contacts are formed in respective regions of the semiconductor structure, such as conductive contact 221 connecting respective channel structures, conductive contact 222 connecting respective gates in the word line connection region covering the stacked layers, and

conductive contacts

223 and 224 in the word line connection region not covering the stacked layers. The

conductive contacts

The core region of the three-dimensional memory 200 has conductive contacts 221 connecting the respective channel structures. The portion of the word line connection region overlying stack layer 210 of three-dimensional memory 200 has conductive contacts 222 connecting the various gate layers. The portion of the word line connection region of the three-dimensional memory 200 not covering the stack layer 210 has

conductive contacts

223 and 224 connecting the substrate 201. The stack layer 210 also has a metal interconnect structure 228 on the front surface for the conductive contact 221-224. These metal interconnect structures 228 may include source lines, drain lines, and gate lines.

The three-dimensional memory 200 has a connection layer 225 on the back side of the substrate 201. The connection layer 225 connects the conductive contact 223 and the conductive contact 209. The connection layer 225 is located on the back of the protection layer 226. This back-out source approach allows the gate line gap to be no longer filled with conductive contacts. Because no conductive contact exists in the grid line gap, no capacitance exists between the grid line gap and the channel hole, and the potential leakage hazard between the grid line gap and the channel hole can be remarkably relieved. And the insulating layer is filled in the grid line gap, so that the supporting effect can be achieved, and the stress of the device can be relieved.

As shown in fig. 2L, the three-dimensional memory 200 may include another device, such as a CMOS device. The semiconductor structure in which the stack layer 210 is located is bonded to another device 230 to form a three-dimensional memory.

Referring to fig. 2L, there is a passivation layer 227 over the protective layer 226, and a portion of the connection layer 225 is connected to the conductive contact 224 through the passivation layer 227. The material of the passivation layer 227 may be silicon nitride.

Fig. 7 is a schematic cross-sectional view of a three-dimensional memory in another embodiment of the present application. Referring to fig. 7, the present embodiment is different from the previous embodiment in that an array common source 218a is formed in the gate line gap. The source of the memory device may not be routed from the back side of the device, but instead may be routed through the array common source 218a of the gate line gap to the front side of the CMOS device, but ultimately out through the contacts of the memory array device. The conductive contact 218b is used to make the conductive layer 208 in good electrical contact with the array common source 218 a.

Fig. 8 is a schematic cross-sectional view of a three-dimensional memory in yet another embodiment of the present application. Referring to fig. 8, this embodiment has a similar array common source 218a and conductive contact 218b as the embodiment shown in fig. 7. The difference is that the source is led out to the front side through the array common source 218a of the gate line gap to the CMOS device and then to the outside through the contact of the CMOS device.

In embodiments of the present disclosure, an exemplary material of the blocking layer and the tunneling layer is silicon oxide, silicon oxynitride, or a mixture thereof, and an exemplary material of the charge trapping layer is silicon nitride or a multilayer structure of silicon nitride and silicon oxynitride. The blocking layer, the charge trapping layer, and the tunneling layer may be formed, for example, in a multilayer structure having silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO); an exemplary material for channel layer 215 is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K (dielectric constant) oxide layer; the material of the channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si: C, SiGe: C, SiGe: H, and other semiconductor materials.

Fig. 2L, 7 and 8 illustrate a three-dimensional memory having a single stack. In another embodiment, the present disclosure may also be used with three-dimensional memory that is multiple stacks.

The three-dimensional memory shown in fig. 2L, 7 and 8 is a charge trapping memory (CTF) in which charge storage is achieved by a dielectric layer. It is understood, however, that embodiments of the present disclosure may also be implemented in floating gate type memories, where the charge trapping layer is implemented by a floating gate. The charge trapping layer includes, for example, a polysilicon material.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.

Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.

Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.

Claims

1. A method of fabricating a three-dimensional memory, comprising the steps of:

providing a substrate, and forming a sacrificial layer on the substrate;

locally doping the sacrificial layer to form doped regions and undoped regions alternating in a first direction, the doped regions and the undoped regions extending along a second direction perpendicular to the first direction;

forming a stack layer and a channel structure vertically penetrating the stack layer and a sacrificial layer on the sacrificial layer, wherein the channel structure has a memory layer and a conductive portion surrounded by the memory layer, the conductive portion reaching the sacrificial layer;

forming a gate line gap vertically through the stacked layers to the sacrificial layer;

selectively removing the doped region or the non-doped region, forming a gap between the stacked layer and the sacrificial layer, removing at least a part of the sidewall of the memory layer in the gap, and exposing at least a part of the sidewall of the conductive part; and

and filling a conducting layer in the gap, wherein the conducting layer is contacted with the conducting part.

2. The method of claim 1, further comprising: and filling an insulating layer in the grid line gap.

3. The method of claim 1, further comprising: and filling an array common source in the grid line gap.

4. The method of claim 1, further comprising:

forming a conductive contact in a stepped region of the substrate not covering the stack of layers; and

and forming a connecting layer for electrically connecting the substrate and the conductive contact on the back surface of the substrate.

5. The method of claim 1, further comprising forming a spacer layer on a sidewall of the gate line gap before removing the sacrificial layer.

6. The method of claim 1, further comprising doping the substrate and the conductive layer of opposite types.

7. The method of claim 4, further comprising, prior to forming a connection layer on the back side of the substrate that electrically connects the substrate and the conductive contact: bonding the stacked layers to another device.

8. The method of claim 4, wherein forming a connection layer on the back side of the substrate to electrically connect the substrate and the conductive contact comprises:

forming a protective layer on the back side of the substrate, and forming a first through hole exposing the conductive contact and a second through hole exposing the substrate from the back side of the protective layer; and

and forming a connecting layer extending to the first through hole and the second through hole on the back of the protective layer.

9. A three-dimensional memory, comprising:

a substrate defining a core region and a word line connection region;

a conductive layer on the substrate, the conductive layer including first and second regions alternating in a first direction, the first and second regions extending along a second direction perpendicular to the first direction;

a stack layer on the conductive layer, the stack layer comprising spaced gate layers; and

a channel structure vertically penetrating the stacked layers and reaching the substrate, the channel structure including a conductive portion, wherein a portion of the conductive layer located on the conductive layer is exposed from a side surface of the channel structure so as to be in contact with the conductive layer,

wherein the first region is formed prior to the stacked layer for supporting the stacked layer, and the second region is formed subsequent to the stacked layer.

10. The three-dimensional memory of claim 9, further comprising a gate line gap vertically through the stack of layers to the conductive layer, the gate line gap filled with an insulating layer.

11. The three-dimensional memory of claim 9, further comprising a gate line gap passing vertically through the stack of layers to the conductive layer, the gate line gap being filled with an array common source.

12. The three-dimensional memory of claim 9, wherein the substrate and the conductive layer are doped and of opposite doping types.

13. The three-dimensional memory of claim 9, further comprising another device bonded to the front side of the stack.

14. The three-dimensional memory according to claim 10, further comprising:

a conductive contact located on the substrate not overlying the word line connection region of the stack of layers; and

and the connecting layer is positioned on the back surface of the substrate and electrically connects the substrate and the conductive contact.

15. The three-dimensional memory according to claim 11, further comprising:

a conductive contact at the conductive layer, the conductive contact contacting the array common source.