WO2024012085A1 - Semiconductor structure and preparation method for semiconductor structure - Google Patents
Semiconductor structure and preparation method for semiconductor structure Download PDFInfo
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- WO2024012085A1 WO2024012085A1 PCT/CN2023/097833 CN2023097833W WO2024012085A1 WO 2024012085 A1 WO2024012085 A1 WO 2024012085A1 CN 2023097833 W CN2023097833 W CN 2023097833W WO 2024012085 A1 WO2024012085 A1 WO 2024012085A1
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- semiconductor pillar
- sacrificial layer
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- 238000002360 preparation method Methods 0.000 title abstract description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
- the floating body effect In field effect transistors, the floating body effect is usually prone to occur.
- the floating body effect means that due to the accumulation of holes in the channel, a voltage is generated in the channel, thereby increasing the drain current.
- the floating body effect will cause the output characteristic curve of the device to warp, that is, the Kink effect.
- the Kink effect has many adverse effects on device and circuit performance and reliability.
- 3D DRAM dynamic random access memory
- semiconductor pillars are usually stacked horizontally, and word lines or bit lines are usually arranged in a ladder-like manner to save space and improve integration.
- Embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; a word line, the word line covers the channel region part of the side of the semiconductor pillar, and expose the remaining part of the side of the semiconductor pillar in the channel area; a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and the conductive layer is used to be electrically connected to the ground.
- the cross-sectional shape of the semiconductor pillar is a rectangle in a direction perpendicular to the doping region and toward the channel region, and the word line exposes one side of the semiconductor pillar.
- the semiconductor pillar is parallel to the substrate surface, the word line is parallel to the substrate surface, and the conductive layer is arranged opposite to the word line. It also includes: a conductive pillar, the conductive pillar is perpendicular to the substrate surface, and the conductive pillar is electrically connected to the conductive layer, And the conductive pillar is used for grounding.
- the conductive layer is made of the same material as the conductive pillar.
- the material of the conductive layer includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, At least one of titanium silicides.
- the substrate surface is provided with a plurality of semiconductor pillars stacked in a direction away from the substrate and a plurality of word lines, wherein the side surfaces of part of the semiconductor pillars covering the channel region in the semiconductor pillars are covered, and in the semiconductor pillars, At least part of the side surfaces of the exposed semiconductor pillars in the channel region are electrically connected to the conductive layer.
- the semiconductor structure further includes a conductive pillar, the conductive pillar is electrically connected to the plurality of conductive layers, and the conductive pillar is used to be electrically connected to the ground.
- a bit line is further included, and the bit line is electrically connected to an end of a semiconductor pillar in a doped region.
- embodiments of the present disclosure also provide a method for preparing a semiconductor structure, including: providing a substrate; forming a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; forming a word line, the word line covers part of the side of the semiconductor pillar in the channel area, and exposes the remaining part of the side of the semiconductor pillar in the channel area; forming a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and The conductive layer is used for electrical connection with the ground terminal.
- a method for forming a conductive layer and a word line includes: forming at least two initial semiconductor pillars stacked in a direction away from the substrate on a substrate; forming a first sacrificial layer, the first sacrificial layer being located on an adjacent initial semiconductor pillar between, and the first sacrificial layer at least covers the surface of the initial semiconductor pillar in the channel area; etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer to form a semiconductor pillar and exposing the top surface of the semiconductor pillar; in the channel A word line is formed on the top surface of the semiconductor pillar in the channel area; the first sacrificial layer is removed to expose part of the bottom surface of the semiconductor pillar; a conductive layer is formed on the bottom surface of the semiconductor pillar in the channel area, and the conductive layer located on the bottom surface of one semiconductor pillar is in contact with the adjacent semiconductor pillar.
- Word lines on the top surface are adjacent in a direction perpendicular to the first
- the substrate is a silicon substrate
- the method of forming the first sacrificial layer includes: forming an initial sacrificial layer, the initial sacrificial layer is located between adjacent initial semiconductor pillars, and the material of the initial sacrificial layer includes first silicon germanium; Part of the initial sacrificial layer is removed to form a first groove, which exposes part of the bottom surface of the initial semiconductor pillar; a first sacrificial layer is formed in the first groove, and the material of the first sacrificial layer is different from the material of the initial sacrificial layer.
- the method of etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer includes: forming a second sacrificial layer stacked with the initial sacrificial layer, and the material of the second sacrificial layer is a second silicon germanium , the germanium content in the second silicon germanium is lower than the germanium content in the first silicon germanium, and the second sacrificial layer is in contact with the top surface of the initial semiconductor pillar and part of the initial sacrificial layer is removed to form the first sacrificial layer; part of the first sacrificial layer is removed The second sacrificial layer exposes the top surface of the initial semiconductor pillar; the top surface of the initial semiconductor pillar is etched to form a semiconductor pillar.
- the method further includes: forming a first dielectric layer, the first dielectric layer being located between an adjacent word line in a direction perpendicular to the substrate and the conductive layer.
- the material of the first dielectric layer includes: a low-k dielectric material.
- a plurality of semiconductor pillars arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars are arranged on the same layer, and the word line covers part of each channel region in a row of semiconductor pillars arranged along the first direction.
- the method of forming the word line includes: forming an isolation structure between adjacent semiconductor pillars along the first direction and covering the side of the semiconductor pillar in the channel region; The top surface is etched until the isolation structure has a predetermined thickness; a word line is formed on the top surface of the semiconductor pillar and part of the side surface of the channel area.
- Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
- Figure 2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure
- Figure 3 is a schematic cross-sectional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
- 4 to 32 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
- Embodiments of the present disclosure provide a semiconductor structure by arranging word lines to cover part of the semiconductor pillar side surfaces of the channel region and exposing the remaining semiconductor pillar side surfaces of the channel area, so that the word lines located on the semiconductor pillar side surfaces of the channel area can Used to control the conduction of the channel, the side of the exposed semiconductor pillar in the channel area can be used for grounding; the conductive layer is electrically connected to the side of the semiconductor pillar in the exposed channel area, and the conductive layer is used to be electrically connected to the ground terminal, so that The charges accumulated in the channel region can be discharged to the ground through the conductive layer, thereby preventing the floating body effect.
- FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
- FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
- FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Schematic cross-section of the structure.
- the semiconductor structure includes: a substrate; a semiconductor pillar 10 located on the substrate, the semiconductor pillar 10 having a channel region 11 and doped regions 12 located on opposite sides of the channel region 11 ; a word line 101 .
- 101 covers part of the side surfaces of the semiconductor pillars 10 in the channel region 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; the conductive layer 102, the conductive layer 102 and at least part of the side surfaces of the semiconductor pillars 10 in the channel area 11 are exposed Electrically connected, and the conductive layer 102 is used to be electrically connected to the ground.
- the conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charges in the channel region 11 can be transferred to the conductive layer 102, and then discharged to the ground via the conductive layer 102, thus preventing the occurrence of The problem of floating body effect occurs due to excessive charge accumulation in the channel region 11 .
- the material of the substrate is a semiconductor material.
- the material of the substrate is silicon.
- the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon on insulator substrate.
- the material of the semiconductor pillar 10 may be the same as the material of the substrate. In some embodiments, the material of the semiconductor pillar 10 may be silicon.
- the channel region 11 and the doped regions 12 located on both sides of the channel region 11 can be used to form a transistor, wherein the doped regions 12 located on both sides of the channel region 11 can serve as one of the source or drain of the transistor.
- the word line 101 may serve as a gate of the semiconductor structure, and is used to conduct the channel region 11 based on the control signal to realize carrier transfer between the source and the drain.
- the doping ion type of the channel region 11 may be different from the doping ion type of the doping region 12 , thereby forming a junction transistor.
- the doping ion type in the channel region 11 may be P.
- the type of doping ions in the doping region 12 may be N-type, forming an NMOS transistor.
- the semiconductor structure forms an NMOS transistor, electrons move in the channel, and the electrons in the channel obtain enough energy in the high field region of the drain end to generate electron-hole pairs, causing the holes to move toward the channel region 11 with a lower potential. move. That is, holes move from the drain to the source. Since the gate-source junction has a high potential barrier, holes accumulate in the channel region 11 . Therefore, the conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11. When holes move from the drain to the source into the channel region 11, they will be discharged to the ground through the conductive layer 102, thereby Avoid floating body effect.
- the doping ion type of the channel region 11 may be the same as the doping ion type of the doping region 12 to form a junctionless transistor.
- the cross-sectional shape of the semiconductor pillar 10 is rectangular in a direction perpendicular to the doping region 12 and directed toward the channel region 11 , and the word line 101 exposes one side of the semiconductor pillar 10 . That is to say, the word line 101 is arranged around three sides of the semiconductor pillar 10, so that the contact area between the word line 101 and the semiconductor pillar 10 in the channel region 11 is larger, thereby increasing the area of the formed channel and The length enhances the ability of the word line 101 to control the channel and also helps reduce leakage current.
- the word line 101 is arranged to expose one side of the semiconductor pillar 10 for forming an electrical connection with the conductive layer 102 .
- the side surface exposed by the word line 101 is arranged opposite to the word line 101, and the conductive layer 102 is electrically connected to the exposed side surface, so that the distance between the conductive layer 102 and the word line 101 is large, thereby preventing the actual preparation of the conductive layer 102. During the process, the distance between the conductive layer 102 and the word line 101 is too close, resulting in the problem of electrical connection between the formed conductive layer 102 and the word line 101 .
- the word line 101 may completely cover three sides of the semiconductor pillar 10 to increase the contact area between the word line 101 and the semiconductor pillar 10 .
- the word line 101 may also cover the side of the semiconductor pillar 10 opposite to the exposed side of the semiconductor pillar 10 , and partially cover the remaining two sides of the semiconductor pillar 10 , so that the word line 101 reaches the side of the exposed semiconductor pillar 10 The distance between them is large. Therefore, when the conductive layer 102 forms an electrical connection with the exposed side of the semiconductor pillar 10 , the distance between the conductive layer 102 and the word line 101 is larger, further preventing the problem of contact between the conductive layer 102 and the word line 101 .
- the semiconductor pillar 10 is parallel to the substrate surface, the word line 101 is parallel to the substrate surface, and the conductive layer 102 is arranged opposite to the word line 101. It also includes: a conductive pillar 103, the conductive pillar 103 is perpendicular to the substrate surface, and the conductive pillar 103 is perpendicular to the substrate surface. 103 is electrically connected to the conductive layer 102, and the conductive pillar 103 is used for grounding.
- the semiconductor pillars 10 are arranged parallel to the substrate surface, and the word lines 101 are parallel to the substrate surface, so that in the direction perpendicular to the substrate, the sizes occupied by the semiconductor pillars 10 and the word lines 101 are smaller, which is beneficial to the formation of the semiconductor pillars 10
- the stacked structure improves the integration of the formed semiconductor structure. Arranging the conductive layer 102 and the word line 101 to face each other can prevent the problem of electrical contact between the conductive layer 102 and the word line 101 due to being too close. Since the word line 101 is parallel to the substrate surface, the conductive layer 102 is also parallel to the substrate surface, and the overall size of the semiconductor structure is small.
- the conductive layer 102 When the conductive layer 102 is arranged parallel to the substrate surface, it may cause the problem that the conductive layer 102 cannot be connected to the ground. . Based on this, the conductive pillars 103 are arranged perpendicular to the surface of the substrate, that is, perpendicular to the conductive layer 102 . This not only makes it easy for the conductive pillars 103 to form an electrical connection with the ground, but also allows the charges transmitted in the conductive layer 102 to pass through the conductive pillars 103 It is discharged to the ground and is also helpful in reducing the process difficulty of preparing semiconductor structures.
- the conductive layer 102 is made of the same material as the conductive pillars 103 .
- the conductive layer 102 is made of the same material as the conductive pillar 103 , so that the charge transmission capabilities of the conductive layer 102 and the conductive pillar 103 are close to or the same, so that when the charge is transferred from the conductive layer 102 to the conductive pillar 103 , the charge can be kept relatively fast.
- the transmission rate allows the charges accumulated in the channel region 11 to be discharged to the ground more quickly, thereby avoiding the floating body effect and maintaining the normal performance of the semiconductor structure.
- the material of the conductive layer 102 includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide.
- the substrate is a silicon substrate, and the material of the semiconductor pillar 10 is the same as the substrate, that is, the material of the semiconductor pillar 10 is silicon. In this way, the conductive layer 102 has the same elements as the semiconductor pillar 10 , that is, the conductive layer 102 The material properties of are close to those of the semiconductor pillar 10 .
- the substrate surface is provided with a plurality of semiconductor pillars 10 stacked in a direction away from the substrate and a plurality of word lines 101, wherein the side surfaces of part of the semiconductor pillar 10 covering the channel region 11 in the semiconductor pillar 10,
- the semiconductor pillar 10 at least part of the side surfaces of the semiconductor pillar 10 in the exposed channel region 11 is electrically connected to the conductive layer 102 .
- Each semiconductor pillar 10 is used to form a transistor.
- Multiple semiconductor pillars 10 are stacked on the surface of the substrate, so that multiple transistors can be formed.
- the stacked semiconductor pillars 10 occupy a smaller size, which is beneficial to Improve the integration level of the formed semiconductor structure.
- each semiconductor pillar 10 When there are multiple semiconductor pillars 10 , the channel region 11 of each semiconductor pillar 10 needs to be electrically connected to the word line 101 so that the word line 101 can control the conduction of the channel region 11 .
- the word line 101 In order to reduce the area occupied by the word line 101, the word line 101 is set parallel to the substrate surface, so that the size of the word line 101 in the direction perpendicular to the substrate surface can be reduced, thereby reducing the overall size of the semiconductor structure. Based on this, among the stacked semiconductor pillars 10 , each semiconductor pillar 10 corresponds to a word line 101 , that is, each word line 101 is electrically connected to the channel region 11 in each semiconductor pillar 10 , so that the semiconductor structure can be maintained.
- each semiconductor pillar 10 can be controlled. Since the conductive layer 102 is arranged opposite to the word line 101, when the word line 101 is parallel to the substrate surface, the conductive layer 102 is parallel to the substrate, thereby preventing the conductive layer 102 from electrical contact with the word line 101. Based on this, in the stacked semiconductor pillars 10 , the side surfaces of each exposed semiconductor pillar 10 in the channel region 11 are electrically connected to a conductive layer 102 respectively, so that no electrical contact is formed between the stacked semiconductor pillars 10 . Electrical interference occurs, and the charges accumulated in each channel region 11 can be discharged to the ground through the conductive layer 102 .
- the semiconductor structure further includes conductive pillars 103, the conductive pillars 103 are electrically connected to the plurality of conductive layers 102, and the conductive pillars 103 are used to be electrically connected to the ground.
- each semiconductor pillar 10 corresponds to a conductive layer 102
- the conductive layer 102 is arranged parallel to the substrate surface, which is equivalent to a stacked arrangement of the conductive layers 102 .
- the conductive pillars 103 are arranged perpendicular to the conductive layer 102 for grounding the conductive layer 102, and the conductive pillars 103 do not form an electrical connection with the semiconductor pillars 10, that is, there is no need to consider whether electrical contact will be formed between the conductive pillars 103 and the semiconductor pillars 10.
- the size of the conductive pillar 103 is greatly reduced, thereby reducing size of small semiconductor structures. And the charges transmitted in each conductive layer 102 can be discharged to the ground through the same conductive pillar 103 .
- the side of the semiconductor pillar 10 away from the substrate is electrically connected to the word line 101
- the side of the semiconductor pillar 10 facing the substrate is electrically connected to the conductive layer 102 .
- the word line 101 corresponding to one of the semiconductor pillars 10 will be arranged adjacent to the conductive layer 102 corresponding to the adjacent semiconductor pillar 10 .
- a first dielectric layer 104 is also included. The first dielectric layer 104 is located between the adjacent word line 101 and the conductive layer 102 and is used to isolate the adjacent word line 101 and the conductive layer 102.
- the material of the first dielectric layer 104 may be a low-k dielectric material.
- the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.
- a bit line 105 is also included, and the bit line 105 is electrically connected to an end of the semiconductor pillar 10 of a doped region 12 .
- the bit line 105 can extract electrical signals from the doped region 12 located on one side of the channel region 11 .
- the process difficulty of preparing the bit line 105 at the end of the semiconductor pillar 10 can be reduced, which is beneficial to improving the quality of the semiconductor structure. Yield.
- a plurality of semiconductor pillars 10 arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars 10 are arranged on the same layer.
- the word line 101 covers each of a row of semiconductor pillars 10 arranged along the first direction X.
- a doping region 12 in two adjacent semiconductor pillars 10 is electrically connected to the same bit line 105.
- One direction X is parallel to the substrate surface, and the second direction Y is the stacking direction of the plurality of semiconductor pillars 10 .
- the first direction X is different from the second direction Y.
- Arranging a plurality of semiconductor pillars 10 arranged in an array on the surface of the substrate is beneficial to increasing the arrangement density of the semiconductor pillars 10 and thereby increasing the integration level of the semiconductor pillars 10 .
- a plurality of semiconductor pillars 10 arranged in an array are arranged on the same layer. That is to say, the semiconductor pillars 10 arranged in an array are not stacked. When there are multiple semiconductor pillars 10 stacked on the surface of the substrate, the stacked semiconductor pillars 10 are not in the same layer. In the stacked semiconductor pillars 10 , the layer where each semiconductor pillar 10 is located has multiple semiconductors arranged in an array. Column 10.
- the multiple semiconductor pillars 10 can be arranged in different layers.
- the semiconductor pillars 10 of each layer are arranged in an array, and the semiconductor pillars 10 arranged in the array can be stacked. In this way, the arrangement density of the semiconductor pillars 10 can be further increased, making the semiconductor pillars 10 more integrated.
- the arrangement direction of the semiconductor pillars 10 is parallel to the substrate surface, and the word lines 101 are also parallel to the substrate surface. Therefore, the word lines 101 can be arranged to be arranged along the first direction X.
- Part of the semiconductor pillars 10 of each channel region 11 in a row of semiconductor pillars 10 is covered on the side, that is, multiple semiconductor pillars 10 arranged along the first direction volume, thereby reducing the overall size of the semiconductor structure.
- the bit line 105 is disposed perpendicularly to the word line 101 , that is, the bit line 105 has the same stacking direction as the plurality of semiconductor pillars 10 . Therefore, the bit line 105 can be set to be electrically connected to one of the doped regions 12 in a row of semiconductor pillars 10 arranged along the second direction Y, so that the stacked semiconductor pillars 10 can share the same bit line 105, which can further enable The bit line 105 occupies a smaller volume, thereby further reducing the overall size of the semiconductor structure.
- the bit line 105 may include a barrier layer, a conductive portion, and an insulating layer sequentially stacked in a direction away from the semiconductor pillar 10 .
- the conductive part may be a metal material, such as any one of tungsten, copper, or aluminum. In other embodiments, the conductive part may also be a semiconductor material, such as polysilicon.
- the barrier layer prevents mutual diffusion between the conductive part and the doped region 12.
- the material of the barrier layer may be titanium nitride.
- the insulating layer is used to isolate the conductive part from other conductive devices in the semiconductor structure.
- the material of the insulating layer may be silicon oxide. Or any of silicon nitride.
- the material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.
- a gate dielectric layer 106 may also be included.
- the gate dielectric layer 106 is located between the word line 101 and the semiconductor pillar 10 of the channel region 11 .
- the gate dielectric layer 106 is used to isolate the word line 101 from the semiconductor pillar 10 in the channel region 11.
- the gate dielectric layer 106 is located on the surface of the semiconductor pillar 10 in the channel area 11, so that the transistor composed of the semiconductor pillar 10 becomes a low-voltage device. In other words, due to the existence of the gate dielectric layer 106, a smaller voltage is applied to the transistor to turn on the transistor and complete the writing of data, which is beneficial to improving the performance of the semiconductor structure.
- the material of the gate dielectric layer 106 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It also includes: a barrier layer 107.
- the barrier layer 107 is located between the gate dielectric layer 106 and the word line 101 to prevent mutual diffusion of ions in the gate dielectric layer 106 and the word line 101.
- the material of the barrier layer 107 may include titanium nitride.
- a capacitor structure 108 is also included, and the capacitor structure 108 is electrically connected to another doped region 12 in the semiconductor pillar 10 . That is, the bit line 105 and the capacitor structure 108 are electrically connected to the two doped regions 12 in the semiconductor pillar 10 respectively.
- the capacitive structure 108 may include a lower electrode layer (not shown), a capacitive dielectric layer (not shown), and an upper electrode layer (not shown) sequentially stacked in a direction away from the semiconductor pillar 10 , wherein the lower electrode layer The material and the material of the upper electrode layer can be the same.
- the material of the lower electrode layer and the material of the upper electrode layer can be platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium. of at least one. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different.
- the materials of the capacitor dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, and titanium oxide.
- the word line 101 is arranged to cover part of the semiconductor side surfaces of the channel region 11 and expose the remaining part of the semiconductor pillar 10 side surfaces of the channel region 11. In this way, the semiconductor pillars 10 located in the channel region 11 are exposed.
- the word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel area 11; the conductive layer 102 is electrically connected to the exposed side of the semiconductor pillar 10 of the channel area 11, and the conductive layer 102 is used to be electrically connected to the ground. This allows the charges accumulated in the channel region 11 to be discharged to the ground through the conductive layer 102, thereby preventing the floating body effect from occurring.
- embodiments of the present disclosure also provide a method for preparing a semiconductor structure.
- the method of preparing a semiconductor structure can be used to prepare the semiconductor structure provided by the above embodiments.
- the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. illustrate.
- Figure 6 corresponds to the schematic cross-sectional structural diagram in the aa' direction in Figure 5.
- a substrate 100 is provided.
- the material of the substrate 100 is silicon.
- the substrate 100 may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
- a semiconductor pillar 10 is formed on a substrate 100.
- the semiconductor pillar 10 has a channel region 11 and doping regions 12 located on opposite sides of the channel region 11; a word line 101 is formed, and the word line 101 covers the trench. part of the side surfaces of the semiconductor pillars 10 in the channel area 11, and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; a conductive layer 102 is formed, and the conductive layer 102 is electrically connected to at least part of the side surfaces of the exposed semiconductor pillars 10 in the channel area 11, And the conductive layer 102 is used for electrical connection with the ground.
- the conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charges in the channel region 11 can be transferred to the conductive layer 102, and then discharged to the ground via the conductive layer 102, thus preventing the occurrence of The problem of floating body effect occurs due to excessive charge accumulation in the channel region 11 .
- the number of semiconductor pillars 10 may be multiple, thereby increasing the integration level of the semiconductor structure.
- the material of the semiconductor pillar 10 may be the same as the material of the substrate 100 .
- the doped regions 12 on both sides of the channel region 11 can serve as the source and drain of the transistor, and the word line 101 can serve as the gate of the transistor for controlling the conduction of the source and drain.
- the doping ion type of the doping region 12 may be the same as the doping ions of the channel region 11 , so that the type of transistor formed is a junctionless transistor. In other embodiments, the doping ion type of the doping region 12 is different from the doping ion type of the channel region 11 , so that the type of the formed transistor is a junction transistor.
- a method of forming a conductive layer and a word line includes:
- At least two initial semiconductor pillars 20 stacked in a direction away from the substrate 100 are formed on the substrate 100 .
- multiple stacked semiconductor pillars can be formed, and each semiconductor pillar can be used to form a transistor, thereby improving semiconductor Structural integration.
- a plurality of semiconductor pillars 10 arranged in an array can also be formed in the substrate 100 .
- the semiconductor pillars 10 arranged in a plurality of arrays are arranged in the same layer, and the semiconductor pillars 10 arranged in a multi-layer array can be stacked.
- the substrate 100 can be divided into a first area 1 and a second area 2, and a multi-layer stack is formed in the first area 1 and the second area 2 respectively.
- the method of forming the first area 1 and the second area 2 may include: patterning the surface of the initial semiconductor pillar 20 to define the positions of the first area 1 and the second area 2.
- the method may be on the top surface of the initial semiconductor pillar 20.
- the first mask layer 21 is formed, and the first mask layer 21 exposes the location that needs to be etched.
- a capping layer 22 is formed on top of the initial semiconductor pillar 20 to protect the initial semiconductor pillar 20 .
- the capping layer Specifically, 22 may be a silicon oxide layer and a silicon nitride layer stacked in a direction away from the substrate 100. Therefore, a first mask layer 21 may be formed on the surface of the cover layer 22.
- the pillar 20 undergoes an etching process to form the first region 1 and the second region 2 . It is worth noting that the process method for forming the semiconductor pillars 10 in the first region 1 and the second region 2 may be the same. The following will take the formation of multiple semiconductor pillars 10 in the first region 1 as an example for description.
- Figure 7 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5;
- Figure 8 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5;
- Figure 9 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5;
- Figure 10 corresponds to Figure Schematic diagram of the cross-sectional structure in the bb' direction in 5.
- a first sacrificial layer 23 is formed, the first sacrificial layer 23 is located between adjacent initial semiconductor pillars 20 , and the first sacrificial layer 23 at least covers the surface of the initial semiconductor pillar 20 in the channel region 11 ;
- a sacrificial layer 23 is located on the surface of the initial semiconductor pillar 20 in the channel region 11 to reserve space for the subsequent formation of the conductive layer 102, so that during the process of forming the word line 101, the process of forming the word line 101 will not damage the first sacrificial layer 23. Damage is formed on the covered surface of the initial semiconductor pillar 20 . Therefore, good electrical contact can be formed between the subsequently formed semiconductor layer and the surface of the semiconductor pillar 10 in the channel region 11 .
- the substrate 100 is a silicon substrate
- the method of forming the first sacrificial layer 23 includes:
- an initial sacrificial layer 24 is formed.
- the initial sacrificial layer 24 is located between adjacent initial semiconductor pillars 20 .
- the material of the initial sacrificial layer 24 includes first silicon germanium. Since the substrate 100 is a silicon substrate, the initial sacrificial layer 24 is provided.
- the material of layer 24 includes first silicon germanium, so that the initial sacrificial layer 24 and the substrate 100 have the same silicon element, so that the silicon substrate matches the lattice constant of silicon germanium.
- the silicon in the silicon substrate can be used to grow silicon germanium more easily, making the preparation process simple and forming
- There is a clear boundary between the first sacrificial layer 23 and the initial semiconductor pillar 20 which facilitates subsequent complete removal of the first sacrificial layer 23 located on the surface of the initial semiconductor pillar 20 .
- part of the initial sacrificial layer 24 is removed to form a first groove 26 .
- the first groove 26 exposes part of the bottom surface of the initial semiconductor pillar 20 .
- the first sacrificial layer subsequently formed in the first groove 26 Layer 23 may cover the bottom surface of initial semiconductor pillar 20 .
- an etching process can be used to remove part of the initial sacrificial layer 24 . Since the material of the initial sacrificial layer 24 is different from the material of the initial semiconductor layer, the etching process can be used to remove parts of the initial sacrificial layer 24 and the initial semiconductor layer. Different etching selectivity ratios realize selective etching.
- the etching process may be either dry etching or wet etching. Only part of the initial sacrificial layer 24 is removed, so that the remaining part of the sacrificial layer is still located between adjacent initial semiconductor pillars 20 to play a supporting and isolating role.
- a first sacrificial layer 23 is formed in the first groove 26 , and the material of the first sacrificial layer 23 is different from the material of the initial sacrificial layer 24 .
- the first sacrificial layer 23 needs to have a greater hardness to prevent damage to the first sacrificial layer 23 when the word line 101 is subsequently formed. Process damage. Since the material of the initial sacrificial layer 24 is the first silicon germanium, it is easier to form the first silicon germanium on the surface of the silicon substrate than with other materials.
- an initial sacrificial layer 24 is first formed on the substrate 100 to form a stacked structure of the initial sacrificial layer 24 and the initial semiconductor pillar 20 .
- the initial sacrificial layer 24 reserves space for the subsequent formation of the first sacrificial layer 23 .
- the initial sacrificial layer 24 is removed, and the first sacrificial layer 23 is formed at the original position of the first sacrificial layer 23.
- the first sacrificial layer 23 reserves space for the subsequent formation of the conductive layer 102. In this way, the quality of the semiconductor structure formed in each step of the process is higher, so that the yield rate of the finally formed semiconductor structure is higher.
- a deposition process may be used to form the first sacrificial layer 23 in the first groove 26 , for example, it may be any one of a thermal oxidation process or an atomic layer deposition process.
- the material of the first sacrificial layer 23 may be silicon nitride.
- Figure 11 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5
- Figure 12 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5
- Figure 13 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5
- Figure 14 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5
- the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is etched to form the semiconductor pillar 10 and expose the top surface of the semiconductor pillar 10 , that is, the top surface of the semiconductor pillar 10 is exposed.
- the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is thinned. On the one hand, it is beneficial to reduce the size of the semiconductor pillar 10. On the other hand, it can reserve enough space for the subsequent formation of the word line 101 on the top surface of the semiconductor pillar 10. .
- the epitaxial process is used to form the initial sacrificial layer 24 between the surface of the silicon substrate and the initial semiconductor pillar 20, and the atomic radius of the germanium atom is larger than the atomic radius of the silicon atom, due to reasons such as stress and lattice defects, the epitaxial layer 24 is formed on the silicon substrate due to reasons such as stress and lattice defects.
- the thickness of the first silicon germanium layer is smaller.
- the thickness of the preformed initial semiconductor pillar 20 needs to be larger, so that the initial sacrificial layer 24 epitaxially formed on the surface of the initial semiconductor pillar 20 has a larger thickness. Based on this, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 needs to be etched subsequently, so that the thickness of the formed semiconductor pillar 10 meets the requirements.
- the exposed top surface of the semiconductor pillar 10 becomes the channel area. 11 on the top surface of the semiconductor pillar 10 .
- the word line 101 can be electrically connected to the surface of the semiconductor pillar 10 in the channel region 11 .
- the method of etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 includes:
- a second sacrificial layer 25 is formed stacked with the initial sacrificial layer 24 .
- the material of the second sacrificial layer 25 is second silicon germanium.
- the germanium content in the second silicon germanium is lower than that in the first silicon germanium.
- germanium content, and the second sacrificial layer 25 is in contact with the top surface of the initial semiconductor pillar 20; the etching amount of silicon germanium is related to the germanium content in silicon germanium.
- the germanium content in silicon germanium is higher, the etching amount of silicon germanium is The more difficult it is to etch silicon germanium, that is, the smaller the etching amount of silicon germanium is.
- the germanium content of the second silicon germanium is set to be lower than the germanium content of the first silicon germanium. In this way, when etching the first silicon germanium, the etching selection of the first silicon germanium and the second silicon germanium can be utilized. ratio, so that the etching process will not etch the second silicon germanium adjacent to the first silicon germanium, so that the morphology of the formed first sacrificial layer 23 meets expectations.
- the germanium content in the first silicon germanium may also be less than the germanium content in the second silicon germanium, as long as the germanium content in the first silicon germanium and the second germanium content are satisfied.
- the content of germanium in the silicon oxide can vary.
- a portion of the initial sacrificial layer 24 is removed to form a first sacrificial layer 23 .
- part of the second sacrificial layer 25 is removed to expose the top surface of the initial semiconductor pillar 20; that is, before etching the top surface of the initial semiconductor pillar 20, the second sacrificial layer 25 is first etched, to expose the top surface of the semiconductor pillar 10 .
- the process of etching the initial semiconductor pillar 20 is simpler, and the etching process formed after the etching is The top surface of the semiconductor pillar 10 is smoother and more in line with expectations.
- the top surface of the initial semiconductor pillar 20 is exposed, so that the gas or solution used in the etching process can evenly contact the top surface of the initial semiconductor pillar 20, and the etching process
- the contact area between the gas or liquid and the top surface of the semiconductor pillar 10 is large, which is beneficial to the etching process and makes the top surface of the formed semiconductor pillar 10 relatively smooth.
- the top surface of the initial semiconductor pillar 20 is etched to form the semiconductor pillar 10 .
- a word line 101 is formed on the top surface of the semiconductor pillar 10 in the channel region 11 .
- the formed word line 101 can also cover at least part of the top surface of the semiconductor pillar 10 . Both sides of the connection are connected, so that the word line 101 surrounds at least part of the side surfaces of the semiconductor pillar 10 of the channel area 11 , and the remaining part of the side surface of the semiconductor pillar 10 of the channel area 11 can be used to be electrically connected to the ground terminal, so that the channel area 11 The charge accumulated in can be discharged to the ground.
- the surface of the substrate 100 is provided with a plurality of semiconductor pillars 10 arranged in an array, and the plurality of semiconductor pillars 10 are arranged on the same layer.
- the word line 101 covers each semiconductor pillar 10 in a row arranged along the first direction X.
- a method of forming the word line 101 on the side of a portion of the semiconductor pillar 10 in the channel region 11 includes:
- Figure 16 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 15
- Figure 17 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 15
- Figure 19 corresponds to the schematic cross-sectional structure diagram in the aa' direction in Figure 18
- Figure 20 corresponds to Figure The schematic cross-sectional structural diagram in the aa' direction in Figure 18
- Figure 22 corresponds to the cross-sectional structural diagram in the aa' direction in Figure 5.
- an isolation structure 29 is formed.
- the isolation structure 29 is located between adjacent semiconductor pillars 10 along the first direction X and covers the side surfaces of the semiconductor pillars 10 in the channel region 11 .
- the isolation structure 29 is used to isolate adjacent semiconductor pillars 10 so that no electrical contact occurs between adjacent semiconductor pillars 10 along the first direction X.
- the method of forming the isolation structure 29 may include:
- a second dielectric layer 27 is formed on the top surface of each semiconductor pillar 10 .
- the second dielectric layer 27 fills the gap between the semiconductor pillar 10 and the first sacrificial layer 23 for subsequent formation of word lines. 101 reserved space.
- the second dielectric layer 27 can prevent the isolation structure 29 from being simultaneously formed between the top surface of the semiconductor pillar 10 and the first sacrificial layer 23 when the material of the isolation structure 29 is subsequently deposited to form the isolation structure 29 .
- a deposition process may be used to form the second dielectric layer 27.
- the material of the first sacrificial layer 23 is silicon nitride
- the material of the second dielectric layer 27 may be a low-k dielectric material.
- the etching selectivity can be used to remove only the second dielectric layer 27 while retaining the first sacrificial layer 23.
- the top surface of the top semiconductor pillar 10 is patterned to define the position of the semiconductor pillar 10 arranged in an array.
- a second mask layer 28 can be formed on the top surface of the top semiconductor pillar 10.
- the second mask layer 28 exposes the top surface of the semiconductor pillar 10 that needs to be etched.
- the silicon nitride layer in the cap layer 22 may be removed first, leaving only the silicon oxide layer, which is beneficial to the etching process. After removing the silicon nitride layer, a second mask layer 28 is formed on the surface of the silicon oxide layer.
- an etching process is performed on the top surface of the patterned semiconductor pillars 10 to form semiconductor pillars 10 arranged in an array, wherein a plurality of semiconductor pillars 10 are arranged at intervals along the first direction X, and adjacent semiconductor pillars There is a gap between 10.
- a deposition process is used to deposit an isolation material between adjacent semiconductor pillars 10 to form an isolation structure 29 .
- the isolation structure 29 fills the gap between adjacent semiconductor pillars 10 and covers each The side surface of the semiconductor pillar 10 .
- the material of the isolation structure 29 may be silicon oxide.
- Figure 24 corresponds to the schematic cross-sectional structural diagram in the direction aa’ in Figure 23
- Figure 25 corresponds to the schematic cross-sectional structural diagram in the direction bb’ in Figure 23.
- the isolation structure 29 After the isolation structure 29 is formed, refer to FIGS. 23 to 25 to remove the second dielectric layer 27 to expose the top surface of the semiconductor pillar 10 and the bottom surface of the first sacrificial layer 23 . In this way, the word line 101 can be formed on the exposed top surface of the semiconductor pillar 10 .
- Figure 27 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26;
- Figure 28 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.
- word lines 101 are formed on the top surface and part of the side surfaces of the semiconductor pillar 10 in the channel region 11 . Specifically, before forming the word line 101 , the top surface of the isolation structure 29 between adjacent semiconductor pillars 10 is etched until the isolation structure 29 has a preset thickness, so that there is a gap between adjacent semiconductor pillars 10 , and only a portion of the isolation structure 29 located between adjacent semiconductor pillars 10 is etched, so that the remaining portion of the isolation structure 29 located between the semiconductor pillars 10 can still play an isolation role.
- the word line 101 material when the word line 101 material is deposited on the top surface of the semiconductor pillar 10 to form the word line 101, the word line 101 can also be formed on the side of the semiconductor pillar 10, so that the word line 101 can cover the top surface of the semiconductor pillar 10 and connect with the top surface. Part of the side where the faces meet.
- the isolation structure 29 when the material of the isolation structure 29 is silicon oxide, in the step of etching the isolation structure 29 between adjacent semiconductor pillars 10, part of the isolation structure 29 located on the side of the semiconductor pillar 10 can be retained, so that Therefore, the isolation structure 29 located on the side of the semiconductor pillar 10 can serve as the gate dielectric layer 106 .
- the method of forming the word line 101 includes: forming a gate dielectric layer 106 on the top surface of the exposed semiconductor pillar 10, and the gate dielectric layer 106 is connected to the isolation structure 29 located on the side of the semiconductor pillar 10.
- a deposition process can be used to form the gate dielectric layer 106 on the top surface of the semiconductor pillar 10 , and the material of the gate dielectric layer 106 can be silicon oxide.
- a deposition process is used to form a barrier layer 107 on the surface of the gate dielectric layer 106.
- the material of the barrier layer 107 may be silicon nitride.
- a deposition process is used to form a word line 101 on the surface of the gate dielectric layer 106.
- the material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt or ruthenium.
- the gate dielectric layer 106 and the word line 101 are formed on the top surface of the semiconductor pillar 10 using a deposition process. at the same time, the first sacrificial layer 23 will also A first gate dielectric layer 32 and a first word line 31 are formed on the bottom surface.
- the deposition process is stopped, and the semiconductor pillar 10 is An initial dielectric layer 30 is formed between the word line 101 on the top surface and the first word line 31 on the bottom surface of the first sacrificial layer 23 for isolating the word line 101 on the top surface of the semiconductor pillar 10 and the first word line 31 on the bottom surface of the first sacrificial layer 23 Line 31.
- the word line 101 and the first word line 101 on the top surface of the semiconductor pillar 10 can be removed.
- the sacrificial layer 23 plays a protective role.
- Figure 29 corresponds to the schematic cross-sectional structural diagram in the direction aa' in Figure 26
- Figure 30 corresponds to the schematic cross-sectional structural diagram in the bb' direction in Figure 26.
- the first sacrificial layer 23 is removed to expose part of the bottom surface of the semiconductor pillar 10; the exposed bottom surface of the semiconductor pillar 10 can be used to form the conductive layer 102, so that the conductive layer 102 is connected to part of the trench.
- the surface of the semiconductor pillar 10 in the channel region 11 is electrically connected, and the conductive layer 102 is used for grounding, so that the charges accumulated in the channel region 11 can be discharged to the ground via the conductive layer 102 .
- Figure 31 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26;
- Figure 32 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.
- a conductive layer 102 is formed on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and the conductive layer 102 on the bottom surface of one semiconductor pillar 10 and the word line 101 on the top surface of the adjacent semiconductor pillar 10 are in a vertical position. adjacent in the direction of the base. Since multiple semiconductor pillars 10 are stacked and the conductive layer 102 is located on the bottom surface of the semiconductor pillar 10 and the word line 101 is located on the top surface of the semiconductor pillar 10, there is a conductive layer of one semiconductor pillar 10 between two adjacent semiconductor pillars 10. 102 is adjacent to the word line 101 of another semiconductor pillar 10 .
- first dielectric layer 104 In order to prevent adjacent word lines 101 from forming electrical contact with the conductive layer 102, in some embodiments, it also includes: forming a first dielectric layer 104.
- the first dielectric layer 104 is located on the adjacent word lines 101 in a direction perpendicular to the substrate. and the conductive layer 102.
- the material of the first dielectric layer 104 may be the same as the material of the initial dielectric layer 30 . This is because the initial dielectric layer 30 is located between adjacent semiconductor pillars 10 . Therefore, there is no need to remove the initial dielectric layer 30 formed in the previous steps. This is beneficial to saving process steps and saving materials for forming the first dielectric layer 104 .
- the material of the first dielectric layer 104 may be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.
- the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23 may be removed, and the initial dielectric layer 30 may be retained. In this way, it is possible to prevent the formation of the conductive layer 102 on the surface of the gate dielectric layer 106 on the bottom surface of the first sacrificial layer 23, and subsequent removal of the gate dielectric layer 106 and the word line 101 on the bottom surface of the first sacrificial layer 23, which may cause the conductive layer 102 to be produced. Damage issues.
- the material of the first dielectric layer 104 can be deposited on the top surface of the initial dielectric layer 30, so as to be consistent with the initial dielectric layer 30.
- the dielectric layers 30 together form the first dielectric layer 104 .
- a deposition process can be used to form the conductive layer 102 on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and due to the existence of the initial dielectric layer 30 , the formed conductive layer 102 will not interact with the top surface of another semiconductor pillar 10
- the word lines 101 form electrical contacts.
- the material of the conductive layer 102 may be polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide.
- the formed word line 101 covers part of the side surfaces of the semiconductor pillars 10 of the channel area 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 of the channel area 11 , so that the word line 101 is located in the channel area 11
- the word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel, and the side of the semiconductor pillar 10 of the exposed channel region 11 can be used for grounding; the formed conductive layer 102 is connected with the exposed
- the side surfaces of the semiconductor pillars 10 of the channel region 11 are electrically connected, and the conductive layer 102 is used to electrically connect with the ground terminal, so that the charges accumulated in the channel region 11 can be discharged to the ground terminal through the conductive layer 102, thereby preventing the floating body effect. produce.
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Abstract
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a preparation method for a semiconductor structure. The semiconductor structure comprises: a substrate; semiconductor columns, which are located on the substrate, wherein each semiconductor column is provided with a channel region and doped regions located on two opposite sides of the channel region; word lines, which cover some side faces in channel regions of the semiconductor columns and expose the remaining side faces in the channel regions of the semiconductor columns; and a conductive layer, which is electrically connected to at least some of the exposed side faces in the channel regions of the semiconductor columns, and is used for electrically connecting to a grounding end.
Description
交叉引用cross reference
本公开要求于2022年7月12日递交的名称为“半导体结构及半导体结构的制备方法”、申请号为202210819899.4的中国专利申请的优先权,其通过引用被全部并入本公开。This disclosure claims priority from the Chinese patent application titled "Semiconductor Structure and Preparation Method of Semiconductor Structure" and application number 202210819899.4, filed on July 12, 2022, which is fully incorporated by reference into this disclosure.
本公开实施例涉及半导体技术领域,特别涉及一种半导体结构及半导体结构的制备方法。Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
在场效应晶体管中,通常容易发生浮体效应,浮体效应是指,由于空穴在沟道中累积,导致沟道中产生了电压,从而使得漏端电流增大。浮体效应会导致器件的输出特性曲线有翘曲现象,即产生Kink效应,Kink效应对器件和电路性能以及可靠性产生诸多不利的影响。In field effect transistors, the floating body effect is usually prone to occur. The floating body effect means that due to the accumulation of holes in the channel, a voltage is generated in the channel, thereby increasing the drain current. The floating body effect will cause the output characteristic curve of the device to warp, that is, the Kink effect. The Kink effect has many adverse effects on device and circuit performance and reliability.
随着半导体器件的集成度提高,存储器例如动态随机存储器(DRAM)的尺寸越来越小,因此,3D DRAM的结构越来越受到重视。在3D DRAM结构中,半导体柱通常形成水平堆叠,字线或者位线通常成阶梯状排列,以节约空间,提高集成度。As the integration of semiconductor devices increases, the size of memories such as dynamic random access memory (DRAM) becomes smaller and smaller. Therefore, the structure of 3D DRAM is receiving more and more attention. In 3D DRAM structures, semiconductor pillars are usually stacked horizontally, and word lines or bit lines are usually arranged in a ladder-like manner to save space and improve integration.
然而,目前的半导体结构中,较容易发生浮体效应。However, in current semiconductor structures, floating body effects are more likely to occur.
发明内容Contents of the invention
本公开实施例提供一种半导体结构,包括:基底;位于基底上的半导体柱,半导体柱具有沟道区以及位于沟道区相对两侧的掺杂区;字线,字线包覆沟道区的部分半导体柱侧面,并露出沟道区的剩余部分半导体柱侧面;导电层,导电层与露出的沟道区的半导体柱的至少部分侧面电连接,且导电层用于与地端电连接。Embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; a word line, the word line covers the channel region part of the side of the semiconductor pillar, and expose the remaining part of the side of the semiconductor pillar in the channel area; a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and the conductive layer is used to be electrically connected to the ground.
在一些实施例中,在垂直于掺杂区指向沟道区的方向上,半导体柱的截面形状为矩形,字线露出半导体柱的其中一个侧面。In some embodiments, the cross-sectional shape of the semiconductor pillar is a rectangle in a direction perpendicular to the doping region and toward the channel region, and the word line exposes one side of the semiconductor pillar.
在一些实施例中,半导体柱平行于基底表面,字线平行于基底表面,且导电层与字线相对设置,还包括:导电柱,导电柱垂直于基底表面,导电柱与导电层电连接,且导电柱用于接地。In some embodiments, the semiconductor pillar is parallel to the substrate surface, the word line is parallel to the substrate surface, and the conductive layer is arranged opposite to the word line. It also includes: a conductive pillar, the conductive pillar is perpendicular to the substrate surface, and the conductive pillar is electrically connected to the conductive layer, And the conductive pillar is used for grounding.
在一些实施例中,导电层的材料与导电柱的材料相同。In some embodiments, the conductive layer is made of the same material as the conductive pillar.
在一些实施例中,导电层的材料包括:多晶硅或者掺杂硅、掺杂锗、氮化钛、氮化钽、钨、钛、钽、铜、铝、银、金、硅化钨、硅化钴、硅化钛中的至少一者。In some embodiments, the material of the conductive layer includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, At least one of titanium silicides.
在一些实施例中,基底表面设置有多个沿远离基底方向堆叠的半导体柱以及多条字线,其中,所述包覆半导体柱中的沟道区的部分半导体柱侧面,且半导体柱中,露出的沟道区的半导体柱的至少部分侧面与导电层电连接。In some embodiments, the substrate surface is provided with a plurality of semiconductor pillars stacked in a direction away from the substrate and a plurality of word lines, wherein the side surfaces of part of the semiconductor pillars covering the channel region in the semiconductor pillars are covered, and in the semiconductor pillars, At least part of the side surfaces of the exposed semiconductor pillars in the channel region are electrically connected to the conductive layer.
在一些实施例中,半导体结构还包括导电柱,导电柱与多个导电层电连接,且导电柱用于与地端电连接。In some embodiments, the semiconductor structure further includes a conductive pillar, the conductive pillar is electrically connected to the plurality of conductive layers, and the conductive pillar is used to be electrically connected to the ground.
在一些实施例中,还包括:位线,位线与一掺杂区的半导体柱端部电连接。
In some embodiments, a bit line is further included, and the bit line is electrically connected to an end of a semiconductor pillar in a doped region.
相应地,本公开实施例还提供一种半导体结构的制备方法,包括:提供基底;在基底上形成半导体柱,半导体柱具有沟道区以及位于沟道区相对两侧的掺杂区;形成字线,字线包覆沟道区的部分半导体柱侧面,并露出沟道区的剩余部分半导体柱侧面;形成导电层,导电层与露出的沟道区的半导体柱的至少部分侧面电连接,且导电层用于与地端电连接。Correspondingly, embodiments of the present disclosure also provide a method for preparing a semiconductor structure, including: providing a substrate; forming a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; forming a word line, the word line covers part of the side of the semiconductor pillar in the channel area, and exposes the remaining part of the side of the semiconductor pillar in the channel area; forming a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and The conductive layer is used for electrical connection with the ground terminal.
在一些实施例中,形成导电层以及字线的方法包括:在基底上形成至少两个沿远离基底方向堆叠的初始半导体柱;形成第一牺牲层,第一牺牲层位于相邻的初始半导体柱之间,且第一牺牲层至少覆盖沟道区的初始半导体柱表面;对第一牺牲层对应的初始半导体柱顶面进行刻蚀,形成半导体柱,并露出半导体柱的顶面;在沟道区的半导体柱顶面形成字线;去除第一牺牲层,露出部分半导体柱底面;在沟道区的半导体柱底面形成导电层,且位于一半导体柱底面的导电层与位于相邻的半导体柱顶面的字线在垂直于所述基底的方向上相邻。In some embodiments, a method for forming a conductive layer and a word line includes: forming at least two initial semiconductor pillars stacked in a direction away from the substrate on a substrate; forming a first sacrificial layer, the first sacrificial layer being located on an adjacent initial semiconductor pillar between, and the first sacrificial layer at least covers the surface of the initial semiconductor pillar in the channel area; etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer to form a semiconductor pillar and exposing the top surface of the semiconductor pillar; in the channel A word line is formed on the top surface of the semiconductor pillar in the channel area; the first sacrificial layer is removed to expose part of the bottom surface of the semiconductor pillar; a conductive layer is formed on the bottom surface of the semiconductor pillar in the channel area, and the conductive layer located on the bottom surface of one semiconductor pillar is in contact with the adjacent semiconductor pillar. Word lines on the top surface are adjacent in a direction perpendicular to the substrate.
在一些实施例中,基底为硅基底,形成第一牺牲层的方法包括:形成初始牺牲层,初始牺牲层位于相邻的初始半导体柱之间,初始牺牲层的材料包括第一锗化硅;去除部分初始牺牲层,形成第一凹槽,第一凹槽露出初始半导体柱的部分底面;在第一凹槽中形成第一牺牲层,第一牺牲层的材料与初始牺牲层的材料不同。In some embodiments, the substrate is a silicon substrate, and the method of forming the first sacrificial layer includes: forming an initial sacrificial layer, the initial sacrificial layer is located between adjacent initial semiconductor pillars, and the material of the initial sacrificial layer includes first silicon germanium; Part of the initial sacrificial layer is removed to form a first groove, which exposes part of the bottom surface of the initial semiconductor pillar; a first sacrificial layer is formed in the first groove, and the material of the first sacrificial layer is different from the material of the initial sacrificial layer.
在一些实施例中,对第一牺牲层对应的初始半导体柱顶面进行刻蚀的方法包括:形成与初始牺牲层堆叠设置的第二牺牲层,第二牺牲层的材料为第二锗化硅,第二锗化硅中的锗含量低于第一锗化硅中的锗含量,且第二牺牲层与初始半导体柱顶面相接触去除部分初始牺牲层,以形成第一牺牲层;去除部分第二牺牲层,露出初始半导体柱的顶面;对初始半导体柱顶面进行刻蚀,形成半导体柱。In some embodiments, the method of etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer includes: forming a second sacrificial layer stacked with the initial sacrificial layer, and the material of the second sacrificial layer is a second silicon germanium , the germanium content in the second silicon germanium is lower than the germanium content in the first silicon germanium, and the second sacrificial layer is in contact with the top surface of the initial semiconductor pillar and part of the initial sacrificial layer is removed to form the first sacrificial layer; part of the first sacrificial layer is removed The second sacrificial layer exposes the top surface of the initial semiconductor pillar; the top surface of the initial semiconductor pillar is etched to form a semiconductor pillar.
在一些实施例中,还包括:形成第一介质层,第一介质层位于在垂直于所述基底方向上相邻的字线与所述导电层之间。In some embodiments, the method further includes: forming a first dielectric layer, the first dielectric layer being located between an adjacent word line in a direction perpendicular to the substrate and the conductive layer.
在一些实施例中,第一介质层的材料包括:低k介质材料。In some embodiments, the material of the first dielectric layer includes: a low-k dielectric material.
在一些实施例中,基底表面设置有多个阵列排布的半导体柱,且多个半导体柱同层设置,字线包覆沿第一方向排列的一行半导体柱中的每一沟道区的部分半导体柱侧面,形成字线的方法包括:形成隔离结构,隔离结构位于沿第一方向相邻的半导体柱之间,并覆盖沟道区半导体柱侧面;对相邻的半导体柱之间的隔离结构顶面进行刻蚀,直至隔离结构具有预设厚度;在沟道区的半导体柱顶面以及部分侧面形成字线。In some embodiments, a plurality of semiconductor pillars arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars are arranged on the same layer, and the word line covers part of each channel region in a row of semiconductor pillars arranged along the first direction. On the side of the semiconductor pillar, the method of forming the word line includes: forming an isolation structure between adjacent semiconductor pillars along the first direction and covering the side of the semiconductor pillar in the channel region; The top surface is etched until the isolation structure has a predetermined thickness; a word line is formed on the top surface of the semiconductor pillar and part of the side surface of the channel area.
一个或多个实施例通过与之对应的附图中的图片进行示例性说明,这些示例性说明并不构成对实施例的限定,除非有特别申明,附图中的图不构成比例限制;为了更清楚地说明本公开实施例或传统技术中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.
图1为本公开一实施例提供的一种半导体结构的结构示意图;Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;
图2为本公开一实施例提供的一种半导体结构的俯视结构示意图;Figure 2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;
图3为本公开一实施例提供的一种半导体结构的剖视结构示意图;
Figure 3 is a schematic cross-sectional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;
图4至图32本公开另一实施例提供的半导体结构的制备方法中各步骤对应的结构示意图。4 to 32 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
由背景技术可知,目前的半导体结构中,存在可能发生浮体效应的问题。It can be known from the background art that there is a problem that the floating body effect may occur in current semiconductor structures.
分析发现,导致半导体结构产生浮体效应的原因之一在于,对于场效应晶体管而言,在足够高的漏端电压下,沟道的电子在漏端高场区获得足够能量,通过碰撞电离产生电子-空穴对,空穴向电势交底的沟道区处移动,由于栅源结较高的势垒,空穴会堆积在沟道区,从而抬高了沟道区的电势,使栅源结正偏。浮体上的正电位使阈值电压降低,漏端电流增大,从而产生了浮体效应。The analysis found that one of the reasons for the floating body effect in the semiconductor structure is that for field-effect transistors, under a sufficiently high drain terminal voltage, the electrons in the channel obtain enough energy in the high field region of the drain terminal to generate electrons through collision ionization. - Hole pairs, holes move to the channel area where the potentials are at the bottom. Due to the higher potential barrier of the gate-source junction, holes will accumulate in the channel area, thus raising the potential of the channel area and causing the gate-source junction to Positive deviation. The positive potential on the floating body reduces the threshold voltage and increases the drain current, thus producing the floating body effect.
本公开实施例提供一种半导体结构,通过设置字线包覆沟道区的部分半导体柱侧面,并露出沟道区的剩余部分半导体柱侧面,使得位于沟道区的半导体柱侧面的字线可以用于控制沟道的导通,露出的沟道区的半导体柱侧面可以用于接地;导电层与露出的沟道区的半导体柱侧面电连接,且导电层用于与地端电连接,使得沟道区中堆积的电荷可以通过导电层泄放至地端,从而防止浮体效应的产生。Embodiments of the present disclosure provide a semiconductor structure by arranging word lines to cover part of the semiconductor pillar side surfaces of the channel region and exposing the remaining semiconductor pillar side surfaces of the channel area, so that the word lines located on the semiconductor pillar side surfaces of the channel area can Used to control the conduction of the channel, the side of the exposed semiconductor pillar in the channel area can be used for grounding; the conductive layer is electrically connected to the side of the semiconductor pillar in the exposed channel area, and the conductive layer is used to be electrically connected to the ground terminal, so that The charges accumulated in the channel region can be discharged to the ground through the conductive layer, thereby preventing the floating body effect.
下面将结合附图对本公开的各实施例进行详细的阐述。然而,本领域的普通技术人员可以理解,在本公开各实施例中,为了使读者更好地理解本公开而提出了许多技术细节。但是,即使没有这些技术细节和基于以下各实施例的种种变化和修改,也可以实现本公开所要求保护的技术方案。Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to allow the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.
图1为本公开一实施例提供的一种半导体结构的结构示意图,图2为本公开一实施例提供的一种半导体结构的俯视结构示意图;图3为本公开一实施例提供的一种半导体结构的剖视结构示意图。FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Schematic cross-section of the structure.
参考图1至图3,半导体结构包括:基底;位于基底上的半导体柱10,半导体柱10具有沟道区11以及位于沟道区11相对两侧的掺杂区12;字线101,字线101包覆沟道区11的部分半导体柱10侧面,并露出沟道区11的剩余部分半导体柱10侧面;导电层102,导电层102与露出的沟道区11的半导体柱10的至少部分侧面电连接,且导电层102用于与地端电连接。Referring to FIGS. 1 to 3 , the semiconductor structure includes: a substrate; a semiconductor pillar 10 located on the substrate, the semiconductor pillar 10 having a channel region 11 and doped regions 12 located on opposite sides of the channel region 11 ; a word line 101 . 101 covers part of the side surfaces of the semiconductor pillars 10 in the channel region 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; the conductive layer 102, the conductive layer 102 and at least part of the side surfaces of the semiconductor pillars 10 in the channel area 11 are exposed Electrically connected, and the conductive layer 102 is used to be electrically connected to the ground.
设置导电层102与露出的沟道区11的半导体柱10侧面电连接,使得沟道区11中的电荷可以传输至导电层102中,再经由导电层102泄放至地端,从而可以防止发生由于过多的电荷在沟道区11中累积而产生浮体效应的问题。The conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charges in the channel region 11 can be transferred to the conductive layer 102, and then discharged to the ground via the conductive layer 102, thus preventing the occurrence of The problem of floating body effect occurs due to excessive charge accumulation in the channel region 11 .
基底的材料为半导体材料。在一些实施例中,基底的材料为硅。在另一些实施例中,基底也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。The material of the substrate is a semiconductor material. In some embodiments, the material of the substrate is silicon. In other embodiments, the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon on insulator substrate.
半导体柱10的材料可以与基底的材料相同。在一些实施例中,半导体柱10的材料可以为硅。The material of the semiconductor pillar 10 may be the same as the material of the substrate. In some embodiments, the material of the semiconductor pillar 10 may be silicon.
沟道区11以及位于沟道区11两侧的掺杂区12可以用于构成一个晶体管,其中,位于沟道区11两侧的掺杂区12可以作为晶体管的源极或者漏极中的一者。字线101可以作为半导体结构的栅极,用于基于控制信号导通沟道区11,实现源极与漏极之间的载流子传输。在一些实施例中,沟道区11的掺杂离子类型可以与掺杂区12的掺杂离子类型不同,从而形成有结晶体管,例如,例如沟道区11中的掺杂离子类型可以为P型,掺杂区12中的掺杂离子类型可以为N型,构成NMOS晶体管。当半导体结构形成NMOS晶体管时,电子在沟道中移动,沟道中的电子在漏端高场区中获得足够的能量而产生电子-空穴对,使得空穴向电势较低的沟道区11处移动。即空穴由漏极向源极移动,由于栅源结具有较高的势垒,使得空穴在沟道区11堆积。因此,设置导电层102与露出的沟道区11的半导体柱10侧面电连接,当空穴由漏极向源极移动至沟道区11中时,会通过导电层102泄放至地端,从而避免产生浮体效应。
The channel region 11 and the doped regions 12 located on both sides of the channel region 11 can be used to form a transistor, wherein the doped regions 12 located on both sides of the channel region 11 can serve as one of the source or drain of the transistor. By. The word line 101 may serve as a gate of the semiconductor structure, and is used to conduct the channel region 11 based on the control signal to realize carrier transfer between the source and the drain. In some embodiments, the doping ion type of the channel region 11 may be different from the doping ion type of the doping region 12 , thereby forming a junction transistor. For example, the doping ion type in the channel region 11 may be P. Type, the type of doping ions in the doping region 12 may be N-type, forming an NMOS transistor. When the semiconductor structure forms an NMOS transistor, electrons move in the channel, and the electrons in the channel obtain enough energy in the high field region of the drain end to generate electron-hole pairs, causing the holes to move toward the channel region 11 with a lower potential. move. That is, holes move from the drain to the source. Since the gate-source junction has a high potential barrier, holes accumulate in the channel region 11 . Therefore, the conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11. When holes move from the drain to the source into the channel region 11, they will be discharged to the ground through the conductive layer 102, thereby Avoid floating body effect.
在另一些实施例中,沟道区11的掺杂离子类型也可以与掺杂区12的掺杂离子类型相同,形成无结晶体管。In other embodiments, the doping ion type of the channel region 11 may be the same as the doping ion type of the doping region 12 to form a junctionless transistor.
在一些实施例中,在垂直于掺杂区12指向沟道区11的方向上,半导体柱10的截面形状为矩形,字线101露出半导体柱10的其中一个侧面。也就是说,字线101环绕半导体柱10的三个侧面设置,如此,使得字线101与沟道区11的半导体柱10之间的接触面积较大,从而可以增加形成的沟道的面积以及长度,增强字线101对沟道的控制能力,同时还有利于减小漏电流。设置字线101露出半导体柱10的一个侧面,用于与导电层102形成电连接。被字线101露出的侧面与字线101正对设置,导电层102与露出的侧面电连接,使得导电层102与字线101之间的距离较大,从而可以防止在实际制备导电层102的工艺中,由于与字线101之间的距离过近而导致形成的导电层102与字线101形成电连接的问题。具体地,在一些实施例中,字线101可以完全覆盖半导体柱10的三个侧面,以增加字线101与半导体柱10之间的接触面积。在另一些实施例中,字线101也可以覆盖与露出的半导体柱10侧面相对的半导体柱10侧面,并覆盖部分剩余的两个半导体柱10侧面,使得字线101到露出的半导体柱10侧面之间的距离较大。从而当导电层102与露出的半导体柱10侧面形成电连接时,导电层102与字线101之间的距离更大,进一步防止发生导电层102与字线101接触的问题。In some embodiments, the cross-sectional shape of the semiconductor pillar 10 is rectangular in a direction perpendicular to the doping region 12 and directed toward the channel region 11 , and the word line 101 exposes one side of the semiconductor pillar 10 . That is to say, the word line 101 is arranged around three sides of the semiconductor pillar 10, so that the contact area between the word line 101 and the semiconductor pillar 10 in the channel region 11 is larger, thereby increasing the area of the formed channel and The length enhances the ability of the word line 101 to control the channel and also helps reduce leakage current. The word line 101 is arranged to expose one side of the semiconductor pillar 10 for forming an electrical connection with the conductive layer 102 . The side surface exposed by the word line 101 is arranged opposite to the word line 101, and the conductive layer 102 is electrically connected to the exposed side surface, so that the distance between the conductive layer 102 and the word line 101 is large, thereby preventing the actual preparation of the conductive layer 102. During the process, the distance between the conductive layer 102 and the word line 101 is too close, resulting in the problem of electrical connection between the formed conductive layer 102 and the word line 101 . Specifically, in some embodiments, the word line 101 may completely cover three sides of the semiconductor pillar 10 to increase the contact area between the word line 101 and the semiconductor pillar 10 . In other embodiments, the word line 101 may also cover the side of the semiconductor pillar 10 opposite to the exposed side of the semiconductor pillar 10 , and partially cover the remaining two sides of the semiconductor pillar 10 , so that the word line 101 reaches the side of the exposed semiconductor pillar 10 The distance between them is large. Therefore, when the conductive layer 102 forms an electrical connection with the exposed side of the semiconductor pillar 10 , the distance between the conductive layer 102 and the word line 101 is larger, further preventing the problem of contact between the conductive layer 102 and the word line 101 .
在一些实施例中,半导体柱10平行于基底表面,字线101平行于基底表面,且导电层102与字线101相对设置,还包括:导电柱103,导电柱103垂直于基底表面,导电柱103与导电层102电连接,且导电柱103用于接地。设置半导体柱10平行于基底表面设置,且字线101平行于基底表面,使得在垂直于基底的方向上,半导体柱10以及字线101所占用的尺寸较小,从而有利于形成半导体柱10的堆叠结构,提高形成的半导体结构的集成度。设置导电层102与字线101相对设置,可以防止导电层102与字线101由于距离过近而电接触的问题。由于字线101平行于基底表面,使得导电层102也平行于基底表面,而半导体结构的整体尺寸较小,当导电层102平行于基底表面设置时,可能会导致导电层102无法引出接地的问题。基于此,设置导电柱103,导电柱103垂直于基底表面,即垂直于导电层102设置,不仅使得导电柱103易于与地端形成电连接,且导电层102中传输的电荷可以通过导电柱103泄放至地端,并且还有利于降低制备半导体结构的工艺难度。In some embodiments, the semiconductor pillar 10 is parallel to the substrate surface, the word line 101 is parallel to the substrate surface, and the conductive layer 102 is arranged opposite to the word line 101. It also includes: a conductive pillar 103, the conductive pillar 103 is perpendicular to the substrate surface, and the conductive pillar 103 is perpendicular to the substrate surface. 103 is electrically connected to the conductive layer 102, and the conductive pillar 103 is used for grounding. The semiconductor pillars 10 are arranged parallel to the substrate surface, and the word lines 101 are parallel to the substrate surface, so that in the direction perpendicular to the substrate, the sizes occupied by the semiconductor pillars 10 and the word lines 101 are smaller, which is beneficial to the formation of the semiconductor pillars 10 The stacked structure improves the integration of the formed semiconductor structure. Arranging the conductive layer 102 and the word line 101 to face each other can prevent the problem of electrical contact between the conductive layer 102 and the word line 101 due to being too close. Since the word line 101 is parallel to the substrate surface, the conductive layer 102 is also parallel to the substrate surface, and the overall size of the semiconductor structure is small. When the conductive layer 102 is arranged parallel to the substrate surface, it may cause the problem that the conductive layer 102 cannot be connected to the ground. . Based on this, the conductive pillars 103 are arranged perpendicular to the surface of the substrate, that is, perpendicular to the conductive layer 102 . This not only makes it easy for the conductive pillars 103 to form an electrical connection with the ground, but also allows the charges transmitted in the conductive layer 102 to pass through the conductive pillars 103 It is discharged to the ground and is also helpful in reducing the process difficulty of preparing semiconductor structures.
在一些实施例中,导电层102的材料与导电柱103的材料相同。设置导电层102的材料与导电柱103的材料相同,使得导电层102与导电柱103对电荷的传输能力接近或者相同,从而使得当电荷由导电层102传输至导电柱103时,可以保持较快的传输速率,使得沟道区11中堆积的电荷可以较快速地泄放至地端,避免产生浮体效应,保持半导体结构正常的性能。In some embodiments, the conductive layer 102 is made of the same material as the conductive pillars 103 . The conductive layer 102 is made of the same material as the conductive pillar 103 , so that the charge transmission capabilities of the conductive layer 102 and the conductive pillar 103 are close to or the same, so that when the charge is transferred from the conductive layer 102 to the conductive pillar 103 , the charge can be kept relatively fast. The transmission rate allows the charges accumulated in the channel region 11 to be discharged to the ground more quickly, thereby avoiding the floating body effect and maintaining the normal performance of the semiconductor structure.
在一些实施例中,导电层102的材料包括:多晶硅或者掺杂硅、掺杂锗、氮化钛、氮化钽、钨、钛、钽、铜、铝、银、金、硅化钨、硅化钴、硅化钛中的至少一者。在一些实施例中,基底为硅基底,且半导体柱10的材料与基底相同,即半导体柱10的材料为硅,如此,使得导电层102中具有与半导体柱10相同的元素,即导电层102的材料特性与半导体柱10的材料特性接近。因此,当堆积于沟道区11的半导体柱10中的电荷传输至导电层102中时,由于导电层102的材料特性与半导体柱10的材料特性相近,使得电荷传输的阻力较小,有利于实现电荷的快速泄放。In some embodiments, the material of the conductive layer 102 includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide. In some embodiments, the substrate is a silicon substrate, and the material of the semiconductor pillar 10 is the same as the substrate, that is, the material of the semiconductor pillar 10 is silicon. In this way, the conductive layer 102 has the same elements as the semiconductor pillar 10 , that is, the conductive layer 102 The material properties of are close to those of the semiconductor pillar 10 . Therefore, when the charges accumulated in the semiconductor pillars 10 in the channel region 11 are transferred to the conductive layer 102, since the material properties of the conductive layer 102 are similar to the material properties of the semiconductor pillars 10, the resistance to charge transfer is small, which is beneficial to Achieve rapid discharge of charge.
在一些实施例中,基底表面设置有多个沿远离基底方向堆叠的半导体柱10以及多条字线101,其中,所述包覆半导体柱10中的沟道区11的部分半导体柱10侧面,且半导体柱10中,露出的沟道区11的半导体柱10的至少部分侧面与导电层102电连接。每一半导体柱10用于形成一个晶体管,设置多个半导体柱10堆叠于基底表面,从而可以形成多个晶体管,且堆叠设置的半导体柱10占用尺寸较小,有利于
提高形成的半导体结构的集成度。当半导体柱10的数量为多个时,每一半导体柱10的沟道区11均需要与字线101电连接,从而使得字线101可以控制沟道区11的导通。为了减小字线101占用的面积,设置字线101平行于基底表面,从而可以减小字线101在垂直于基底表面方向上的尺寸,进而减小半导体结构的整体尺寸。基于此,设置堆叠的半导体柱10中,每一半导体柱10与一字线101对应,即每一字线101与每一半导体柱10中的沟道区11电连接,从而可以在保持半导体结构的尺寸较小的同时,实现对每一半导体柱10的沟道区11的控制。由于导电层102与字线101相对设置,当字线101平行于基底表面时,导电层102与基底平行,从而防止导电层102与字线101电接触。基于此,设置堆叠的半导体柱10中,每一露出的沟道区11的半导体柱10侧面分别与一导电层102电连接,从而使得堆叠设置的半导体柱10之间不会形成电接触而产生电干扰,且每一沟道区11中堆积的电荷均可以通过导电层102泄放至地端。In some embodiments, the substrate surface is provided with a plurality of semiconductor pillars 10 stacked in a direction away from the substrate and a plurality of word lines 101, wherein the side surfaces of part of the semiconductor pillar 10 covering the channel region 11 in the semiconductor pillar 10, In addition, in the semiconductor pillar 10 , at least part of the side surfaces of the semiconductor pillar 10 in the exposed channel region 11 is electrically connected to the conductive layer 102 . Each semiconductor pillar 10 is used to form a transistor. Multiple semiconductor pillars 10 are stacked on the surface of the substrate, so that multiple transistors can be formed. Moreover, the stacked semiconductor pillars 10 occupy a smaller size, which is beneficial to Improve the integration level of the formed semiconductor structure. When there are multiple semiconductor pillars 10 , the channel region 11 of each semiconductor pillar 10 needs to be electrically connected to the word line 101 so that the word line 101 can control the conduction of the channel region 11 . In order to reduce the area occupied by the word line 101, the word line 101 is set parallel to the substrate surface, so that the size of the word line 101 in the direction perpendicular to the substrate surface can be reduced, thereby reducing the overall size of the semiconductor structure. Based on this, among the stacked semiconductor pillars 10 , each semiconductor pillar 10 corresponds to a word line 101 , that is, each word line 101 is electrically connected to the channel region 11 in each semiconductor pillar 10 , so that the semiconductor structure can be maintained. While the size is small, the channel region 11 of each semiconductor pillar 10 can be controlled. Since the conductive layer 102 is arranged opposite to the word line 101, when the word line 101 is parallel to the substrate surface, the conductive layer 102 is parallel to the substrate, thereby preventing the conductive layer 102 from electrical contact with the word line 101. Based on this, in the stacked semiconductor pillars 10 , the side surfaces of each exposed semiconductor pillar 10 in the channel region 11 are electrically connected to a conductive layer 102 respectively, so that no electrical contact is formed between the stacked semiconductor pillars 10 . Electrical interference occurs, and the charges accumulated in each channel region 11 can be discharged to the ground through the conductive layer 102 .
在一些实施例中,半导体结构还包括导电柱103,导电柱103与多个导电层102电连接,且导电柱103用于与地端电连接。当基底表面设置有多个堆叠的半导体柱10时,每一半导体柱10均对应一个导电层102,且导电层102平行于基底表面设置,即相当于导电层102堆叠设置。而由于导电柱103垂直于导电层102设置,用于将导电层102接地,且导电柱103不与半导体柱10形成电连接,即无需考虑导电柱103与半导体柱10之间是否会形成电接触的问题。因此,可以仅设置一个导电柱103与多个堆叠的导电层102电连接,相较于一个导电柱103与一个导电层102对应电连接而言,大大减小了导电柱103的尺寸,从而减小半导体结构的尺寸。且每一导电层102中传输的电荷均可以通过同一导电柱103泄放至地端。In some embodiments, the semiconductor structure further includes conductive pillars 103, the conductive pillars 103 are electrically connected to the plurality of conductive layers 102, and the conductive pillars 103 are used to be electrically connected to the ground. When a plurality of stacked semiconductor pillars 10 are provided on the substrate surface, each semiconductor pillar 10 corresponds to a conductive layer 102 , and the conductive layer 102 is arranged parallel to the substrate surface, which is equivalent to a stacked arrangement of the conductive layers 102 . Since the conductive pillars 103 are arranged perpendicular to the conductive layer 102 for grounding the conductive layer 102, and the conductive pillars 103 do not form an electrical connection with the semiconductor pillars 10, that is, there is no need to consider whether electrical contact will be formed between the conductive pillars 103 and the semiconductor pillars 10. The problem. Therefore, only one conductive pillar 103 can be provided to be electrically connected to multiple stacked conductive layers 102. Compared with one conductive pillar 103 being electrically connected to one conductive layer 102, the size of the conductive pillar 103 is greatly reduced, thereby reducing size of small semiconductor structures. And the charges transmitted in each conductive layer 102 can be discharged to the ground through the same conductive pillar 103 .
在一些实施例中,半导体柱10远离基底的一面与字线101形成电连接,半导体柱10朝向基底的一面与导电层102形成电连接。当基底表面设置多个堆叠的半导体柱10时,其中一个半导体柱10对应的字线101将与相邻的半导体柱10对应的导电层102相邻设置。基于此,在一些实施例中,还包括:第一介质层104,第一介质层104位于相邻的字线101与导电层102之间,用于隔离相邻的字线101与导电层102,防止字线101与导电层102形成电连接而产生电干扰的问题。具体地,在一些实施例中,第一介质层104的材料可以为低k介质材料。在另一些实施例中,第一介质层104的材料还可以为氮化物中的一种,例如可以为氮化硅。In some embodiments, the side of the semiconductor pillar 10 away from the substrate is electrically connected to the word line 101 , and the side of the semiconductor pillar 10 facing the substrate is electrically connected to the conductive layer 102 . When multiple stacked semiconductor pillars 10 are provided on the surface of the substrate, the word line 101 corresponding to one of the semiconductor pillars 10 will be arranged adjacent to the conductive layer 102 corresponding to the adjacent semiconductor pillar 10 . Based on this, in some embodiments, a first dielectric layer 104 is also included. The first dielectric layer 104 is located between the adjacent word line 101 and the conductive layer 102 and is used to isolate the adjacent word line 101 and the conductive layer 102. , to prevent the word line 101 and the conductive layer 102 from forming an electrical connection and causing electrical interference. Specifically, in some embodiments, the material of the first dielectric layer 104 may be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.
在一些实施例中,还包括:位线105,位线105与一掺杂区12的半导体柱10端部电连接。如此,使得位线105可以引出位于沟道区11一侧的掺杂区12的电信号。此外,由于半导体柱10端部处具有较大的操作空间,使得实际在制备位线105的工艺中,可以降低在半导体柱10端部处制备位线105的工艺难度,有利于提高半导体结构的良率。In some embodiments, a bit line 105 is also included, and the bit line 105 is electrically connected to an end of the semiconductor pillar 10 of a doped region 12 . In this way, the bit line 105 can extract electrical signals from the doped region 12 located on one side of the channel region 11 . In addition, since there is a large operating space at the end of the semiconductor pillar 10, the process difficulty of preparing the bit line 105 at the end of the semiconductor pillar 10 can be reduced, which is beneficial to improving the quality of the semiconductor structure. Yield.
在一些实施例中,基底表面设置有多个阵列排布的半导体柱10,且多个半导体柱10同层设置,字线101包覆沿第一方向X排列的一行半导体柱10中的每一沟道区11的部分半导体柱10侧面,且沿第二方向Y排布的一列半导体柱10中,相邻的两个半导体柱10中的一掺杂区12与同一位线105电连接,第一方向X平行于基底表面,第二方向Y为多个半导体柱10的堆叠方向。第一方向X与第二方向Y不同,在基底表面设置多个阵列排布的半导体柱10,有利于增加半导体柱10的排列密度,从而增加半导体柱10的集成度。多个阵列排布的半导体柱10同层设置,也就是说,阵列排布的半导体柱10不是堆叠设置的。当基底表面具有多个堆叠设置的半导体柱10时,堆叠设置的半导体柱10不处于同一层,堆叠设置的半导体柱10中,每一半导体柱10所在的层均具有多个阵列排布的半导体柱10。也就是说,当基底表面设置有多个半导体柱10时,可以将多个半导体柱10分别设置于不同层,每一层的半导体柱10阵列排布,且阵列排布的半导体柱10可以堆叠设置,如此,可以进一步增加半导体柱10的排列密度,使得半导体柱10的集成度更高。
In some embodiments, a plurality of semiconductor pillars 10 arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars 10 are arranged on the same layer. The word line 101 covers each of a row of semiconductor pillars 10 arranged along the first direction X. On some side surfaces of the semiconductor pillars 10 of the channel region 11 and in a row of semiconductor pillars 10 arranged along the second direction Y, a doping region 12 in two adjacent semiconductor pillars 10 is electrically connected to the same bit line 105. One direction X is parallel to the substrate surface, and the second direction Y is the stacking direction of the plurality of semiconductor pillars 10 . The first direction X is different from the second direction Y. Arranging a plurality of semiconductor pillars 10 arranged in an array on the surface of the substrate is beneficial to increasing the arrangement density of the semiconductor pillars 10 and thereby increasing the integration level of the semiconductor pillars 10 . A plurality of semiconductor pillars 10 arranged in an array are arranged on the same layer. That is to say, the semiconductor pillars 10 arranged in an array are not stacked. When there are multiple semiconductor pillars 10 stacked on the surface of the substrate, the stacked semiconductor pillars 10 are not in the same layer. In the stacked semiconductor pillars 10 , the layer where each semiconductor pillar 10 is located has multiple semiconductors arranged in an array. Column 10. That is to say, when multiple semiconductor pillars 10 are provided on the surface of the substrate, the multiple semiconductor pillars 10 can be arranged in different layers. The semiconductor pillars 10 of each layer are arranged in an array, and the semiconductor pillars 10 arranged in the array can be stacked. In this way, the arrangement density of the semiconductor pillars 10 can be further increased, making the semiconductor pillars 10 more integrated.
每一层阵列排布的半导体柱10中,半导体柱10的排布方向均平行于基底表面,且字线101也平行于基底表面,因此,可以设置字线101将沿第一方向X排列的一行半导体柱10中的每一沟道区11的部分半导体柱10侧面包覆,即沿第一方向X排列的多个半导体柱10可以共用同一字线101,如此,可以节约形成的字线101的体积,从而减小半导体结构的整体尺寸。Among the semiconductor pillars 10 arranged in an array in each layer, the arrangement direction of the semiconductor pillars 10 is parallel to the substrate surface, and the word lines 101 are also parallel to the substrate surface. Therefore, the word lines 101 can be arranged to be arranged along the first direction X. Part of the semiconductor pillars 10 of each channel region 11 in a row of semiconductor pillars 10 is covered on the side, that is, multiple semiconductor pillars 10 arranged along the first direction volume, thereby reducing the overall size of the semiconductor structure.
位线105垂直于字线101设置,也就是说,位线105与多个半导体柱10的堆叠方向相同。因此,可以设置位线105与沿第二方向Y排列的一列半导体柱10中的其中一掺杂区12形成电连接,使得堆叠设置的半导体柱10可以共用同一位线105,从而还可以进一步使得位线105所占用的体积较小,从而进一步减小半导体结构的整体尺寸。The bit line 105 is disposed perpendicularly to the word line 101 , that is, the bit line 105 has the same stacking direction as the plurality of semiconductor pillars 10 . Therefore, the bit line 105 can be set to be electrically connected to one of the doped regions 12 in a row of semiconductor pillars 10 arranged along the second direction Y, so that the stacked semiconductor pillars 10 can share the same bit line 105, which can further enable The bit line 105 occupies a smaller volume, thereby further reducing the overall size of the semiconductor structure.
在一些实施例中,位线105可以包括沿远离半导体柱10方向依次堆叠的阻挡层、导电部以及绝缘层。在一些实施例中,导电部可以是金属材料,例如可以是钨、铜或者铝中的任一种,在另一些实施例中,导电部也可以是半导体材料,例如可以是多晶硅。阻挡层防止导电部与掺杂区12之间的相互扩散,阻挡层的材料可以是氮化钛,绝缘层用于隔离导电部与半导体结构中的其它导电器件,绝缘层的材料可以是氧化硅或者氮化硅中的任一种。In some embodiments, the bit line 105 may include a barrier layer, a conductive portion, and an insulating layer sequentially stacked in a direction away from the semiconductor pillar 10 . In some embodiments, the conductive part may be a metal material, such as any one of tungsten, copper, or aluminum. In other embodiments, the conductive part may also be a semiconductor material, such as polysilicon. The barrier layer prevents mutual diffusion between the conductive part and the doped region 12. The material of the barrier layer may be titanium nitride. The insulating layer is used to isolate the conductive part from other conductive devices in the semiconductor structure. The material of the insulating layer may be silicon oxide. Or any of silicon nitride.
在一些实施例中,在一些实施例中,字线101的材料可以为钨、钼、钛、钴或者钌中的至少一者。In some embodiments, the material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.
在一些实施例中,还可以包括:栅介质层106,栅介质层106位于字线101与沟道区11的半导体柱10之间。栅介质层106用于将字线101与沟道区11的半导体柱10隔离开来,栅介质层106位于沟道区11的半导体柱10表面,使得由半导体柱10构成的晶体管成为低压器件。换句话说,由于栅介质层106的存在,使得对晶体管施加较小的电压,便能导通晶体管,完成数据的写入,从而有利于改善半导体结构的性能。在一些实施例中,栅介质层106的材料可以包括氧化硅、氮化硅或者氮氧化硅中的至少一种。还包括:阻挡层107,阻挡层107位于栅介质层106与字线101之间,防止栅介质层106与字线101中的离子相互扩散,阻挡层107的材料可以包括氮化钛。In some embodiments, a gate dielectric layer 106 may also be included. The gate dielectric layer 106 is located between the word line 101 and the semiconductor pillar 10 of the channel region 11 . The gate dielectric layer 106 is used to isolate the word line 101 from the semiconductor pillar 10 in the channel region 11. The gate dielectric layer 106 is located on the surface of the semiconductor pillar 10 in the channel area 11, so that the transistor composed of the semiconductor pillar 10 becomes a low-voltage device. In other words, due to the existence of the gate dielectric layer 106, a smaller voltage is applied to the transistor to turn on the transistor and complete the writing of data, which is beneficial to improving the performance of the semiconductor structure. In some embodiments, the material of the gate dielectric layer 106 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It also includes: a barrier layer 107. The barrier layer 107 is located between the gate dielectric layer 106 and the word line 101 to prevent mutual diffusion of ions in the gate dielectric layer 106 and the word line 101. The material of the barrier layer 107 may include titanium nitride.
在一些实施例中,还包括:电容结构108,电容结构108与半导体柱10中的另一掺杂区12电连接。即位线105与电容结构108分别与半导体柱10中的两个掺杂区12电连接。具体地,电容结构108可以包括沿远离半导体柱10方向依次堆叠的下电极层(未图示)、电容介质层(未图示)以及上电极层(未图示),其中,下电极层的材料和上电极层的材料可以相同,下电极层的材料和上电极层的材料均可以为镍化铂、钛、钽、钴、多晶硅、铜、钨、氮化钽、氮化钛或者钌中的至少一种。在另一些实施例中,下电极层的材料和上电极层的材料也可以不同。电容介质层的材料包括氧化硅、氧化钽、氧化铪、氧化锆、氧化铌、氧化钛等高介电常数材料。In some embodiments, a capacitor structure 108 is also included, and the capacitor structure 108 is electrically connected to another doped region 12 in the semiconductor pillar 10 . That is, the bit line 105 and the capacitor structure 108 are electrically connected to the two doped regions 12 in the semiconductor pillar 10 respectively. Specifically, the capacitive structure 108 may include a lower electrode layer (not shown), a capacitive dielectric layer (not shown), and an upper electrode layer (not shown) sequentially stacked in a direction away from the semiconductor pillar 10 , wherein the lower electrode layer The material and the material of the upper electrode layer can be the same. The material of the lower electrode layer and the material of the upper electrode layer can be platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium. of at least one. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different. The materials of the capacitor dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, and titanium oxide.
上述实施例提供的半导体结构的技术方案中,设置字线101包覆沟道区11的部分半导体侧面,并露出沟道区11的剩余部分半导体柱10侧面,如此,使得位于沟道区11的半导体柱10侧面的字线101可以用于控制沟道区11的导通;导电层102与露出的沟道区11的半导体柱10侧面电连接,且导电层102用于与地端电连接,使得沟道区11中堆积的电荷可以通过导电层102泄放至地端,从而防止浮体效应的产生。In the technical solution of the semiconductor structure provided by the above embodiments, the word line 101 is arranged to cover part of the semiconductor side surfaces of the channel region 11 and expose the remaining part of the semiconductor pillar 10 side surfaces of the channel region 11. In this way, the semiconductor pillars 10 located in the channel region 11 are exposed. The word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel area 11; the conductive layer 102 is electrically connected to the exposed side of the semiconductor pillar 10 of the channel area 11, and the conductive layer 102 is used to be electrically connected to the ground. This allows the charges accumulated in the channel region 11 to be discharged to the ground through the conductive layer 102, thereby preventing the floating body effect from occurring.
相应地,本公开实施例还提供一种半导体结构的制备方法,该半导体结构的制备方法可用于制备上述实施例提供的半导体结构,以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。Correspondingly, embodiments of the present disclosure also provide a method for preparing a semiconductor structure. The method of preparing a semiconductor structure can be used to prepare the semiconductor structure provided by the above embodiments. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. illustrate.
图6对应于图5中aa’方向的剖面结构示意图。
Figure 6 corresponds to the schematic cross-sectional structural diagram in the aa' direction in Figure 5.
参考图4以及图6,提供基底100,在一些实施例中,基底100的材料为硅。在另一些实施例中,基底100也可以为锗基底、锗硅基底、碳化硅基底或者绝缘体上的硅基底。Referring to FIG. 4 and FIG. 6 , a substrate 100 is provided. In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
参考图7至图32,在基底100上形成半导体柱10,半导体柱10具有沟道区11以及位于沟道区11相对两侧的掺杂区12;形成字线101,字线101包覆沟道区11的部分半导体柱10侧面,并露出沟道区11的剩余部分半导体柱10侧面;形成导电层102,导电层102与露出的沟道区11的半导体柱10的至少部分侧面电连接,且导电层102用于与地端电连接。Referring to Figures 7 to 32, a semiconductor pillar 10 is formed on a substrate 100. The semiconductor pillar 10 has a channel region 11 and doping regions 12 located on opposite sides of the channel region 11; a word line 101 is formed, and the word line 101 covers the trench. part of the side surfaces of the semiconductor pillars 10 in the channel area 11, and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; a conductive layer 102 is formed, and the conductive layer 102 is electrically connected to at least part of the side surfaces of the exposed semiconductor pillars 10 in the channel area 11, And the conductive layer 102 is used for electrical connection with the ground.
设置导电层102与露出的沟道区11的半导体柱10侧面电连接,使得沟道区11中的电荷可以传输至导电层102中,再经由导电层102泄放至地端,从而可以防止发生由于过多的电荷在沟道区11中累积而产生浮体效应的问题。The conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charges in the channel region 11 can be transferred to the conductive layer 102, and then discharged to the ground via the conductive layer 102, thus preventing the occurrence of The problem of floating body effect occurs due to excessive charge accumulation in the channel region 11 .
在一些实施例中,半导体柱10的数量可以为多个,从而可以增加半导体结构的集成度。在一些实施例中,半导体柱10的材料可以与基底100的材料相同。沟道区11两侧的掺杂区12可以作为晶体管的源极以及漏极,字线101可以作为晶体管的栅极,用于控制源极以及漏极的导通。在一些实施例中,掺杂区12的掺杂离子类型可以与沟道区11的掺杂离子相同,使得形成的晶体管的类型为无结晶体管。在另一些实施例中,掺杂区12的掺杂离子类型与沟道区11的掺杂离子类型不同,使得形成的晶体管的类型为有结晶体管。In some embodiments, the number of semiconductor pillars 10 may be multiple, thereby increasing the integration level of the semiconductor structure. In some embodiments, the material of the semiconductor pillar 10 may be the same as the material of the substrate 100 . The doped regions 12 on both sides of the channel region 11 can serve as the source and drain of the transistor, and the word line 101 can serve as the gate of the transistor for controlling the conduction of the source and drain. In some embodiments, the doping ion type of the doping region 12 may be the same as the doping ions of the channel region 11 , so that the type of transistor formed is a junctionless transistor. In other embodiments, the doping ion type of the doping region 12 is different from the doping ion type of the channel region 11 , so that the type of the formed transistor is a junction transistor.
在一些实施例中,形成导电层以及字线的方法包括:In some embodiments, a method of forming a conductive layer and a word line includes:
参考图6,在基底100上形成至少两个沿远离基底100方向堆叠的初始半导体柱20,如此,可以形成多个堆叠设置的半导体柱,且每一半导体柱均可以用于形成晶体管,提高半导体结构的集成度。Referring to FIG. 6 , at least two initial semiconductor pillars 20 stacked in a direction away from the substrate 100 are formed on the substrate 100 . In this way, multiple stacked semiconductor pillars can be formed, and each semiconductor pillar can be used to form a transistor, thereby improving semiconductor Structural integration.
在一些实施例中,还可以在基底100中形成阵列排布的多个半导体柱10,多个阵列排布的半导体柱10同层设置,且多层阵列排布的半导体柱10可以堆叠设置。基于此,参考图4以及图5,在一些实施例中,可以将基底100分为第一区1以及第二区2,在第一区1与第二区2中分别形成多层堆叠设置的半导体柱10。形成第一区1以及第二区2的方法可以包括:对初始半导体柱20表面进行图形化处理,用于定义第一区1以及第二区2的位置,具体可以在初始半导体柱20顶面形成第一掩膜层21,第一掩膜层21露出需要刻蚀的位置,在一些实施例中,在初始半导体柱20顶部形成盖层22,用于对初始半导体柱20进行保护,盖层22的具体可以是沿远离基底100方向堆叠的氧化硅层和氮化硅层,因此,可以在盖层22表面形成第一掩膜层21,在一些实施例中;对图形化处理的初始半导体柱20进行刻蚀工艺,形成第一区1以及第二区2。值得注意的是,在第一区1与第二区2中形成半导体柱10的工艺方法可以相同,以下将以在第一区1中形成多个半导体柱10为例进行说明。In some embodiments, a plurality of semiconductor pillars 10 arranged in an array can also be formed in the substrate 100 . The semiconductor pillars 10 arranged in a plurality of arrays are arranged in the same layer, and the semiconductor pillars 10 arranged in a multi-layer array can be stacked. Based on this, referring to Figures 4 and 5, in some embodiments, the substrate 100 can be divided into a first area 1 and a second area 2, and a multi-layer stack is formed in the first area 1 and the second area 2 respectively. Semiconductor pillar 10. The method of forming the first area 1 and the second area 2 may include: patterning the surface of the initial semiconductor pillar 20 to define the positions of the first area 1 and the second area 2. Specifically, the method may be on the top surface of the initial semiconductor pillar 20. The first mask layer 21 is formed, and the first mask layer 21 exposes the location that needs to be etched. In some embodiments, a capping layer 22 is formed on top of the initial semiconductor pillar 20 to protect the initial semiconductor pillar 20 . The capping layer Specifically, 22 may be a silicon oxide layer and a silicon nitride layer stacked in a direction away from the substrate 100. Therefore, a first mask layer 21 may be formed on the surface of the cover layer 22. In some embodiments; for the initial semiconductor of the patterning process The pillar 20 undergoes an etching process to form the first region 1 and the second region 2 . It is worth noting that the process method for forming the semiconductor pillars 10 in the first region 1 and the second region 2 may be the same. The following will take the formation of multiple semiconductor pillars 10 in the first region 1 as an example for description.
图7对应于图5中aa’方向的剖面结构示意图;图8对应于图5中bb’方向的剖面结构示意图;图9对应于图5中aa’方向的剖面结构示意图;图10对应于图5中bb’方向的剖面结构示意图。Figure 7 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 8 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5; Figure 9 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 10 corresponds to Figure Schematic diagram of the cross-sectional structure in the bb' direction in 5.
参考图4至图10,形成第一牺牲层23,第一牺牲层23位于相邻的初始半导体柱20之间,且第一牺牲层23至少覆盖沟道区11的初始半导体柱20表面;第一牺牲层23位于沟道区11的初始半导体柱20表面,为后续形成导电层102预留空间,使得在形成字线101的过程中,形成字线101的工艺不会对第一牺牲层23所覆盖的初始半导体柱20表面形成损伤。从而在后续形成的半导体层与沟道区11的半导体柱10表面之间可以形成良好的电接触。Referring to FIGS. 4 to 10 , a first sacrificial layer 23 is formed, the first sacrificial layer 23 is located between adjacent initial semiconductor pillars 20 , and the first sacrificial layer 23 at least covers the surface of the initial semiconductor pillar 20 in the channel region 11 ; A sacrificial layer 23 is located on the surface of the initial semiconductor pillar 20 in the channel region 11 to reserve space for the subsequent formation of the conductive layer 102, so that during the process of forming the word line 101, the process of forming the word line 101 will not damage the first sacrificial layer 23. Damage is formed on the covered surface of the initial semiconductor pillar 20 . Therefore, good electrical contact can be formed between the subsequently formed semiconductor layer and the surface of the semiconductor pillar 10 in the channel region 11 .
在一些实施例中,基底100为硅基底,形成第一牺牲层23的方法包括:
In some embodiments, the substrate 100 is a silicon substrate, and the method of forming the first sacrificial layer 23 includes:
参考图6,形成初始牺牲层24,初始牺牲层24位于相邻的初始半导体柱20之间,初始牺牲层24的材料包括第一锗化硅;由于基底100为硅基底,因此,设置初始牺牲层24的材料包括第一锗化硅,使得初始牺牲层24与基底100具有相同的硅元素,从而硅基底与锗化硅的晶格常数相配。因此,在采用外延工艺在基底100上形成间隔交替的初始半导体柱20以及第一牺牲层23时,可以利用硅基底中的硅来较容易的生长锗化硅,使得制备工艺简单,且形成的第一牺牲层23与初始半导体柱20之间的界限分明,有利于后续完全去除位于初始半导体柱20表面的第一牺牲层23。Referring to FIG. 6 , an initial sacrificial layer 24 is formed. The initial sacrificial layer 24 is located between adjacent initial semiconductor pillars 20 . The material of the initial sacrificial layer 24 includes first silicon germanium. Since the substrate 100 is a silicon substrate, the initial sacrificial layer 24 is provided. The material of layer 24 includes first silicon germanium, so that the initial sacrificial layer 24 and the substrate 100 have the same silicon element, so that the silicon substrate matches the lattice constant of silicon germanium. Therefore, when the epitaxial process is used to form the initial semiconductor pillars 20 and the first sacrificial layer 23 at alternating intervals on the substrate 100, the silicon in the silicon substrate can be used to grow silicon germanium more easily, making the preparation process simple and forming There is a clear boundary between the first sacrificial layer 23 and the initial semiconductor pillar 20 , which facilitates subsequent complete removal of the first sacrificial layer 23 located on the surface of the initial semiconductor pillar 20 .
参考图7至图8,去除部分初始牺牲层24,形成第一凹槽26,第一凹槽26露出初始半导体柱20的部分底面,如此,后续在第一凹槽26中形成的第一牺牲层23可以覆盖初始半导体柱20的底面。在一些实施例中,可以采用刻蚀工艺去除部分初始牺牲层24,由于初始牺牲层24的材料与初始半导体层的材料不同,因此,可以利用刻蚀工艺对初始牺牲层24以及初始半导体层的刻蚀选择比的不同,实现选择性刻蚀。具体地,刻蚀工艺可以是干法刻蚀或者湿法刻蚀中的任一种。仅去除部分初始牺牲层24,使得剩余的部分牺牲层仍然位于相邻的初始半导体柱20之间,起到支撑以及隔离作用。Referring to FIGS. 7 and 8 , part of the initial sacrificial layer 24 is removed to form a first groove 26 . The first groove 26 exposes part of the bottom surface of the initial semiconductor pillar 20 . In this way, the first sacrificial layer subsequently formed in the first groove 26 Layer 23 may cover the bottom surface of initial semiconductor pillar 20 . In some embodiments, an etching process can be used to remove part of the initial sacrificial layer 24 . Since the material of the initial sacrificial layer 24 is different from the material of the initial semiconductor layer, the etching process can be used to remove parts of the initial sacrificial layer 24 and the initial semiconductor layer. Different etching selectivity ratios realize selective etching. Specifically, the etching process may be either dry etching or wet etching. Only part of the initial sacrificial layer 24 is removed, so that the remaining part of the sacrificial layer is still located between adjacent initial semiconductor pillars 20 to play a supporting and isolating role.
参考图7至图9,在第一凹槽26中形成第一牺牲层23,第一牺牲层23的材料与初始牺牲层24的材料不同。考虑到第一牺牲层23用于为后续形成导电层102预留空间,因此,需要第一牺牲层23具有较大的硬度,从而可以防止在后续形成字线101时对第一牺牲层23造成工艺损伤。而由于初始牺牲层24的材料为第一锗化硅,相较于其它材料而言,在硅基底表面形成第一锗化硅更为容易。因此,首先在基底100上形成初始牺牲层24,从而形成初始牺牲层24与初始半导体柱20堆叠设置的结构,初始牺牲层24为后续形成第一牺牲层23预留空间。接着去除初始牺牲层24,并在第一牺牲层23的原有位置形成第一牺牲层23,第一牺牲层23为后续形成导电层102预留空间。如此,使得每一步工序中,形成的半导体结构的质量均较高,从而使得最终形成的半导体结构的良率较高。Referring to FIGS. 7 to 9 , a first sacrificial layer 23 is formed in the first groove 26 , and the material of the first sacrificial layer 23 is different from the material of the initial sacrificial layer 24 . Considering that the first sacrificial layer 23 is used to reserve space for the subsequent formation of the conductive layer 102, the first sacrificial layer 23 needs to have a greater hardness to prevent damage to the first sacrificial layer 23 when the word line 101 is subsequently formed. Process damage. Since the material of the initial sacrificial layer 24 is the first silicon germanium, it is easier to form the first silicon germanium on the surface of the silicon substrate than with other materials. Therefore, an initial sacrificial layer 24 is first formed on the substrate 100 to form a stacked structure of the initial sacrificial layer 24 and the initial semiconductor pillar 20 . The initial sacrificial layer 24 reserves space for the subsequent formation of the first sacrificial layer 23 . Then, the initial sacrificial layer 24 is removed, and the first sacrificial layer 23 is formed at the original position of the first sacrificial layer 23. The first sacrificial layer 23 reserves space for the subsequent formation of the conductive layer 102. In this way, the quality of the semiconductor structure formed in each step of the process is higher, so that the yield rate of the finally formed semiconductor structure is higher.
在一些实施例中,可以采用沉积工艺在第一凹槽26中形成第一牺牲层23,例如可以为热氧化工艺或原子层沉积工艺中的任一种。第一牺牲层23的材料可以为氮化硅。In some embodiments, a deposition process may be used to form the first sacrificial layer 23 in the first groove 26 , for example, it may be any one of a thermal oxidation process or an atomic layer deposition process. The material of the first sacrificial layer 23 may be silicon nitride.
图11对应于图5中aa’方向的剖面结构示意图;图12对应于图5中bb’方向的剖面结构示意图;图13对应于图5中aa’方向的剖面结构示意图;图14对应于图5中bb’方向的剖面结构示意图。Figure 11 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 12 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5; Figure 13 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 14 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5 Schematic diagram of the cross-sectional structure in the bb' direction in 5.
参考图11至图14,在形成第一牺牲层23之后,对第一牺牲层23对应的初始半导体柱20顶面进行刻蚀,形成半导体柱10,并露出半导体柱10的顶面,即对第一牺牲层23对应的初始半导体柱20进行减薄处理,一方面有利于减小半导体柱10的尺寸,另一方面可以为后续在半导体柱10顶面形成字线101预留出足够的空间。Referring to FIGS. 11 to 14 , after the first sacrificial layer 23 is formed, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is etched to form the semiconductor pillar 10 and expose the top surface of the semiconductor pillar 10 , that is, the top surface of the semiconductor pillar 10 is exposed. The initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is thinned. On the one hand, it is beneficial to reduce the size of the semiconductor pillar 10. On the other hand, it can reserve enough space for the subsequent formation of the word line 101 on the top surface of the semiconductor pillar 10. .
由于采用外延工艺在硅基底表面以及初始半导体柱20之间形成初始牺牲层24,而锗原子的原子半径大于硅原子的原子半径,基于应力以及晶格缺陷等原因,导致在硅基底上外延的第一锗化硅层的厚度较小。为了形成较大厚度的初始牺牲层24,需要使得预先形成的初始半导体柱20的厚度较大,从而使得在初始半导体柱20表面外延形成的初始牺牲层24的厚度较大。基于此,后续需要对第一牺牲层23对应的初始半导体柱20顶面进行刻蚀,以使形成的半导体柱10的厚度符合要求。Since the epitaxial process is used to form the initial sacrificial layer 24 between the surface of the silicon substrate and the initial semiconductor pillar 20, and the atomic radius of the germanium atom is larger than the atomic radius of the silicon atom, due to reasons such as stress and lattice defects, the epitaxial layer 24 is formed on the silicon substrate due to reasons such as stress and lattice defects. The thickness of the first silicon germanium layer is smaller. In order to form the initial sacrificial layer 24 with a larger thickness, the thickness of the preformed initial semiconductor pillar 20 needs to be larger, so that the initial sacrificial layer 24 epitaxially formed on the surface of the initial semiconductor pillar 20 has a larger thickness. Based on this, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 needs to be etched subsequently, so that the thickness of the formed semiconductor pillar 10 meets the requirements.
由于第一牺牲层23覆盖沟道区11的初始半导体柱20表面,因此,对第一牺牲层23对应的初始半导体柱20顶面进行刻蚀后,露出的半导体柱10顶面为沟道区11的半导体柱10顶面。如此,后续在对露出的半导体柱10顶面形成字线101时,使得字线101可以与沟道区11的半导体柱10表面电连接。Since the first sacrificial layer 23 covers the surface of the initial semiconductor pillar 20 in the channel area 11, after etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23, the exposed top surface of the semiconductor pillar 10 becomes the channel area. 11 on the top surface of the semiconductor pillar 10 . In this way, when the word line 101 is subsequently formed on the exposed top surface of the semiconductor pillar 10 , the word line 101 can be electrically connected to the surface of the semiconductor pillar 10 in the channel region 11 .
在一些实施例中,对第一牺牲层23对应的初始半导体柱20顶面进行刻蚀的方法包括:
In some embodiments, the method of etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 includes:
参考图6,形成与初始牺牲层24堆叠设置的第二牺牲层25,第二牺牲层25的材料为第二锗化硅,第二锗化硅中的锗含量低于第一锗化硅中的锗含量,且第二牺牲层25与初始半导体柱20顶面相接触;对锗化硅的刻蚀量与锗化硅中的锗含量相关,当锗化硅中的锗含量越高时,对锗化硅的刻蚀越困难,即锗化硅的刻蚀量越小。设置第二锗化硅的锗含量低于第一锗化硅的锗含量,如此,当在刻蚀第一锗化硅时,可以利用第一锗化硅与第二锗化硅的刻蚀选择比,使得刻蚀工艺不会刻蚀与第一锗化硅相邻的第二锗化硅,从而使得形成的第一牺牲层23的形貌符合预期。Referring to FIG. 6 , a second sacrificial layer 25 is formed stacked with the initial sacrificial layer 24 . The material of the second sacrificial layer 25 is second silicon germanium. The germanium content in the second silicon germanium is lower than that in the first silicon germanium. germanium content, and the second sacrificial layer 25 is in contact with the top surface of the initial semiconductor pillar 20; the etching amount of silicon germanium is related to the germanium content in silicon germanium. When the germanium content in silicon germanium is higher, the etching amount of silicon germanium is The more difficult it is to etch silicon germanium, that is, the smaller the etching amount of silicon germanium is. The germanium content of the second silicon germanium is set to be lower than the germanium content of the first silicon germanium. In this way, when etching the first silicon germanium, the etching selection of the first silicon germanium and the second silicon germanium can be utilized. ratio, so that the etching process will not etch the second silicon germanium adjacent to the first silicon germanium, so that the morphology of the formed first sacrificial layer 23 meets expectations.
可以理解的是,在另一些实施例中,第一锗化硅中的锗含量也可以小于第二锗化硅中的锗含量,仅需满足第一锗化硅中的锗含量与第二锗化硅中的锗含量不同即可。It can be understood that in other embodiments, the germanium content in the first silicon germanium may also be less than the germanium content in the second silicon germanium, as long as the germanium content in the first silicon germanium and the second germanium content are satisfied. The content of germanium in the silicon oxide can vary.
参考图7至图10,去除部分初始牺牲层24,以形成第一牺牲层23。Referring to FIGS. 7 to 10 , a portion of the initial sacrificial layer 24 is removed to form a first sacrificial layer 23 .
参考图11至图12,去除部分第二牺牲层25,露出初始半导体柱20的顶面;也就是说,在对初始半导体柱20顶面进行刻蚀之前,首先刻蚀第二牺牲层25,以露出半导体柱10的顶面。相较于不形成第二牺牲层25,直接对第一牺牲层23接触的初始半导体顶面进行刻蚀而言,使得对初始半导体柱20进行刻蚀的工艺更加简单,且刻蚀之后形成的半导体柱10的顶面更加平整,且更加符合预期。这是因为,由于刻蚀第二牺牲层25之后,露出了初始半导体柱20的顶面,使得刻蚀工艺所采用的气体或者溶液可以均匀的与初始半导体柱20的顶面相接触,且刻蚀气体或者液体与半导体柱10顶面的接触面积较大,有利于刻蚀工艺的进行,且使得形成的半导体柱10的顶面形貌较为平整。Referring to Figures 11 and 12, part of the second sacrificial layer 25 is removed to expose the top surface of the initial semiconductor pillar 20; that is, before etching the top surface of the initial semiconductor pillar 20, the second sacrificial layer 25 is first etched, to expose the top surface of the semiconductor pillar 10 . Compared with not forming the second sacrificial layer 25 and directly etching the top surface of the initial semiconductor in contact with the first sacrificial layer 23, the process of etching the initial semiconductor pillar 20 is simpler, and the etching process formed after the etching is The top surface of the semiconductor pillar 10 is smoother and more in line with expectations. This is because after etching the second sacrificial layer 25, the top surface of the initial semiconductor pillar 20 is exposed, so that the gas or solution used in the etching process can evenly contact the top surface of the initial semiconductor pillar 20, and the etching process The contact area between the gas or liquid and the top surface of the semiconductor pillar 10 is large, which is beneficial to the etching process and makes the top surface of the formed semiconductor pillar 10 relatively smooth.
参考图13至图14,对初始半导体柱20顶面进行刻蚀,形成半导体柱10。Referring to FIGS. 13 and 14 , the top surface of the initial semiconductor pillar 20 is etched to form the semiconductor pillar 10 .
参考图15至图32,在露出半导体柱10的顶面后,在沟道区11的半导体柱10顶面形成字线101,形成的字线101还可以覆盖至少部分与半导体柱10顶面相接的两侧侧面,使得字线101环绕沟道区11的半导体柱10的至少部分侧面,剩余部分沟道区11的半导体柱10侧面可以用于与地端电连接,从而使得沟道区11中堆积的电荷可以被泄放至地端。Referring to FIGS. 15 to 32 , after the top surface of the semiconductor pillar 10 is exposed, a word line 101 is formed on the top surface of the semiconductor pillar 10 in the channel region 11 . The formed word line 101 can also cover at least part of the top surface of the semiconductor pillar 10 . Both sides of the connection are connected, so that the word line 101 surrounds at least part of the side surfaces of the semiconductor pillar 10 of the channel area 11 , and the remaining part of the side surface of the semiconductor pillar 10 of the channel area 11 can be used to be electrically connected to the ground terminal, so that the channel area 11 The charge accumulated in can be discharged to the ground.
在一些实施例中,基底100表面设置有多个阵列排布的半导体柱10,且多个半导体柱10同层设置,字线101包覆沿第一方向X排列的一行半导体柱10中的每一沟道区11的部分半导体柱10侧面,形成字线101的方法包括:In some embodiments, the surface of the substrate 100 is provided with a plurality of semiconductor pillars 10 arranged in an array, and the plurality of semiconductor pillars 10 are arranged on the same layer. The word line 101 covers each semiconductor pillar 10 in a row arranged along the first direction X. A method of forming the word line 101 on the side of a portion of the semiconductor pillar 10 in the channel region 11 includes:
图16对应于图15中aa’方向的剖面结构示意图;图17对应于图15中bb’方向的剖面结构示意图;图19对应于图18中aa’方向的剖面结构示意图;图20对应于图18中aa’方向的剖面结构示意图;图22对应于图5中aa’方向的剖面结构示意图。Figure 16 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 15; Figure 17 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 15; Figure 19 corresponds to the schematic cross-sectional structure diagram in the aa' direction in Figure 18; Figure 20 corresponds to Figure The schematic cross-sectional structural diagram in the aa' direction in Figure 18; Figure 22 corresponds to the cross-sectional structural diagram in the aa' direction in Figure 5.
参考图15至图22,形成隔离结构29,隔离结构29位于沿第一方向X相邻的半导体柱10之间,并覆盖沟道区11半导体柱10侧面。隔离结构29用于对相邻的半导体柱10进行隔离,使得沿第一方向X相邻的半导体柱10之间不会产生电接触。Referring to FIGS. 15 to 22 , an isolation structure 29 is formed. The isolation structure 29 is located between adjacent semiconductor pillars 10 along the first direction X and covers the side surfaces of the semiconductor pillars 10 in the channel region 11 . The isolation structure 29 is used to isolate adjacent semiconductor pillars 10 so that no electrical contact occurs between adjacent semiconductor pillars 10 along the first direction X.
具体地,形成隔离结构29的方法可以包括:Specifically, the method of forming the isolation structure 29 may include:
参考图15至图17,在每一半导体柱10顶面形成第二介质层27,第二介质层27填满半导体柱10与第一牺牲层23之间的空隙,用于为后续形成字线101预留空间。第二介质层27可以防止后续沉积隔离结构29的材料以形成隔离结构29时,在半导体柱10顶面与第一牺牲层23之间也同时形成隔离结构29。具体地,在一些实施例中,可以采用沉积工艺形成第二介质层27,当第一牺牲层23的材料为氮化硅时,第二介质层27的材料可以为低k介质材料。低k介质材料与氮化硅材料之间具有较大的刻蚀选择比,如
此,在后续需要去除第二介质层27,以形成字线101时,可以利用刻蚀选择比,仅去除第二介质层27,而保留第一牺牲层23。Referring to FIGS. 15 to 17 , a second dielectric layer 27 is formed on the top surface of each semiconductor pillar 10 . The second dielectric layer 27 fills the gap between the semiconductor pillar 10 and the first sacrificial layer 23 for subsequent formation of word lines. 101 reserved space. The second dielectric layer 27 can prevent the isolation structure 29 from being simultaneously formed between the top surface of the semiconductor pillar 10 and the first sacrificial layer 23 when the material of the isolation structure 29 is subsequently deposited to form the isolation structure 29 . Specifically, in some embodiments, a deposition process may be used to form the second dielectric layer 27. When the material of the first sacrificial layer 23 is silicon nitride, the material of the second dielectric layer 27 may be a low-k dielectric material. There is a large etching selectivity ratio between low-k dielectric materials and silicon nitride materials, such as Therefore, when the second dielectric layer 27 needs to be removed later to form the word line 101, the etching selectivity can be used to remove only the second dielectric layer 27 while retaining the first sacrificial layer 23.
参考图18至图19,对顶层的半导体柱10顶面进行图形化处理,用于定义出阵列排布的半导体柱10的位置,具体可以顶层的半导体柱10顶面形成第二掩膜层28,第二掩膜层28露出需要刻蚀的半导体柱10顶面。具体地,在一些实施例中,在形成第二掩膜层28之前,可以先去除盖层22中的氮化硅层,仅保留氧化硅层,如此,有利于进行刻蚀工艺。在去除氮化硅层之后,在氧化硅层表面形成第二掩膜层28。Referring to Figures 18 and 19, the top surface of the top semiconductor pillar 10 is patterned to define the position of the semiconductor pillar 10 arranged in an array. Specifically, a second mask layer 28 can be formed on the top surface of the top semiconductor pillar 10. , the second mask layer 28 exposes the top surface of the semiconductor pillar 10 that needs to be etched. Specifically, in some embodiments, before forming the second mask layer 28 , the silicon nitride layer in the cap layer 22 may be removed first, leaving only the silicon oxide layer, which is beneficial to the etching process. After removing the silicon nitride layer, a second mask layer 28 is formed on the surface of the silicon oxide layer.
参考图20,对图形化的半导体柱10顶面进行刻蚀工艺,以形成阵列排布的半导体柱10,其中,多个半导体柱10沿第一方向X间隔排布,且相邻的半导体柱10之间具有空隙。Referring to FIG. 20 , an etching process is performed on the top surface of the patterned semiconductor pillars 10 to form semiconductor pillars 10 arranged in an array, wherein a plurality of semiconductor pillars 10 are arranged at intervals along the first direction X, and adjacent semiconductor pillars There is a gap between 10.
参考图21至图22,采用沉积工艺在相邻的半导体柱10之间沉积隔离材料,以形成隔离结构29,隔离结构29填满相邻的半导体柱10之间的间隙,且包覆每一半导体柱10的侧面。具体地,在一些实施例中,隔离结构29的材料可以为氧化硅。Referring to FIGS. 21 and 22 , a deposition process is used to deposit an isolation material between adjacent semiconductor pillars 10 to form an isolation structure 29 . The isolation structure 29 fills the gap between adjacent semiconductor pillars 10 and covers each The side surface of the semiconductor pillar 10 . Specifically, in some embodiments, the material of the isolation structure 29 may be silicon oxide.
图24对应于图23中aa’方向的剖面结构示意图;图25对应于图23中bb’方向的剖面结构示意图。Figure 24 corresponds to the schematic cross-sectional structural diagram in the direction aa’ in Figure 23; Figure 25 corresponds to the schematic cross-sectional structural diagram in the direction bb’ in Figure 23.
形成隔离结构29之后,参考图23至图25,去除第二介质层27,露出半导体柱10顶面以及第一牺牲层23底面,如此,可以在露出的半导体柱10顶面形成字线101。After the isolation structure 29 is formed, refer to FIGS. 23 to 25 to remove the second dielectric layer 27 to expose the top surface of the semiconductor pillar 10 and the bottom surface of the first sacrificial layer 23 . In this way, the word line 101 can be formed on the exposed top surface of the semiconductor pillar 10 .
图27对应于图26中aa’方向的剖面结构示意图;图28对应于图26中bb’方向的剖面结构示意图。Figure 27 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26; Figure 28 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.
参考图26至图28,在沟道区11的半导体柱10的顶面以及部分侧面形成字线101。具体地,在形成字线101之前,对相邻的半导体柱10之间的隔离结构29顶面进行刻蚀,直至隔离结构29具有预设厚度,从而使得相邻的半导体柱10之间存在间隙,且仅刻蚀部分位于相邻的半导体柱10之间的隔离结构29,使得位于半导体柱10之间的剩余部分隔离结构29仍可以起到隔离作用。如此,当在半导体柱10顶面沉积字线101材料以形成字线101时,还可以在半导体柱10的侧面形成字线101,使得字线101可以包覆半导体柱10的顶面以及与顶面相接的部分侧面。Referring to FIGS. 26 to 28 , word lines 101 are formed on the top surface and part of the side surfaces of the semiconductor pillar 10 in the channel region 11 . Specifically, before forming the word line 101 , the top surface of the isolation structure 29 between adjacent semiconductor pillars 10 is etched until the isolation structure 29 has a preset thickness, so that there is a gap between adjacent semiconductor pillars 10 , and only a portion of the isolation structure 29 located between adjacent semiconductor pillars 10 is etched, so that the remaining portion of the isolation structure 29 located between the semiconductor pillars 10 can still play an isolation role. In this way, when the word line 101 material is deposited on the top surface of the semiconductor pillar 10 to form the word line 101, the word line 101 can also be formed on the side of the semiconductor pillar 10, so that the word line 101 can cover the top surface of the semiconductor pillar 10 and connect with the top surface. Part of the side where the faces meet.
在一些实施例中,当隔离结构29的材料为氧化硅时,在刻蚀相邻的半导体柱10之间的隔离结构29的步骤中,可以保留位于半导体柱10侧面的部分隔离结构29,从而使得位于半导体柱10侧面的隔离结构29可以作为栅介质层106。In some embodiments, when the material of the isolation structure 29 is silicon oxide, in the step of etching the isolation structure 29 between adjacent semiconductor pillars 10, part of the isolation structure 29 located on the side of the semiconductor pillar 10 can be retained, so that Therefore, the isolation structure 29 located on the side of the semiconductor pillar 10 can serve as the gate dielectric layer 106 .
在一些实施例中,形成字线101的方法包括:在露出的半导体柱10顶面形成栅介质层106,且栅介质层106与位于半导体柱10侧面的隔离结构29相接,在一些实施例中,就可以采用沉积工艺在半导体柱10顶面形成栅介质层106,栅介质层106的材料可以为氧化硅。In some embodiments, the method of forming the word line 101 includes: forming a gate dielectric layer 106 on the top surface of the exposed semiconductor pillar 10, and the gate dielectric layer 106 is connected to the isolation structure 29 located on the side of the semiconductor pillar 10. In some embodiments, , a deposition process can be used to form the gate dielectric layer 106 on the top surface of the semiconductor pillar 10 , and the material of the gate dielectric layer 106 can be silicon oxide.
采用沉积工艺在栅介质层106表面形成阻挡层107,在一些实施例中,阻挡层107的材料可以为氮化硅。A deposition process is used to form a barrier layer 107 on the surface of the gate dielectric layer 106. In some embodiments, the material of the barrier layer 107 may be silicon nitride.
采用沉积工艺在栅介质层106表面形成字线101,字线101的材料可以为钨、钼、钛、钴或者钌中的至少一者。A deposition process is used to form a word line 101 on the surface of the gate dielectric layer 106. The material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt or ruthenium.
可以理解的是,由于去除第二介质层27之后,露出了第一牺牲层23以及半导体柱10的顶面,因此,在采用沉积工艺在半导体柱10顶面形成栅介质层106以及字线101时,同时也会在第一牺牲层23
底面形成第一栅介质层32以及第一字线31。为了后续容易去除位于第一牺牲层23底面的第一栅介质层32以及第一字线31,当位于半导体柱10顶面的字线101厚度符合预期时,停止沉积工艺,并在半导体柱10顶面的字线101与第一牺牲层23底面的第一字线31之间形成初始介质层30,用于隔离半导体柱10顶面的字线101与第一牺牲层23底面的第一字线31。如此,当后续在去除第一牺牲层23底面的第一栅介质层32以及第一字线31时,由于初始介质层30的存在,可以对位于半导体柱10顶面的字线101以及第一牺牲层23起到保护作用。It can be understood that after the second dielectric layer 27 is removed, the first sacrificial layer 23 and the top surface of the semiconductor pillar 10 are exposed. Therefore, the gate dielectric layer 106 and the word line 101 are formed on the top surface of the semiconductor pillar 10 using a deposition process. at the same time, the first sacrificial layer 23 will also A first gate dielectric layer 32 and a first word line 31 are formed on the bottom surface. In order to easily remove the first gate dielectric layer 32 and the first word line 31 located on the bottom surface of the first sacrificial layer 23 later, when the thickness of the word line 101 located on the top surface of the semiconductor pillar 10 is as expected, the deposition process is stopped, and the semiconductor pillar 10 is An initial dielectric layer 30 is formed between the word line 101 on the top surface and the first word line 31 on the bottom surface of the first sacrificial layer 23 for isolating the word line 101 on the top surface of the semiconductor pillar 10 and the first word line 31 on the bottom surface of the first sacrificial layer 23 Line 31. In this way, when the first gate dielectric layer 32 and the first word line 31 on the bottom surface of the first sacrificial layer 23 are subsequently removed, due to the existence of the initial dielectric layer 30, the word line 101 and the first word line 101 on the top surface of the semiconductor pillar 10 can be removed. The sacrificial layer 23 plays a protective role.
图29对应于图26中aa’方向的剖面结构示意图;图30对应于图26中bb’方向的剖面结构示意图。Figure 29 corresponds to the schematic cross-sectional structural diagram in the direction aa' in Figure 26; Figure 30 corresponds to the schematic cross-sectional structural diagram in the bb' direction in Figure 26.
参考图29至图30,在形成字线101之后,去除第一牺牲层23,露出部分半导体柱10底面;露出的半导体柱10底面可以用于形成导电层102,从而使得导电层102与部分沟道区11的半导体柱10表面形成电连接,且导电层102用于接地,使得沟道区11中堆积的电荷可以经由导电层102泄放至地端。Referring to Figures 29 and 30, after forming the word line 101, the first sacrificial layer 23 is removed to expose part of the bottom surface of the semiconductor pillar 10; the exposed bottom surface of the semiconductor pillar 10 can be used to form the conductive layer 102, so that the conductive layer 102 is connected to part of the trench. The surface of the semiconductor pillar 10 in the channel region 11 is electrically connected, and the conductive layer 102 is used for grounding, so that the charges accumulated in the channel region 11 can be discharged to the ground via the conductive layer 102 .
图31对应于图26中aa’方向的剖面结构示意图;图32对应于图26中bb’方向的剖面结构示意图。Figure 31 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26; Figure 32 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.
参考图31至图32,在沟道区11的半导体柱10底面形成导电层102,且位于一半导体柱10底面的导电层102与位于相邻的半导体柱10顶面的字线101在垂直于基底的方向上相邻。由于多个半导体柱10堆叠设置,且导电层102位于半导体柱10的底面,字线101位于半导体柱10的顶面,使得相邻的两个半导体柱10之间,一半导体柱10的导电层102与另一半导体柱10的字线101相邻。Referring to FIGS. 31 to 32 , a conductive layer 102 is formed on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and the conductive layer 102 on the bottom surface of one semiconductor pillar 10 and the word line 101 on the top surface of the adjacent semiconductor pillar 10 are in a vertical position. adjacent in the direction of the base. Since multiple semiconductor pillars 10 are stacked and the conductive layer 102 is located on the bottom surface of the semiconductor pillar 10 and the word line 101 is located on the top surface of the semiconductor pillar 10, there is a conductive layer of one semiconductor pillar 10 between two adjacent semiconductor pillars 10. 102 is adjacent to the word line 101 of another semiconductor pillar 10 .
为了防止相邻的字线101与导电层102形成电接触,在一些实施例中,还包括:形成第一介质层104,第一介质层104位于在垂直于基底方向上相邻的字线101与导电层102之间。第一介质层104的材料可以与初始介质层30的材料相同,这是因为,初始介质层30位于相邻的半导体柱10之间,因此,无需去除前述步骤中形成的初始介质层30,有利于节省工艺步骤以及节约形成第一介质层104的材料。具体地,在一些实施例中,第一介质层104的材料可以为低k介质材料。在另一些实施例中,第一介质层104的材料还可以为氮化物中的一种,例如可以为氮化硅。In order to prevent adjacent word lines 101 from forming electrical contact with the conductive layer 102, in some embodiments, it also includes: forming a first dielectric layer 104. The first dielectric layer 104 is located on the adjacent word lines 101 in a direction perpendicular to the substrate. and the conductive layer 102. The material of the first dielectric layer 104 may be the same as the material of the initial dielectric layer 30 . This is because the initial dielectric layer 30 is located between adjacent semiconductor pillars 10 . Therefore, there is no need to remove the initial dielectric layer 30 formed in the previous steps. This is beneficial to saving process steps and saving materials for forming the first dielectric layer 104 . Specifically, in some embodiments, the material of the first dielectric layer 104 may be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.
在一些实施例中,在形成导电层102之前,可以去除位于第一牺牲层23底面的第一字线31以及第一栅介质层32,并保留初始介质层30。如此,可以防止由于在第一牺牲层23底面的栅介质层106表面形成导电层102,后续再去除第一牺牲层23底面的栅介质层106以及字线101时,可能导致导电层102产生工艺损伤的问题。In some embodiments, before forming the conductive layer 102 , the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23 may be removed, and the initial dielectric layer 30 may be retained. In this way, it is possible to prevent the formation of the conductive layer 102 on the surface of the gate dielectric layer 106 on the bottom surface of the first sacrificial layer 23, and subsequent removal of the gate dielectric layer 106 and the word line 101 on the bottom surface of the first sacrificial layer 23, which may cause the conductive layer 102 to be produced. Injury issues.
在一些实施例中,在去除位于第一牺牲层23底面的第一字线31以及第一栅介质层32之后,可以在初始介质层30顶面沉积第一介质层104的材料,从而与初始介质层30一起构成第一介质层104。In some embodiments, after removing the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23, the material of the first dielectric layer 104 can be deposited on the top surface of the initial dielectric layer 30, so as to be consistent with the initial dielectric layer 30. The dielectric layers 30 together form the first dielectric layer 104 .
在一些实施例中,可以采用沉积工艺在沟道区11的半导体柱10底面形成导电层102,且由于初始介质层30的存在,使得形成的导电层102不会与另一半导体柱10顶面的字线101形成电接触。在一些实施例中,导电层102的材料可以为多晶硅或者掺杂硅、掺杂锗、氮化钛、氮化钽、钨、钛、钽、铜、铝、银、金、硅化钨、硅化钴、硅化钛中的至少一者。In some embodiments, a deposition process can be used to form the conductive layer 102 on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and due to the existence of the initial dielectric layer 30 , the formed conductive layer 102 will not interact with the top surface of another semiconductor pillar 10 The word lines 101 form electrical contacts. In some embodiments, the material of the conductive layer 102 may be polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide.
上述实施例提供的半导体结构的制备方法中,形成的字线101包覆沟道区11的部分半导体柱10侧面,并露出沟道区11的剩余部分半导体柱10侧面,使得位于沟道区11的半导体柱10侧面的字线101可以用于控制沟道的导通,露出的沟道区11的半导体柱10侧面可以用于接地;形成的导电层102与露出
的沟道区11的半导体柱10侧面电连接,且导电层102用于与地端电连接,使得沟道区11中堆积的电荷可以通过导电层102泄放至地端,从而防止浮体效应的产生。In the preparation method of the semiconductor structure provided in the above embodiment, the formed word line 101 covers part of the side surfaces of the semiconductor pillars 10 of the channel area 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 of the channel area 11 , so that the word line 101 is located in the channel area 11 The word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel, and the side of the semiconductor pillar 10 of the exposed channel region 11 can be used for grounding; the formed conductive layer 102 is connected with the exposed The side surfaces of the semiconductor pillars 10 of the channel region 11 are electrically connected, and the conductive layer 102 is used to electrically connect with the ground terminal, so that the charges accumulated in the channel region 11 can be discharged to the ground terminal through the conductive layer 102, thereby preventing the floating body effect. produce.
本领域的普通技术人员可以理解,上述各实施方式是实现本公开的具体实施例,而在实际应用中,可以在形式上和细节上对其作各种改变,而不偏离本公开的精神和范围。任何本领域技术人员,在不脱离本公开的精神和范围内,均可作各自更动与修改,因此本公开的保护范围应当以权利要求限定的范围为准。
Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.
Claims (15)
- 一种半导体结构,包括:A semiconductor structure including:基底(100);base(100);位于所述基底(100)上的半导体柱(10),所述半导体柱(10)具有沟道区(11)以及位于所述沟道区(11)相对两侧的掺杂区(12);A semiconductor pillar (10) located on the substrate (100), the semiconductor pillar (10) having a channel region (11) and doping regions (12) located on opposite sides of the channel region (11);字线(101),所述字线(101)包覆所述沟道区(11)的部分半导体柱(10)侧面,并露出所述沟道区(11)的剩余部分半导体柱(10)侧面;Word line (101), the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of the channel area (11), and exposes the remaining part of the semiconductor pillars (10) of the channel area (11) side;导电层(102),所述导电层(102)与露出的所述沟道区(11)的半导体柱(10)的至少部分侧面电连接,且所述导电层(102)用于与地端电连接。Conductive layer (102), the conductive layer (102) is electrically connected to at least part of the side surfaces of the exposed semiconductor pillar (10) of the channel region (11), and the conductive layer (102) is used to connect to the ground terminal. Electrical connection.
- 根据权利要求1所述的半导体结构,其中,在垂直于所述掺杂区(12)指向所述沟道区(11)的方向上,所述半导体柱(10)的截面形状为矩形,所述字线(101)露出所述半导体柱(10)的其中一个侧面。The semiconductor structure according to claim 1, wherein the cross-sectional shape of the semiconductor pillar (10) is rectangular in a direction perpendicular to the doping region (12) and directed to the channel region (11), so The word line (101) exposes one side of the semiconductor pillar (10).
- 根据权利要求1所述的半导体结构,其中,所述半导体柱(10)平行于所述基底(100)表面,所述字线(101)平行于所述基底(100)表面,且所述导电层(102)与所述字线(101)相对设置,还包括:导电柱(103),所述导电柱(103)垂直于所述基底(100)表面,所述导电柱(103)与所述导电层(102)电连接,且所述导电柱(103)用于接地。The semiconductor structure according to claim 1, wherein the semiconductor pillar (10) is parallel to the surface of the substrate (100), the word line (101) is parallel to the surface of the substrate (100), and the conductive The layer (102) is arranged opposite to the word line (101), and further includes: a conductive pillar (103), the conductive pillar (103) is perpendicular to the surface of the substrate (100), and the conductive pillar (103) is connected to the The conductive layer (102) is electrically connected, and the conductive pillar (103) is used for grounding.
- 根据权利要求3所述的半导体结构,其中,所述导电层(102)的材料与所述导电柱(103)的材料相同。The semiconductor structure of claim 3, wherein the conductive layer (102) is made of the same material as the conductive pillar (103).
- 根据权利要求1或4所述的半导体结构,其中,所述导电层(102)的材料包括:多晶硅或者掺杂硅、掺杂锗、氮化钛、氮化钽、钨、钛、钽、铜、铝、银、金、硅化钨、硅化钴、硅化钛中的至少一者。The semiconductor structure according to claim 1 or 4, wherein the material of the conductive layer (102) includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper , at least one of aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide.
- 根据权利要求1所述的半导体结构,其中,所述基底(100)表面设置有多个沿远离所述基底(100)方向堆叠的半导体柱(10)以及多条字线(101),其中,所述字线(101)包覆所述半导体柱(10)中的所述沟道区(11)的部分半导体柱(10)侧面,且所述半导体柱(10)中,露出的所述沟道区(11)的半导体柱(10)的至少部分侧面与所述导电层(102)电连接。The semiconductor structure according to claim 1, wherein the surface of the substrate (100) is provided with a plurality of semiconductor pillars (10) stacked in a direction away from the substrate (100) and a plurality of word lines (101), wherein, The word line (101) covers part of the side surfaces of the semiconductor pillar (10) of the channel region (11) in the semiconductor pillar (10), and in the semiconductor pillar (10), the exposed trench At least part of the side surfaces of the semiconductor pillars (10) of the track region (11) are electrically connected to the conductive layer (102).
- 根据权利要求6所述的半导体结构,其中,所述半导体结构还包括导电柱(103),所述导电柱(103)与多个所述导电层(102)电连接,且所述导电柱(103)用于与地端电连接。The semiconductor structure according to claim 6, wherein the semiconductor structure further includes a conductive pillar (103), the conductive pillar (103) is electrically connected to a plurality of the conductive layers (102), and the conductive pillar (103) 103) is used for electrical connection with the ground.
- 根据权利要求6所述的半导体结构,其中,还包括:位线(105),所述位线(105)与所述掺杂区(12)的半导体柱(10)端部电连接。The semiconductor structure according to claim 6, further comprising: a bit line (105), the bit line (105) being electrically connected to an end of the semiconductor pillar (10) of the doped region (12).
- 一种半导体结构的制备方法,包括:A method for preparing a semiconductor structure, including:提供基底(100);provideBase(100);在所述基底(100)上形成半导体柱(10),所述半导体柱(10)具有沟道区(11)以及位于所述沟道区(11)相对两侧的掺杂区(12);Forming a semiconductor pillar (10) on the substrate (100), the semiconductor pillar (10) having a channel region (11) and doped regions (12) located on opposite sides of the channel region (11);形成字线(101),所述字线(101)包覆所述沟道区(11)的部分半导体柱(10)侧面,并露出所述沟道区(11)的剩余部分半导体柱(10)侧面; Forming a word line (101), the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of the channel area (11), and exposes the remaining part of the semiconductor pillars (10) of the channel area (11). )side;形成导电层(102),所述导电层(102)与露出的所述沟道区(11)的半导体柱(10)的至少部分侧面电连接,且所述导电层(102)用于与地端电连接。A conductive layer (102) is formed, the conductive layer (102) is electrically connected to at least part of the side surfaces of the exposed semiconductor pillar (10) of the channel region (11), and the conductive layer (102) is used to connect to ground. terminal electrical connection.
- 根据权利要求9所述的半导体结构的制备方法,其中,形成所述导电层(102)以及所述字线(101)的方法包括:The method of preparing a semiconductor structure according to claim 9, wherein the method of forming the conductive layer (102) and the word line (101) includes:在所述基底(100)上形成至少两个沿远离所述基底(100)方向堆叠的初始半导体柱(20);forming at least two initial semiconductor pillars (20) stacked in a direction away from the substrate (100) on the substrate (100);形成第一牺牲层(23),所述第一牺牲层(23)位于相邻的所述初始半导体柱(20)之间,且所述第一牺牲层(23)至少覆盖所述沟道区(11)的初始半导体柱(20)表面;A first sacrificial layer (23) is formed, the first sacrificial layer (23) is located between the adjacent initial semiconductor pillars (20), and the first sacrificial layer (23) at least covers the channel region The surface of the initial semiconductor pillar (20) of (11);对所述第一牺牲层(23)对应的所述初始半导体柱(20)顶面进行刻蚀,形成半导体柱(10),并露出所述半导体柱(10)的顶面;Etch the top surface of the initial semiconductor pillar (20) corresponding to the first sacrificial layer (23) to form a semiconductor pillar (10), and expose the top surface of the semiconductor pillar (10);在所述沟道区(11)的半导体柱(10)顶面形成字线(101);A word line (101) is formed on the top surface of the semiconductor pillar (10) in the channel region (11);去除所述第一牺牲层(23),露出部分所述半导体柱(10)底面;Remove the first sacrificial layer (23) to expose part of the bottom surface of the semiconductor pillar (10);在所述沟道区(11)的半导体柱(10)底面形成所述导电层(102),且位于一所述半导体柱(10)底面的所述导电层(102)与位于相邻的所述半导体柱(10)顶面的所述字线(101)在垂直于所述基底(100)的方向上相邻。The conductive layer (102) is formed on the bottom surface of the semiconductor pillar (10) in the channel region (11), and the conductive layer (102) located on the bottom surface of one of the semiconductor pillars (10) is connected to all adjacent ones. The word lines (101) on the top surface of the semiconductor pillar (10) are adjacent in a direction perpendicular to the substrate (100).
- 根据权利要求10所述的半导体结构的制备方法,其中,所述基底(100)为硅基底,形成所述第一牺牲层(23)的方法包括:The method of preparing a semiconductor structure according to claim 10, wherein the substrate (100) is a silicon substrate, and the method of forming the first sacrificial layer (23) includes:形成初始牺牲层(24),所述初始牺牲层(24)位于相邻的所述初始半导体柱(20)之间,所述初始牺牲层(24)的材料包括第一锗化硅;Form an initial sacrificial layer (24), the initial sacrificial layer (24) is located between the adjacent initial semiconductor pillars (20), the material of the initial sacrificial layer (24) includes first silicon germanium;去除部分所述初始牺牲层(24),形成第一凹槽(26),所述第一凹槽(26)露出所述初始半导体柱(20)的部分底面;Remove part of the initial sacrificial layer (24) to form a first groove (26), and the first groove (26) exposes part of the bottom surface of the initial semiconductor pillar (20);在所述第一凹槽(26)中形成所述第一牺牲层(23),所述第一牺牲层(23)的材料与所述初始牺牲层(24)的材料不同。The first sacrificial layer (23) is formed in the first groove (26), and the material of the first sacrificial layer (23) is different from the material of the initial sacrificial layer (24).
- 根据权利要求11所述的半导体结构的制备方法,其中,所述对所述第一牺牲层(23)对应的所述初始半导体柱(20)顶面进行刻蚀的方法包括:The method of preparing a semiconductor structure according to claim 11, wherein the method of etching the top surface of the initial semiconductor pillar (20) corresponding to the first sacrificial layer (23) includes:形成与所述初始牺牲层(24)堆叠设置的第二牺牲层(25),所述第二牺牲层(25)的材料为第二锗化硅,所述第二锗化硅中的锗含量低于所述第一锗化硅中的锗含量,且所述第二牺牲层(25)与所述初始半导体柱(20)顶面相接触;Forming a second sacrificial layer (25) stacked with the initial sacrificial layer (24), the material of the second sacrificial layer (25) is second silicon germanium, and the germanium content in the second silicon germanium Lower than the germanium content in the first silicon germanium, and the second sacrificial layer (25) is in contact with the top surface of the initial semiconductor pillar (20);去除部分所述初始牺牲层(24),以形成所述第一牺牲层(23);Remove part of the initial sacrificial layer (24) to form the first sacrificial layer (23);去除部分所述第二牺牲层(25),露出所述初始半导体柱(20)的顶面;Remove part of the second sacrificial layer (25) to expose the top surface of the initial semiconductor pillar (20);对所述初始半导体柱(20)顶面进行刻蚀,形成所述半导体柱(10)。The top surface of the initial semiconductor pillar (20) is etched to form the semiconductor pillar (10).
- 根据权利要求10所述的半导体结构的制备方法,其中,还包括:形成第一介质层(104),所述第一介质层(104)位于在垂直于所述基底(100)方向上相邻的所述字线(101)与所述导电层(102)之间。The method for preparing a semiconductor structure according to claim 10, further comprising: forming a first dielectric layer (104), the first dielectric layer (104) being adjacent in a direction perpendicular to the substrate (100) between the word line (101) and the conductive layer (102).
- 根据权利要求13所述的半导体结构的制备方法,其中,所述第一介质层(104)的材料包括:低k介 质材料。The method of preparing a semiconductor structure according to claim 13, wherein the material of the first dielectric layer (104) includes: low-k dielectric quality materials.
- 根据权利要求10所述的半导体结构的制备方法,其中,所述基底(100)表面设置有多个阵列排布的所述半导体柱(10),且多个所述半导体柱(10)同层设置,所述字线(101)包覆沿第一方向(X)排列的一行半导体柱(10)中的每一沟道区(11)的部分半导体柱(10)侧面,形成所述字线(101)的方法包括:The method for preparing a semiconductor structure according to claim 10, wherein a plurality of the semiconductor pillars (10) arranged in an array are provided on the surface of the substrate (100), and the plurality of semiconductor pillars (10) are in the same layer. It is configured that the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of each channel region (11) in a row of semiconductor pillars (10) arranged along the first direction (X) to form the word line (101) methods include:形成隔离结构(29),所述隔离结构(29)位于沿所述第一方向(X)相邻的所述半导体柱(10)之间,并覆盖所述沟道区(11)半导体柱(10)侧面;An isolation structure (29) is formed, the isolation structure (29) is located between the adjacent semiconductor pillars (10) along the first direction (X), and covers the channel region (11) semiconductor pillar ( 10) Side;对相邻的所述半导体柱(10)之间的隔离结构(29)顶面进行刻蚀,直至所述隔离结构(29)具有预设厚度;Etch the top surface of the isolation structure (29) between adjacent semiconductor pillars (10) until the isolation structure (29) has a preset thickness;在所述沟道区(11)的所述半导体柱(10)顶面以及部分侧面形成字线(101)。 A word line (101) is formed on the top surface and part of the side surface of the semiconductor pillar (10) of the channel region (11).
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CN115101523A (en) * | 2022-07-12 | 2022-09-23 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (5)
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US20040259312A1 (en) * | 2001-05-29 | 2004-12-23 | Till Schlosser | DRAM cell arrangement with vertical MOS transistors, and method for its fabrication |
US20050088895A1 (en) * | 2003-07-25 | 2005-04-28 | Infineon Technologies Ag | DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM |
US20130043525A1 (en) * | 2011-08-19 | 2013-02-21 | Samsung Electronics Co., Ltd. | Semiconductor devices including a vertical channel transistor and methods of fabricating the same |
CN106158756A (en) * | 2014-10-10 | 2016-11-23 | 爱思开海力士有限公司 | Vertical channel semiconductor devices |
CN115101523A (en) * | 2022-07-12 | 2022-09-23 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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2022
- 2022-07-12 CN CN202210819899.4A patent/CN115101523A/en active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040259312A1 (en) * | 2001-05-29 | 2004-12-23 | Till Schlosser | DRAM cell arrangement with vertical MOS transistors, and method for its fabrication |
US20050088895A1 (en) * | 2003-07-25 | 2005-04-28 | Infineon Technologies Ag | DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM |
US20130043525A1 (en) * | 2011-08-19 | 2013-02-21 | Samsung Electronics Co., Ltd. | Semiconductor devices including a vertical channel transistor and methods of fabricating the same |
CN106158756A (en) * | 2014-10-10 | 2016-11-23 | 爱思开海力士有限公司 | Vertical channel semiconductor devices |
CN115101523A (en) * | 2022-07-12 | 2022-09-23 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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