WO2024012085A1

WO2024012085A1 - Semiconductor structure and preparation method for semiconductor structure

Info

Publication number: WO2024012085A1
Application number: PCT/CN2023/097833
Authority: WO
Inventors: 李晓杰
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-07-12
Filing date: 2023-06-01
Publication date: 2024-01-18
Also published as: CN115101523A

Abstract

Disclosed in the embodiments of the present disclosure are a semiconductor structure and a preparation method for a semiconductor structure. The semiconductor structure comprises: a substrate; semiconductor columns, which are located on the substrate, wherein each semiconductor column is provided with a channel region and doped regions located on two opposite sides of the channel region; word lines, which cover some side faces in channel regions of the semiconductor columns and expose the remaining side faces in the channel regions of the semiconductor columns; and a conductive layer, which is electrically connected to at least some of the exposed side faces in the channel regions of the semiconductor columns, and is used for electrically connecting to a grounding end.

Description

Semiconductor structure and preparation method of semiconductor structure

cross reference

This disclosure claims priority from the Chinese patent application titled "Semiconductor Structure and Preparation Method of Semiconductor Structure" and application number 202210819899.4, filed on July 12, 2022, which is fully incorporated by reference into this disclosure.

Technical field

Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background technique

In field effect transistors, the floating body effect is usually prone to occur. The floating body effect means that due to the accumulation of holes in the channel, a voltage is generated in the channel, thereby increasing the drain current. The floating body effect will cause the output characteristic curve of the device to warp, that is, the Kink effect. The Kink effect has many adverse effects on device and circuit performance and reliability.

As the integration of semiconductor devices increases, the size of memories such as dynamic random access memory (DRAM) becomes smaller and smaller. Therefore, the structure of 3D DRAM is receiving more and more attention. In 3D DRAM structures, semiconductor pillars are usually stacked horizontally, and word lines or bit lines are usually arranged in a ladder-like manner to save space and improve integration.

However, in current semiconductor structures, floating body effects are more likely to occur.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; a word line, the word line covers the channel region part of the side of the semiconductor pillar, and expose the remaining part of the side of the semiconductor pillar in the channel area; a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and the conductive layer is used to be electrically connected to the ground.

In some embodiments, the cross-sectional shape of the semiconductor pillar is a rectangle in a direction perpendicular to the doping region and toward the channel region, and the word line exposes one side of the semiconductor pillar.

In some embodiments, the semiconductor pillar is parallel to the substrate surface, the word line is parallel to the substrate surface, and the conductive layer is arranged opposite to the word line. It also includes: a conductive pillar, the conductive pillar is perpendicular to the substrate surface, and the conductive pillar is electrically connected to the conductive layer, And the conductive pillar is used for grounding.

In some embodiments, the conductive layer is made of the same material as the conductive pillar.

In some embodiments, the material of the conductive layer includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, At least one of titanium silicides.

In some embodiments, the substrate surface is provided with a plurality of semiconductor pillars stacked in a direction away from the substrate and a plurality of word lines, wherein the side surfaces of part of the semiconductor pillars covering the channel region in the semiconductor pillars are covered, and in the semiconductor pillars, At least part of the side surfaces of the exposed semiconductor pillars in the channel region are electrically connected to the conductive layer.

In some embodiments, the semiconductor structure further includes a conductive pillar, the conductive pillar is electrically connected to the plurality of conductive layers, and the conductive pillar is used to be electrically connected to the ground.

In some embodiments, a bit line is further included, and the bit line is electrically connected to an end of a semiconductor pillar in a doped region.

Correspondingly, embodiments of the present disclosure also provide a method for preparing a semiconductor structure, including: providing a substrate; forming a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and doping regions located on opposite sides of the channel region; forming a word line, the word line covers part of the side of the semiconductor pillar in the channel area, and exposes the remaining part of the side of the semiconductor pillar in the channel area; forming a conductive layer, the conductive layer is electrically connected to at least part of the side of the exposed semiconductor pillar in the channel area, and The conductive layer is used for electrical connection with the ground terminal.

In some embodiments, a method for forming a conductive layer and a word line includes: forming at least two initial semiconductor pillars stacked in a direction away from the substrate on a substrate; forming a first sacrificial layer, the first sacrificial layer being located on an adjacent initial semiconductor pillar between, and the first sacrificial layer at least covers the surface of the initial semiconductor pillar in the channel area; etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer to form a semiconductor pillar and exposing the top surface of the semiconductor pillar; in the channel A word line is formed on the top surface of the semiconductor pillar in the channel area; the first sacrificial layer is removed to expose part of the bottom surface of the semiconductor pillar; a conductive layer is formed on the bottom surface of the semiconductor pillar in the channel area, and the conductive layer located on the bottom surface of one semiconductor pillar is in contact with the adjacent semiconductor pillar. Word lines on the top surface are adjacent in a direction perpendicular to the substrate.

In some embodiments, the substrate is a silicon substrate, and the method of forming the first sacrificial layer includes: forming an initial sacrificial layer, the initial sacrificial layer is located between adjacent initial semiconductor pillars, and the material of the initial sacrificial layer includes first silicon germanium; Part of the initial sacrificial layer is removed to form a first groove, which exposes part of the bottom surface of the initial semiconductor pillar; a first sacrificial layer is formed in the first groove, and the material of the first sacrificial layer is different from the material of the initial sacrificial layer.

In some embodiments, the method of etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer includes: forming a second sacrificial layer stacked with the initial sacrificial layer, and the material of the second sacrificial layer is a second silicon germanium , the germanium content in the second silicon germanium is lower than the germanium content in the first silicon germanium, and the second sacrificial layer is in contact with the top surface of the initial semiconductor pillar and part of the initial sacrificial layer is removed to form the first sacrificial layer; part of the first sacrificial layer is removed The second sacrificial layer exposes the top surface of the initial semiconductor pillar; the top surface of the initial semiconductor pillar is etched to form a semiconductor pillar.

In some embodiments, the method further includes: forming a first dielectric layer, the first dielectric layer being located between an adjacent word line in a direction perpendicular to the substrate and the conductive layer.

In some embodiments, the material of the first dielectric layer includes: a low-k dielectric material.

In some embodiments, a plurality of semiconductor pillars arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars are arranged on the same layer, and the word line covers part of each channel region in a row of semiconductor pillars arranged along the first direction. On the side of the semiconductor pillar, the method of forming the word line includes: forming an isolation structure between adjacent semiconductor pillars along the first direction and covering the side of the semiconductor pillar in the channel region; The top surface is etched until the isolation structure has a predetermined thickness; a word line is formed on the top surface of the semiconductor pillar and part of the side surface of the channel area.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

Figure 2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

Figure 3 is a schematic cross-sectional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

4 to 32 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.

Detailed ways

It can be known from the background art that there is a problem that the floating body effect may occur in current semiconductor structures.

The analysis found that one of the reasons for the floating body effect in the semiconductor structure is that for field-effect transistors, under a sufficiently high drain terminal voltage, the electrons in the channel obtain enough energy in the high field region of the drain terminal to generate electrons through collision ionization. - Hole pairs, holes move to the channel area where the potentials are at the bottom. Due to the higher potential barrier of the gate-source junction, holes will accumulate in the channel area, thus raising the potential of the channel area and causing the gate-source junction to Positive deviation. The positive potential on the floating body reduces the threshold voltage and increases the drain current, thus producing the floating body effect.

Embodiments of the present disclosure provide a semiconductor structure by arranging word lines to cover part of the semiconductor pillar side surfaces of the channel region and exposing the remaining semiconductor pillar side surfaces of the channel area, so that the word lines located on the semiconductor pillar side surfaces of the channel area can Used to control the conduction of the channel, the side of the exposed semiconductor pillar in the channel area can be used for grounding; the conductive layer is electrically connected to the side of the semiconductor pillar in the exposed channel area, and the conductive layer is used to be electrically connected to the ground terminal, so that The charges accumulated in the channel region can be discharged to the ground through the conductive layer, thereby preventing the floating body effect.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to allow the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.

FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. FIG. 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Schematic cross-section of the structure.

Referring to FIGS. 1 to 3 , the semiconductor structure includes: a substrate; a semiconductor pillar 10 located on the substrate, the semiconductor pillar 10 having a channel region 11 and doped regions 12 located on opposite sides of the channel region 11 ; a word line 101 . 101 covers part of the side surfaces of the semiconductor pillars 10 in the channel region 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; the conductive layer 102, the conductive layer 102 and at least part of the side surfaces of the semiconductor pillars 10 in the channel area 11 are exposed Electrically connected, and the conductive layer 102 is used to be electrically connected to the ground.

The conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charges in the channel region 11 can be transferred to the conductive layer 102, and then discharged to the ground via the conductive layer 102, thus preventing the occurrence of The problem of floating body effect occurs due to excessive charge accumulation in the channel region 11 .

The material of the substrate is a semiconductor material. In some embodiments, the material of the substrate is silicon. In other embodiments, the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon on insulator substrate.

The material of the semiconductor pillar 10 may be the same as the material of the substrate. In some embodiments, the material of the semiconductor pillar 10 may be silicon.

The channel region 11 and the doped regions 12 located on both sides of the channel region 11 can be used to form a transistor, wherein the doped regions 12 located on both sides of the channel region 11 can serve as one of the source or drain of the transistor. By. The word line 101 may serve as a gate of the semiconductor structure, and is used to conduct the channel region 11 based on the control signal to realize carrier transfer between the source and the drain. In some embodiments, the doping ion type of the channel region 11 may be different from the doping ion type of the doping region 12 , thereby forming a junction transistor. For example, the doping ion type in the channel region 11 may be P. Type, the type of doping ions in the doping region 12 may be N-type, forming an NMOS transistor. When the semiconductor structure forms an NMOS transistor, electrons move in the channel, and the electrons in the channel obtain enough energy in the high field region of the drain end to generate electron-hole pairs, causing the holes to move toward the channel region 11 with a lower potential. move. That is, holes move from the drain to the source. Since the gate-source junction has a high potential barrier, holes accumulate in the channel region 11 . Therefore, the conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11. When holes move from the drain to the source into the channel region 11, they will be discharged to the ground through the conductive layer 102, thereby Avoid floating body effect.

In other embodiments, the doping ion type of the channel region 11 may be the same as the doping ion type of the doping region 12 to form a junctionless transistor.

In some embodiments, the cross-sectional shape of the semiconductor pillar 10 is rectangular in a direction perpendicular to the doping region 12 and directed toward the channel region 11 , and the word line 101 exposes one side of the semiconductor pillar 10 . That is to say, the word line 101 is arranged around three sides of the semiconductor pillar 10, so that the contact area between the word line 101 and the semiconductor pillar 10 in the channel region 11 is larger, thereby increasing the area of the formed channel and The length enhances the ability of the word line 101 to control the channel and also helps reduce leakage current. The word line 101 is arranged to expose one side of the semiconductor pillar 10 for forming an electrical connection with the conductive layer 102 . The side surface exposed by the word line 101 is arranged opposite to the word line 101, and the conductive layer 102 is electrically connected to the exposed side surface, so that the distance between the conductive layer 102 and the word line 101 is large, thereby preventing the actual preparation of the conductive layer 102. During the process, the distance between the conductive layer 102 and the word line 101 is too close, resulting in the problem of electrical connection between the formed conductive layer 102 and the word line 101 . Specifically, in some embodiments, the word line 101 may completely cover three sides of the semiconductor pillar 10 to increase the contact area between the word line 101 and the semiconductor pillar 10 . In other embodiments, the word line 101 may also cover the side of the semiconductor pillar 10 opposite to the exposed side of the semiconductor pillar 10 , and partially cover the remaining two sides of the semiconductor pillar 10 , so that the word line 101 reaches the side of the exposed semiconductor pillar 10 The distance between them is large. Therefore, when the conductive layer 102 forms an electrical connection with the exposed side of the semiconductor pillar 10 , the distance between the conductive layer 102 and the word line 101 is larger, further preventing the problem of contact between the conductive layer 102 and the word line 101 .

In some embodiments, the semiconductor pillar 10 is parallel to the substrate surface, the word line 101 is parallel to the substrate surface, and the conductive layer 102 is arranged opposite to the word line 101. It also includes: a conductive pillar 103, the conductive pillar 103 is perpendicular to the substrate surface, and the conductive pillar 103 is perpendicular to the substrate surface. 103 is electrically connected to the conductive layer 102, and the conductive pillar 103 is used for grounding. The semiconductor pillars 10 are arranged parallel to the substrate surface, and the word lines 101 are parallel to the substrate surface, so that in the direction perpendicular to the substrate, the sizes occupied by the semiconductor pillars 10 and the word lines 101 are smaller, which is beneficial to the formation of the semiconductor pillars 10 The stacked structure improves the integration of the formed semiconductor structure. Arranging the conductive layer 102 and the word line 101 to face each other can prevent the problem of electrical contact between the conductive layer 102 and the word line 101 due to being too close. Since the word line 101 is parallel to the substrate surface, the conductive layer 102 is also parallel to the substrate surface, and the overall size of the semiconductor structure is small. When the conductive layer 102 is arranged parallel to the substrate surface, it may cause the problem that the conductive layer 102 cannot be connected to the ground. . Based on this, the conductive pillars 103 are arranged perpendicular to the surface of the substrate, that is, perpendicular to the conductive layer 102 . This not only makes it easy for the conductive pillars 103 to form an electrical connection with the ground, but also allows the charges transmitted in the conductive layer 102 to pass through the conductive pillars 103 It is discharged to the ground and is also helpful in reducing the process difficulty of preparing semiconductor structures.

In some embodiments, the conductive layer 102 is made of the same material as the conductive pillars 103 . The conductive layer 102 is made of the same material as the conductive pillar 103 , so that the charge transmission capabilities of the conductive layer 102 and the conductive pillar 103 are close to or the same, so that when the charge is transferred from the conductive layer 102 to the conductive pillar 103 , the charge can be kept relatively fast. The transmission rate allows the charges accumulated in the channel region 11 to be discharged to the ground more quickly, thereby avoiding the floating body effect and maintaining the normal performance of the semiconductor structure.

In some embodiments, the material of the conductive layer 102 includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide. In some embodiments, the substrate is a silicon substrate, and the material of the semiconductor pillar 10 is the same as the substrate, that is, the material of the semiconductor pillar 10 is silicon. In this way, the conductive layer 102 has the same elements as the semiconductor pillar 10 , that is, the conductive layer 102 The material properties of are close to those of the semiconductor pillar 10 . Therefore, when the charges accumulated in the semiconductor pillars 10 in the channel region 11 are transferred to the conductive layer 102, since the material properties of the conductive layer 102 are similar to the material properties of the semiconductor pillars 10, the resistance to charge transfer is small, which is beneficial to Achieve rapid discharge of charge.

In some embodiments, the substrate surface is provided with a plurality of semiconductor pillars 10 stacked in a direction away from the substrate and a plurality of word lines 101, wherein the side surfaces of part of the semiconductor pillar 10 covering the channel region 11 in the semiconductor pillar 10, In addition, in the semiconductor pillar 10 , at least part of the side surfaces of the semiconductor pillar 10 in the exposed channel region 11 is electrically connected to the conductive layer 102 . Each semiconductor pillar 10 is used to form a transistor. Multiple semiconductor pillars 10 are stacked on the surface of the substrate, so that multiple transistors can be formed. Moreover, the stacked semiconductor pillars 10 occupy a smaller size, which is beneficial to Improve the integration level of the formed semiconductor structure. When there are multiple semiconductor pillars 10 , the channel region 11 of each semiconductor pillar 10 needs to be electrically connected to the word line 101 so that the word line 101 can control the conduction of the channel region 11 . In order to reduce the area occupied by the word line 101, the word line 101 is set parallel to the substrate surface, so that the size of the word line 101 in the direction perpendicular to the substrate surface can be reduced, thereby reducing the overall size of the semiconductor structure. Based on this, among the stacked semiconductor pillars 10 , each semiconductor pillar 10 corresponds to a word line 101 , that is, each word line 101 is electrically connected to the channel region 11 in each semiconductor pillar 10 , so that the semiconductor structure can be maintained. While the size is small, the channel region 11 of each semiconductor pillar 10 can be controlled. Since the conductive layer 102 is arranged opposite to the word line 101, when the word line 101 is parallel to the substrate surface, the conductive layer 102 is parallel to the substrate, thereby preventing the conductive layer 102 from electrical contact with the word line 101. Based on this, in the stacked semiconductor pillars 10 , the side surfaces of each exposed semiconductor pillar 10 in the channel region 11 are electrically connected to a conductive layer 102 respectively, so that no electrical contact is formed between the stacked semiconductor pillars 10 . Electrical interference occurs, and the charges accumulated in each channel region 11 can be discharged to the ground through the conductive layer 102 .

In some embodiments, the semiconductor structure further includes conductive pillars 103, the conductive pillars 103 are electrically connected to the plurality of conductive layers 102, and the conductive pillars 103 are used to be electrically connected to the ground. When a plurality of stacked semiconductor pillars 10 are provided on the substrate surface, each semiconductor pillar 10 corresponds to a conductive layer 102 , and the conductive layer 102 is arranged parallel to the substrate surface, which is equivalent to a stacked arrangement of the conductive layers 102 . Since the conductive pillars 103 are arranged perpendicular to the conductive layer 102 for grounding the conductive layer 102, and the conductive pillars 103 do not form an electrical connection with the semiconductor pillars 10, that is, there is no need to consider whether electrical contact will be formed between the conductive pillars 103 and the semiconductor pillars 10. The problem. Therefore, only one conductive pillar 103 can be provided to be electrically connected to multiple stacked conductive layers 102. Compared with one conductive pillar 103 being electrically connected to one conductive layer 102, the size of the conductive pillar 103 is greatly reduced, thereby reducing size of small semiconductor structures. And the charges transmitted in each conductive layer 102 can be discharged to the ground through the same conductive pillar 103 .

In some embodiments, the side of the semiconductor pillar 10 away from the substrate is electrically connected to the word line 101 , and the side of the semiconductor pillar 10 facing the substrate is electrically connected to the conductive layer 102 . When multiple stacked semiconductor pillars 10 are provided on the surface of the substrate, the word line 101 corresponding to one of the semiconductor pillars 10 will be arranged adjacent to the conductive layer 102 corresponding to the adjacent semiconductor pillar 10 . Based on this, in some embodiments, a first dielectric layer 104 is also included. The first dielectric layer 104 is located between the adjacent word line 101 and the conductive layer 102 and is used to isolate the adjacent word line 101 and the conductive layer 102. , to prevent the word line 101 and the conductive layer 102 from forming an electrical connection and causing electrical interference. Specifically, in some embodiments, the material of the first dielectric layer 104 may be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.

In some embodiments, a bit line 105 is also included, and the bit line 105 is electrically connected to an end of the semiconductor pillar 10 of a doped region 12 . In this way, the bit line 105 can extract electrical signals from the doped region 12 located on one side of the channel region 11 . In addition, since there is a large operating space at the end of the semiconductor pillar 10, the process difficulty of preparing the bit line 105 at the end of the semiconductor pillar 10 can be reduced, which is beneficial to improving the quality of the semiconductor structure. Yield.

In some embodiments, a plurality of semiconductor pillars 10 arranged in an array are provided on the surface of the substrate, and the plurality of semiconductor pillars 10 are arranged on the same layer. The word line 101 covers each of a row of semiconductor pillars 10 arranged along the first direction X. On some side surfaces of the semiconductor pillars 10 of the channel region 11 and in a row of semiconductor pillars 10 arranged along the second direction Y, a doping region 12 in two adjacent semiconductor pillars 10 is electrically connected to the same bit line 105. One direction X is parallel to the substrate surface, and the second direction Y is the stacking direction of the plurality of semiconductor pillars 10 . The first direction X is different from the second direction Y. Arranging a plurality of semiconductor pillars 10 arranged in an array on the surface of the substrate is beneficial to increasing the arrangement density of the semiconductor pillars 10 and thereby increasing the integration level of the semiconductor pillars 10 . A plurality of semiconductor pillars 10 arranged in an array are arranged on the same layer. That is to say, the semiconductor pillars 10 arranged in an array are not stacked. When there are multiple semiconductor pillars 10 stacked on the surface of the substrate, the stacked semiconductor pillars 10 are not in the same layer. In the stacked semiconductor pillars 10 , the layer where each semiconductor pillar 10 is located has multiple semiconductors arranged in an array. Column 10. That is to say, when multiple semiconductor pillars 10 are provided on the surface of the substrate, the multiple semiconductor pillars 10 can be arranged in different layers. The semiconductor pillars 10 of each layer are arranged in an array, and the semiconductor pillars 10 arranged in the array can be stacked. In this way, the arrangement density of the semiconductor pillars 10 can be further increased, making the semiconductor pillars 10 more integrated.

Among the semiconductor pillars 10 arranged in an array in each layer, the arrangement direction of the semiconductor pillars 10 is parallel to the substrate surface, and the word lines 101 are also parallel to the substrate surface. Therefore, the word lines 101 can be arranged to be arranged along the first direction X. Part of the semiconductor pillars 10 of each channel region 11 in a row of semiconductor pillars 10 is covered on the side, that is, multiple semiconductor pillars 10 arranged along the first direction volume, thereby reducing the overall size of the semiconductor structure.

The bit line 105 is disposed perpendicularly to the word line 101 , that is, the bit line 105 has the same stacking direction as the plurality of semiconductor pillars 10 . Therefore, the bit line 105 can be set to be electrically connected to one of the doped regions 12 in a row of semiconductor pillars 10 arranged along the second direction Y, so that the stacked semiconductor pillars 10 can share the same bit line 105, which can further enable The bit line 105 occupies a smaller volume, thereby further reducing the overall size of the semiconductor structure.

In some embodiments, the bit line 105 may include a barrier layer, a conductive portion, and an insulating layer sequentially stacked in a direction away from the semiconductor pillar 10 . In some embodiments, the conductive part may be a metal material, such as any one of tungsten, copper, or aluminum. In other embodiments, the conductive part may also be a semiconductor material, such as polysilicon. The barrier layer prevents mutual diffusion between the conductive part and the doped region 12. The material of the barrier layer may be titanium nitride. The insulating layer is used to isolate the conductive part from other conductive devices in the semiconductor structure. The material of the insulating layer may be silicon oxide. Or any of silicon nitride.

In some embodiments, the material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.

In some embodiments, a gate dielectric layer 106 may also be included. The gate dielectric layer 106 is located between the word line 101 and the semiconductor pillar 10 of the channel region 11 . The gate dielectric layer 106 is used to isolate the word line 101 from the semiconductor pillar 10 in the channel region 11. The gate dielectric layer 106 is located on the surface of the semiconductor pillar 10 in the channel area 11, so that the transistor composed of the semiconductor pillar 10 becomes a low-voltage device. In other words, due to the existence of the gate dielectric layer 106, a smaller voltage is applied to the transistor to turn on the transistor and complete the writing of data, which is beneficial to improving the performance of the semiconductor structure. In some embodiments, the material of the gate dielectric layer 106 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It also includes: a barrier layer 107. The barrier layer 107 is located between the gate dielectric layer 106 and the word line 101 to prevent mutual diffusion of ions in the gate dielectric layer 106 and the word line 101. The material of the barrier layer 107 may include titanium nitride.

In some embodiments, a capacitor structure 108 is also included, and the capacitor structure 108 is electrically connected to another doped region 12 in the semiconductor pillar 10 . That is, the bit line 105 and the capacitor structure 108 are electrically connected to the two doped regions 12 in the semiconductor pillar 10 respectively. Specifically, the capacitive structure 108 may include a lower electrode layer (not shown), a capacitive dielectric layer (not shown), and an upper electrode layer (not shown) sequentially stacked in a direction away from the semiconductor pillar 10 , wherein the lower electrode layer The material and the material of the upper electrode layer can be the same. The material of the lower electrode layer and the material of the upper electrode layer can be platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium. of at least one. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different. The materials of the capacitor dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, and titanium oxide.

In the technical solution of the semiconductor structure provided by the above embodiments, the word line 101 is arranged to cover part of the semiconductor side surfaces of the channel region 11 and expose the remaining part of the semiconductor pillar 10 side surfaces of the channel region 11. In this way, the semiconductor pillars 10 located in the channel region 11 are exposed. The word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel area 11; the conductive layer 102 is electrically connected to the exposed side of the semiconductor pillar 10 of the channel area 11, and the conductive layer 102 is used to be electrically connected to the ground. This allows the charges accumulated in the channel region 11 to be discharged to the ground through the conductive layer 102, thereby preventing the floating body effect from occurring.

Correspondingly, embodiments of the present disclosure also provide a method for preparing a semiconductor structure. The method of preparing a semiconductor structure can be used to prepare the semiconductor structure provided by the above embodiments. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. illustrate.

Figure 6 corresponds to the schematic cross-sectional structural diagram in the aa' direction in Figure 5.

Referring to FIG. 4 and FIG. 6 , a substrate 100 is provided. In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

Referring to Figures 7 to 32, a semiconductor pillar 10 is formed on a substrate 100. The semiconductor pillar 10 has a channel region 11 and doping regions 12 located on opposite sides of the channel region 11; a word line 101 is formed, and the word line 101 covers the trench. part of the side surfaces of the semiconductor pillars 10 in the channel area 11, and exposes the remaining part of the side surfaces of the semiconductor pillars 10 in the channel area 11; a conductive layer 102 is formed, and the conductive layer 102 is electrically connected to at least part of the side surfaces of the exposed semiconductor pillars 10 in the channel area 11, And the conductive layer 102 is used for electrical connection with the ground.

In some embodiments, the number of semiconductor pillars 10 may be multiple, thereby increasing the integration level of the semiconductor structure. In some embodiments, the material of the semiconductor pillar 10 may be the same as the material of the substrate 100 . The doped regions 12 on both sides of the channel region 11 can serve as the source and drain of the transistor, and the word line 101 can serve as the gate of the transistor for controlling the conduction of the source and drain. In some embodiments, the doping ion type of the doping region 12 may be the same as the doping ions of the channel region 11 , so that the type of transistor formed is a junctionless transistor. In other embodiments, the doping ion type of the doping region 12 is different from the doping ion type of the channel region 11 , so that the type of the formed transistor is a junction transistor.

In some embodiments, a method of forming a conductive layer and a word line includes:

Referring to FIG. 6 , at least two initial semiconductor pillars 20 stacked in a direction away from the substrate 100 are formed on the substrate 100 . In this way, multiple stacked semiconductor pillars can be formed, and each semiconductor pillar can be used to form a transistor, thereby improving semiconductor Structural integration.

In some embodiments, a plurality of semiconductor pillars 10 arranged in an array can also be formed in the substrate 100 . The semiconductor pillars 10 arranged in a plurality of arrays are arranged in the same layer, and the semiconductor pillars 10 arranged in a multi-layer array can be stacked. Based on this, referring to Figures 4 and 5, in some embodiments, the substrate 100 can be divided into a first area 1 and a second area 2, and a multi-layer stack is formed in the first area 1 and the second area 2 respectively. Semiconductor pillar 10. The method of forming the first area 1 and the second area 2 may include: patterning the surface of the initial semiconductor pillar 20 to define the positions of the first area 1 and the second area 2. Specifically, the method may be on the top surface of the initial semiconductor pillar 20. The first mask layer 21 is formed, and the first mask layer 21 exposes the location that needs to be etched. In some embodiments, a capping layer 22 is formed on top of the initial semiconductor pillar 20 to protect the initial semiconductor pillar 20 . The capping layer Specifically, 22 may be a silicon oxide layer and a silicon nitride layer stacked in a direction away from the substrate 100. Therefore, a first mask layer 21 may be formed on the surface of the cover layer 22. In some embodiments; for the initial semiconductor of the patterning process The pillar 20 undergoes an etching process to form the first region 1 and the second region 2 . It is worth noting that the process method for forming the semiconductor pillars 10 in the first region 1 and the second region 2 may be the same. The following will take the formation of multiple semiconductor pillars 10 in the first region 1 as an example for description.

Figure 7 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 8 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5; Figure 9 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 10 corresponds to Figure Schematic diagram of the cross-sectional structure in the bb' direction in 5.

Referring to FIGS. 4 to 10 , a first sacrificial layer 23 is formed, the first sacrificial layer 23 is located between adjacent initial semiconductor pillars 20 , and the first sacrificial layer 23 at least covers the surface of the initial semiconductor pillar 20 in the channel region 11 ; A sacrificial layer 23 is located on the surface of the initial semiconductor pillar 20 in the channel region 11 to reserve space for the subsequent formation of the conductive layer 102, so that during the process of forming the word line 101, the process of forming the word line 101 will not damage the first sacrificial layer 23. Damage is formed on the covered surface of the initial semiconductor pillar 20 . Therefore, good electrical contact can be formed between the subsequently formed semiconductor layer and the surface of the semiconductor pillar 10 in the channel region 11 .

In some embodiments, the substrate 100 is a silicon substrate, and the method of forming the first sacrificial layer 23 includes:

Referring to FIG. 6 , an initial sacrificial layer 24 is formed. The initial sacrificial layer 24 is located between adjacent initial semiconductor pillars 20 . The material of the initial sacrificial layer 24 includes first silicon germanium. Since the substrate 100 is a silicon substrate, the initial sacrificial layer 24 is provided. The material of layer 24 includes first silicon germanium, so that the initial sacrificial layer 24 and the substrate 100 have the same silicon element, so that the silicon substrate matches the lattice constant of silicon germanium. Therefore, when the epitaxial process is used to form the initial semiconductor pillars 20 and the first sacrificial layer 23 at alternating intervals on the substrate 100, the silicon in the silicon substrate can be used to grow silicon germanium more easily, making the preparation process simple and forming There is a clear boundary between the first sacrificial layer 23 and the initial semiconductor pillar 20 , which facilitates subsequent complete removal of the first sacrificial layer 23 located on the surface of the initial semiconductor pillar 20 .

Referring to FIGS. 7 and 8 , part of the initial sacrificial layer 24 is removed to form a first groove 26 . The first groove 26 exposes part of the bottom surface of the initial semiconductor pillar 20 . In this way, the first sacrificial layer subsequently formed in the first groove 26 Layer 23 may cover the bottom surface of initial semiconductor pillar 20 . In some embodiments, an etching process can be used to remove part of the initial sacrificial layer 24 . Since the material of the initial sacrificial layer 24 is different from the material of the initial semiconductor layer, the etching process can be used to remove parts of the initial sacrificial layer 24 and the initial semiconductor layer. Different etching selectivity ratios realize selective etching. Specifically, the etching process may be either dry etching or wet etching. Only part of the initial sacrificial layer 24 is removed, so that the remaining part of the sacrificial layer is still located between adjacent initial semiconductor pillars 20 to play a supporting and isolating role.

Referring to FIGS. 7 to 9 , a first sacrificial layer 23 is formed in the first groove 26 , and the material of the first sacrificial layer 23 is different from the material of the initial sacrificial layer 24 . Considering that the first sacrificial layer 23 is used to reserve space for the subsequent formation of the conductive layer 102, the first sacrificial layer 23 needs to have a greater hardness to prevent damage to the first sacrificial layer 23 when the word line 101 is subsequently formed. Process damage. Since the material of the initial sacrificial layer 24 is the first silicon germanium, it is easier to form the first silicon germanium on the surface of the silicon substrate than with other materials. Therefore, an initial sacrificial layer 24 is first formed on the substrate 100 to form a stacked structure of the initial sacrificial layer 24 and the initial semiconductor pillar 20 . The initial sacrificial layer 24 reserves space for the subsequent formation of the first sacrificial layer 23 . Then, the initial sacrificial layer 24 is removed, and the first sacrificial layer 23 is formed at the original position of the first sacrificial layer 23. The first sacrificial layer 23 reserves space for the subsequent formation of the conductive layer 102. In this way, the quality of the semiconductor structure formed in each step of the process is higher, so that the yield rate of the finally formed semiconductor structure is higher.

In some embodiments, a deposition process may be used to form the first sacrificial layer 23 in the first groove 26 , for example, it may be any one of a thermal oxidation process or an atomic layer deposition process. The material of the first sacrificial layer 23 may be silicon nitride.

Figure 11 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 12 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 5; Figure 13 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5; Figure 14 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 5 Schematic diagram of the cross-sectional structure in the bb' direction in 5.

Referring to FIGS. 11 to 14 , after the first sacrificial layer 23 is formed, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is etched to form the semiconductor pillar 10 and expose the top surface of the semiconductor pillar 10 , that is, the top surface of the semiconductor pillar 10 is exposed. The initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is thinned. On the one hand, it is beneficial to reduce the size of the semiconductor pillar 10. On the other hand, it can reserve enough space for the subsequent formation of the word line 101 on the top surface of the semiconductor pillar 10. .

Since the epitaxial process is used to form the initial sacrificial layer 24 between the surface of the silicon substrate and the initial semiconductor pillar 20, and the atomic radius of the germanium atom is larger than the atomic radius of the silicon atom, due to reasons such as stress and lattice defects, the epitaxial layer 24 is formed on the silicon substrate due to reasons such as stress and lattice defects. The thickness of the first silicon germanium layer is smaller. In order to form the initial sacrificial layer 24 with a larger thickness, the thickness of the preformed initial semiconductor pillar 20 needs to be larger, so that the initial sacrificial layer 24 epitaxially formed on the surface of the initial semiconductor pillar 20 has a larger thickness. Based on this, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 needs to be etched subsequently, so that the thickness of the formed semiconductor pillar 10 meets the requirements.

Since the first sacrificial layer 23 covers the surface of the initial semiconductor pillar 20 in the channel area 11, after etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23, the exposed top surface of the semiconductor pillar 10 becomes the channel area. 11 on the top surface of the semiconductor pillar 10 . In this way, when the word line 101 is subsequently formed on the exposed top surface of the semiconductor pillar 10 , the word line 101 can be electrically connected to the surface of the semiconductor pillar 10 in the channel region 11 .

In some embodiments, the method of etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 includes:

Referring to FIG. 6 , a second sacrificial layer 25 is formed stacked with the initial sacrificial layer 24 . The material of the second sacrificial layer 25 is second silicon germanium. The germanium content in the second silicon germanium is lower than that in the first silicon germanium. germanium content, and the second sacrificial layer 25 is in contact with the top surface of the initial semiconductor pillar 20; the etching amount of silicon germanium is related to the germanium content in silicon germanium. When the germanium content in silicon germanium is higher, the etching amount of silicon germanium is The more difficult it is to etch silicon germanium, that is, the smaller the etching amount of silicon germanium is. The germanium content of the second silicon germanium is set to be lower than the germanium content of the first silicon germanium. In this way, when etching the first silicon germanium, the etching selection of the first silicon germanium and the second silicon germanium can be utilized. ratio, so that the etching process will not etch the second silicon germanium adjacent to the first silicon germanium, so that the morphology of the formed first sacrificial layer 23 meets expectations.

It can be understood that in other embodiments, the germanium content in the first silicon germanium may also be less than the germanium content in the second silicon germanium, as long as the germanium content in the first silicon germanium and the second germanium content are satisfied. The content of germanium in the silicon oxide can vary.

Referring to FIGS. 7 to 10 , a portion of the initial sacrificial layer 24 is removed to form a first sacrificial layer 23 .

Referring to Figures 11 and 12, part of the second sacrificial layer 25 is removed to expose the top surface of the initial semiconductor pillar 20; that is, before etching the top surface of the initial semiconductor pillar 20, the second sacrificial layer 25 is first etched, to expose the top surface of the semiconductor pillar 10 . Compared with not forming the second sacrificial layer 25 and directly etching the top surface of the initial semiconductor in contact with the first sacrificial layer 23, the process of etching the initial semiconductor pillar 20 is simpler, and the etching process formed after the etching is The top surface of the semiconductor pillar 10 is smoother and more in line with expectations. This is because after etching the second sacrificial layer 25, the top surface of the initial semiconductor pillar 20 is exposed, so that the gas or solution used in the etching process can evenly contact the top surface of the initial semiconductor pillar 20, and the etching process The contact area between the gas or liquid and the top surface of the semiconductor pillar 10 is large, which is beneficial to the etching process and makes the top surface of the formed semiconductor pillar 10 relatively smooth.

Referring to FIGS. 13 and 14 , the top surface of the initial semiconductor pillar 20 is etched to form the semiconductor pillar 10 .

Referring to FIGS. 15 to 32 , after the top surface of the semiconductor pillar 10 is exposed, a word line 101 is formed on the top surface of the semiconductor pillar 10 in the channel region 11 . The formed word line 101 can also cover at least part of the top surface of the semiconductor pillar 10 . Both sides of the connection are connected, so that the word line 101 surrounds at least part of the side surfaces of the semiconductor pillar 10 of the channel area 11 , and the remaining part of the side surface of the semiconductor pillar 10 of the channel area 11 can be used to be electrically connected to the ground terminal, so that the channel area 11 The charge accumulated in can be discharged to the ground.

In some embodiments, the surface of the substrate 100 is provided with a plurality of semiconductor pillars 10 arranged in an array, and the plurality of semiconductor pillars 10 are arranged on the same layer. The word line 101 covers each semiconductor pillar 10 in a row arranged along the first direction X. A method of forming the word line 101 on the side of a portion of the semiconductor pillar 10 in the channel region 11 includes:

Figure 16 corresponds to the schematic cross-sectional structure diagram in the direction aa' in Figure 15; Figure 17 corresponds to the schematic cross-sectional structure diagram in the bb' direction in Figure 15; Figure 19 corresponds to the schematic cross-sectional structure diagram in the aa' direction in Figure 18; Figure 20 corresponds to Figure The schematic cross-sectional structural diagram in the aa' direction in Figure 18; Figure 22 corresponds to the cross-sectional structural diagram in the aa' direction in Figure 5.

Referring to FIGS. 15 to 22 , an isolation structure 29 is formed. The isolation structure 29 is located between adjacent semiconductor pillars 10 along the first direction X and covers the side surfaces of the semiconductor pillars 10 in the channel region 11 . The isolation structure 29 is used to isolate adjacent semiconductor pillars 10 so that no electrical contact occurs between adjacent semiconductor pillars 10 along the first direction X.

Specifically, the method of forming the isolation structure 29 may include:

Referring to FIGS. 15 to 17 , a second dielectric layer 27 is formed on the top surface of each semiconductor pillar 10 . The second dielectric layer 27 fills the gap between the semiconductor pillar 10 and the first sacrificial layer 23 for subsequent formation of word lines. 101 reserved space. The second dielectric layer 27 can prevent the isolation structure 29 from being simultaneously formed between the top surface of the semiconductor pillar 10 and the first sacrificial layer 23 when the material of the isolation structure 29 is subsequently deposited to form the isolation structure 29 . Specifically, in some embodiments, a deposition process may be used to form the second dielectric layer 27. When the material of the first sacrificial layer 23 is silicon nitride, the material of the second dielectric layer 27 may be a low-k dielectric material. There is a large etching selectivity ratio between low-k dielectric materials and silicon nitride materials, such as Therefore, when the second dielectric layer 27 needs to be removed later to form the word line 101, the etching selectivity can be used to remove only the second dielectric layer 27 while retaining the first sacrificial layer 23.

Referring to Figures 18 and 19, the top surface of the top semiconductor pillar 10 is patterned to define the position of the semiconductor pillar 10 arranged in an array. Specifically, a second mask layer 28 can be formed on the top surface of the top semiconductor pillar 10. , the second mask layer 28 exposes the top surface of the semiconductor pillar 10 that needs to be etched. Specifically, in some embodiments, before forming the second mask layer 28 , the silicon nitride layer in the cap layer 22 may be removed first, leaving only the silicon oxide layer, which is beneficial to the etching process. After removing the silicon nitride layer, a second mask layer 28 is formed on the surface of the silicon oxide layer.

Referring to FIG. 20 , an etching process is performed on the top surface of the patterned semiconductor pillars 10 to form semiconductor pillars 10 arranged in an array, wherein a plurality of semiconductor pillars 10 are arranged at intervals along the first direction X, and adjacent semiconductor pillars There is a gap between 10.

Referring to FIGS. 21 and 22 , a deposition process is used to deposit an isolation material between adjacent semiconductor pillars 10 to form an isolation structure 29 . The isolation structure 29 fills the gap between adjacent semiconductor pillars 10 and covers each The side surface of the semiconductor pillar 10 . Specifically, in some embodiments, the material of the isolation structure 29 may be silicon oxide.

Figure 24 corresponds to the schematic cross-sectional structural diagram in the direction aa’ in Figure 23; Figure 25 corresponds to the schematic cross-sectional structural diagram in the direction bb’ in Figure 23.

After the isolation structure 29 is formed, refer to FIGS. 23 to 25 to remove the second dielectric layer 27 to expose the top surface of the semiconductor pillar 10 and the bottom surface of the first sacrificial layer 23 . In this way, the word line 101 can be formed on the exposed top surface of the semiconductor pillar 10 .

Figure 27 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26; Figure 28 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.

Referring to FIGS. 26 to 28 , word lines 101 are formed on the top surface and part of the side surfaces of the semiconductor pillar 10 in the channel region 11 . Specifically, before forming the word line 101 , the top surface of the isolation structure 29 between adjacent semiconductor pillars 10 is etched until the isolation structure 29 has a preset thickness, so that there is a gap between adjacent semiconductor pillars 10 , and only a portion of the isolation structure 29 located between adjacent semiconductor pillars 10 is etched, so that the remaining portion of the isolation structure 29 located between the semiconductor pillars 10 can still play an isolation role. In this way, when the word line 101 material is deposited on the top surface of the semiconductor pillar 10 to form the word line 101, the word line 101 can also be formed on the side of the semiconductor pillar 10, so that the word line 101 can cover the top surface of the semiconductor pillar 10 and connect with the top surface. Part of the side where the faces meet.

In some embodiments, when the material of the isolation structure 29 is silicon oxide, in the step of etching the isolation structure 29 between adjacent semiconductor pillars 10, part of the isolation structure 29 located on the side of the semiconductor pillar 10 can be retained, so that Therefore, the isolation structure 29 located on the side of the semiconductor pillar 10 can serve as the gate dielectric layer 106 .

In some embodiments, the method of forming the word line 101 includes: forming a gate dielectric layer 106 on the top surface of the exposed semiconductor pillar 10, and the gate dielectric layer 106 is connected to the isolation structure 29 located on the side of the semiconductor pillar 10. In some embodiments, , a deposition process can be used to form the gate dielectric layer 106 on the top surface of the semiconductor pillar 10 , and the material of the gate dielectric layer 106 can be silicon oxide.

A deposition process is used to form a barrier layer 107 on the surface of the gate dielectric layer 106. In some embodiments, the material of the barrier layer 107 may be silicon nitride.

A deposition process is used to form a word line 101 on the surface of the gate dielectric layer 106. The material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt or ruthenium.

It can be understood that after the second dielectric layer 27 is removed, the first sacrificial layer 23 and the top surface of the semiconductor pillar 10 are exposed. Therefore, the gate dielectric layer 106 and the word line 101 are formed on the top surface of the semiconductor pillar 10 using a deposition process. at the same time, the first sacrificial layer 23 will also A first gate dielectric layer 32 and a first word line 31 are formed on the bottom surface. In order to easily remove the first gate dielectric layer 32 and the first word line 31 located on the bottom surface of the first sacrificial layer 23 later, when the thickness of the word line 101 located on the top surface of the semiconductor pillar 10 is as expected, the deposition process is stopped, and the semiconductor pillar 10 is An initial dielectric layer 30 is formed between the word line 101 on the top surface and the first word line 31 on the bottom surface of the first sacrificial layer 23 for isolating the word line 101 on the top surface of the semiconductor pillar 10 and the first word line 31 on the bottom surface of the first sacrificial layer 23 Line 31. In this way, when the first gate dielectric layer 32 and the first word line 31 on the bottom surface of the first sacrificial layer 23 are subsequently removed, due to the existence of the initial dielectric layer 30, the word line 101 and the first word line 101 on the top surface of the semiconductor pillar 10 can be removed. The sacrificial layer 23 plays a protective role.

Figure 29 corresponds to the schematic cross-sectional structural diagram in the direction aa' in Figure 26; Figure 30 corresponds to the schematic cross-sectional structural diagram in the bb' direction in Figure 26.

Referring to Figures 29 and 30, after forming the word line 101, the first sacrificial layer 23 is removed to expose part of the bottom surface of the semiconductor pillar 10; the exposed bottom surface of the semiconductor pillar 10 can be used to form the conductive layer 102, so that the conductive layer 102 is connected to part of the trench. The surface of the semiconductor pillar 10 in the channel region 11 is electrically connected, and the conductive layer 102 is used for grounding, so that the charges accumulated in the channel region 11 can be discharged to the ground via the conductive layer 102 .

Figure 31 corresponds to the cross-sectional structural schematic diagram in the aa' direction in Figure 26; Figure 32 corresponds to the cross-sectional structural diagram in the bb' direction in Figure 26.

Referring to FIGS. 31 to 32 , a conductive layer 102 is formed on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and the conductive layer 102 on the bottom surface of one semiconductor pillar 10 and the word line 101 on the top surface of the adjacent semiconductor pillar 10 are in a vertical position. adjacent in the direction of the base. Since multiple semiconductor pillars 10 are stacked and the conductive layer 102 is located on the bottom surface of the semiconductor pillar 10 and the word line 101 is located on the top surface of the semiconductor pillar 10, there is a conductive layer of one semiconductor pillar 10 between two adjacent semiconductor pillars 10. 102 is adjacent to the word line 101 of another semiconductor pillar 10 .

In order to prevent adjacent word lines 101 from forming electrical contact with the conductive layer 102, in some embodiments, it also includes: forming a first dielectric layer 104. The first dielectric layer 104 is located on the adjacent word lines 101 in a direction perpendicular to the substrate. and the conductive layer 102. The material of the first dielectric layer 104 may be the same as the material of the initial dielectric layer 30 . This is because the initial dielectric layer 30 is located between adjacent semiconductor pillars 10 . Therefore, there is no need to remove the initial dielectric layer 30 formed in the previous steps. This is beneficial to saving process steps and saving materials for forming the first dielectric layer 104 . Specifically, in some embodiments, the material of the first dielectric layer 104 may be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 may also be one of nitrides, such as silicon nitride.

In some embodiments, before forming the conductive layer 102 , the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23 may be removed, and the initial dielectric layer 30 may be retained. In this way, it is possible to prevent the formation of the conductive layer 102 on the surface of the gate dielectric layer 106 on the bottom surface of the first sacrificial layer 23, and subsequent removal of the gate dielectric layer 106 and the word line 101 on the bottom surface of the first sacrificial layer 23, which may cause the conductive layer 102 to be produced. Injury issues.

In some embodiments, after removing the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23, the material of the first dielectric layer 104 can be deposited on the top surface of the initial dielectric layer 30, so as to be consistent with the initial dielectric layer 30. The dielectric layers 30 together form the first dielectric layer 104 .

In some embodiments, a deposition process can be used to form the conductive layer 102 on the bottom surface of the semiconductor pillar 10 in the channel region 11 , and due to the existence of the initial dielectric layer 30 , the formed conductive layer 102 will not interact with the top surface of another semiconductor pillar 10 The word lines 101 form electrical contacts. In some embodiments, the material of the conductive layer 102 may be polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide , at least one of titanium silicide.

In the preparation method of the semiconductor structure provided in the above embodiment, the formed word line 101 covers part of the side surfaces of the semiconductor pillars 10 of the channel area 11 and exposes the remaining part of the side surfaces of the semiconductor pillars 10 of the channel area 11 , so that the word line 101 is located in the channel area 11 The word line 101 on the side of the semiconductor pillar 10 can be used to control the conduction of the channel, and the side of the semiconductor pillar 10 of the exposed channel region 11 can be used for grounding; the formed conductive layer 102 is connected with the exposed The side surfaces of the semiconductor pillars 10 of the channel region 11 are electrically connected, and the conductive layer 102 is used to electrically connect with the ground terminal, so that the charges accumulated in the channel region 11 can be discharged to the ground terminal through the conductive layer 102, thereby preventing the floating body effect. produce.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present disclosure. scope. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

A semiconductor structure including:

base(100);

A semiconductor pillar (10) located on the substrate (100), the semiconductor pillar (10) having a channel region (11) and doping regions (12) located on opposite sides of the channel region (11);

Word line (101), the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of the channel area (11), and exposes the remaining part of the semiconductor pillars (10) of the channel area (11) side;

Conductive layer (102), the conductive layer (102) is electrically connected to at least part of the side surfaces of the exposed semiconductor pillar (10) of the channel region (11), and the conductive layer (102) is used to connect to the ground terminal. Electrical connection.
The semiconductor structure according to claim 1, wherein the cross-sectional shape of the semiconductor pillar (10) is rectangular in a direction perpendicular to the doping region (12) and directed to the channel region (11), so The word line (101) exposes one side of the semiconductor pillar (10).
The semiconductor structure according to claim 1, wherein the semiconductor pillar (10) is parallel to the surface of the substrate (100), the word line (101) is parallel to the surface of the substrate (100), and the conductive The layer (102) is arranged opposite to the word line (101), and further includes: a conductive pillar (103), the conductive pillar (103) is perpendicular to the surface of the substrate (100), and the conductive pillar (103) is connected to the The conductive layer (102) is electrically connected, and the conductive pillar (103) is used for grounding.
The semiconductor structure of claim 3, wherein the conductive layer (102) is made of the same material as the conductive pillar (103).
The semiconductor structure according to claim 1 or 4, wherein the material of the conductive layer (102) includes: polysilicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper , at least one of aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide.
The semiconductor structure according to claim 1, wherein the surface of the substrate (100) is provided with a plurality of semiconductor pillars (10) stacked in a direction away from the substrate (100) and a plurality of word lines (101), wherein, The word line (101) covers part of the side surfaces of the semiconductor pillar (10) of the channel region (11) in the semiconductor pillar (10), and in the semiconductor pillar (10), the exposed trench At least part of the side surfaces of the semiconductor pillars (10) of the track region (11) are electrically connected to the conductive layer (102).
The semiconductor structure according to claim 6, wherein the semiconductor structure further includes a conductive pillar (103), the conductive pillar (103) is electrically connected to a plurality of the conductive layers (102), and the conductive pillar (103) 103) is used for electrical connection with the ground.
The semiconductor structure according to claim 6, further comprising: a bit line (105), the bit line (105) being electrically connected to an end of the semiconductor pillar (10) of the doped region (12).
A method for preparing a semiconductor structure, including:

provideBase(100);

Forming a semiconductor pillar (10) on the substrate (100), the semiconductor pillar (10) having a channel region (11) and doped regions (12) located on opposite sides of the channel region (11);

Forming a word line (101), the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of the channel area (11), and exposes the remaining part of the semiconductor pillars (10) of the channel area (11). )side;

A conductive layer (102) is formed, the conductive layer (102) is electrically connected to at least part of the side surfaces of the exposed semiconductor pillar (10) of the channel region (11), and the conductive layer (102) is used to connect to ground. terminal electrical connection.
The method of preparing a semiconductor structure according to claim 9, wherein the method of forming the conductive layer (102) and the word line (101) includes:

forming at least two initial semiconductor pillars (20) stacked in a direction away from the substrate (100) on the substrate (100);

A first sacrificial layer (23) is formed, the first sacrificial layer (23) is located between the adjacent initial semiconductor pillars (20), and the first sacrificial layer (23) at least covers the channel region The surface of the initial semiconductor pillar (20) of (11);

Etch the top surface of the initial semiconductor pillar (20) corresponding to the first sacrificial layer (23) to form a semiconductor pillar (10), and expose the top surface of the semiconductor pillar (10);

A word line (101) is formed on the top surface of the semiconductor pillar (10) in the channel region (11);

Remove the first sacrificial layer (23) to expose part of the bottom surface of the semiconductor pillar (10);

The conductive layer (102) is formed on the bottom surface of the semiconductor pillar (10) in the channel region (11), and the conductive layer (102) located on the bottom surface of one of the semiconductor pillars (10) is connected to all adjacent ones. The word lines (101) on the top surface of the semiconductor pillar (10) are adjacent in a direction perpendicular to the substrate (100).
The method of preparing a semiconductor structure according to claim 10, wherein the substrate (100) is a silicon substrate, and the method of forming the first sacrificial layer (23) includes:

Form an initial sacrificial layer (24), the initial sacrificial layer (24) is located between the adjacent initial semiconductor pillars (20), the material of the initial sacrificial layer (24) includes first silicon germanium;

Remove part of the initial sacrificial layer (24) to form a first groove (26), and the first groove (26) exposes part of the bottom surface of the initial semiconductor pillar (20);

The first sacrificial layer (23) is formed in the first groove (26), and the material of the first sacrificial layer (23) is different from the material of the initial sacrificial layer (24).
The method of preparing a semiconductor structure according to claim 11, wherein the method of etching the top surface of the initial semiconductor pillar (20) corresponding to the first sacrificial layer (23) includes:

Forming a second sacrificial layer (25) stacked with the initial sacrificial layer (24), the material of the second sacrificial layer (25) is second silicon germanium, and the germanium content in the second silicon germanium Lower than the germanium content in the first silicon germanium, and the second sacrificial layer (25) is in contact with the top surface of the initial semiconductor pillar (20);

Remove part of the initial sacrificial layer (24) to form the first sacrificial layer (23);

Remove part of the second sacrificial layer (25) to expose the top surface of the initial semiconductor pillar (20);

The top surface of the initial semiconductor pillar (20) is etched to form the semiconductor pillar (10).
The method for preparing a semiconductor structure according to claim 10, further comprising: forming a first dielectric layer (104), the first dielectric layer (104) being adjacent in a direction perpendicular to the substrate (100) between the word line (101) and the conductive layer (102).
The method of preparing a semiconductor structure according to claim 13, wherein the material of the first dielectric layer (104) includes: low-k dielectric quality materials.
The method for preparing a semiconductor structure according to claim 10, wherein a plurality of the semiconductor pillars (10) arranged in an array are provided on the surface of the substrate (100), and the plurality of semiconductor pillars (10) are in the same layer. It is configured that the word line (101) covers part of the side surfaces of the semiconductor pillars (10) of each channel region (11) in a row of semiconductor pillars (10) arranged along the first direction (X) to form the word line (101) methods include:

An isolation structure (29) is formed, the isolation structure (29) is located between the adjacent semiconductor pillars (10) along the first direction (X), and covers the channel region (11) semiconductor pillar ( 10) Side;

Etch the top surface of the isolation structure (29) between adjacent semiconductor pillars (10) until the isolation structure (29) has a preset thickness;

A word line (101) is formed on the top surface and part of the side surface of the semiconductor pillar (10) of the channel region (11).