CN219437502U

CN219437502U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Info

Publication number: CN219437502U
Application number: CN202320072771.6U
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2023-07-28
Anticipated expiration: 2033-01-10

Abstract

The utility model discloses a semiconductor device, which comprises a substrate, a capacitor structure and a supporting structure. The capacitor structure is arranged on the substrate and comprises a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein the top of each columnar bottom electrode is provided with a groove, and the capacitor dielectric layer fills the grooves. The support structure is arranged between the adjacent columnar bottom electrodes and comprises a first support layer and a second support layer which are sequentially arranged from bottom to top. Therefore, the adhesiveness between the columnar bottom electrode and the dielectric material can be enhanced through the capacitor dielectric layer, so that the semiconductor device has a more stable and reliable structure, and relatively optimized device performance is achieved.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The present utility model relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor memory device and a method for fabricating the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor devices must meet the requirements of high integration and high density. For the DRAM (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the DRAM with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of capacitor structure. In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to form an array region for storing information, and each memory cell may be formed by a transistor element and a capacitor element connected in series to receive voltage information from Word Lines (WL) and Bit Lines (BL). In response to the product requirement, the density of the memory cells in the array region should be continuously increased, which causes the difficulty and complexity of the related manufacturing process and design to be continuously increased. Accordingly, the prior art or structure is further improved to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

It is an object of the present utility model to provide a semiconductor device in which a recess is formed in a pillar-shaped bottom electrode, and a subsequently formed capacitor dielectric layer is filled in the recess, so that adhesion between a metal (the pillar-shaped bottom electrode) and a dielectric material (the capacitor dielectric layer) is enhanced, and a probability of peeling the capacitor dielectric layer from a capacitor structure is reduced, so that the semiconductor device has a more stable and reliable structure and a relatively optimized device performance is achieved.

It is an object of the present utility model to provide a semiconductor device in which a recess is formed in a pillar-shaped bottom electrode, and a capacitor dielectric layer is filled in the recess, so that adhesion between a metal (the pillar-shaped bottom electrode) and a dielectric material (the capacitor dielectric layer) is enhanced, and the probability of peeling of the capacitor dielectric layer from a capacitor structure is reduced, thereby enabling the semiconductor device to have a more stable and reliable structure and achieving relatively optimized device performance.

To achieve the above object, one embodiment of the present utility model provides a semiconductor device including a substrate, a capacitor structure, and a support structure. The capacitor structure is arranged on the substrate and comprises a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein a groove is formed in the top of each columnar bottom electrode, and the capacitor dielectric layer fills the groove. The support structure is arranged between the adjacent columnar bottom electrodes and comprises a first support layer and a second support layer which are sequentially arranged from bottom to top.

In order to achieve the above object, one embodiment of the present utility model provides a method for manufacturing a semiconductor device, which includes the following steps. First, a substrate is provided, and a capacitor structure is formed on the substrate, wherein the capacitor structure comprises a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, a groove is formed on the top of each columnar bottom electrode, and the capacitor dielectric layer fills the groove. Then, a supporting structure is formed between the adjacent columnar bottom electrodes, and the supporting structure comprises a first supporting layer and a second supporting layer which are sequentially arranged from bottom to top.

Drawings

The accompanying drawings provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 10 are schematic views illustrating steps of a method for fabricating a semiconductor device according to an embodiment of the utility model, wherein:

fig. 1 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a storage node pad;

fig. 2 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a support layer structure;

fig. 3 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a dielectric material layer;

fig. 4 is a schematic cross-sectional view of a semiconductor device of the present utility model after formation of a dielectric layer;

fig. 5 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a bottom electrode layer;

fig. 6 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a mask layer;

fig. 7 is a schematic cross-sectional view of the semiconductor device of the present utility model after removing the third support material layer;

fig. 8 is a schematic cross-sectional view of the semiconductor device of the present utility model after removing the first support material layer;

fig. 9 is a schematic cross-sectional view of a semiconductor device of the present utility model after formation of a capacitive dielectric layer; and

fig. 10 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a top electrode layer.

Wherein reference numerals are as follows:

100. substrate and method for manufacturing the same

101. Shallow trench isolation

103. Active region

110. Dielectric layer

111. Oxide layer

113. Nitride layer

115. Oxide layer

120. Bit line

120a bit line contact

121. Semiconductor layer

123. Barrier layer

125. Conductive layer

127. Cover layer

130. Plug-in connector

140. Spacer structure

141. First spacer

143. Second spacer

145. Third spacer

150. Dielectric layer

151. Storage node bonding pad

160. Insulating layer

170. Supporting layer structure

171. A first support material layer

172. 172a opening

173. A second supporting material layer

175. A third supporting material layer

177. Fourth support material layer

179. Fifth supporting material layer

180. Dielectric material layer

181. High dielectric coefficient dielectric layer

190. Bottom electrode layer

191. Columnar bottom electrode

193. Capacitor dielectric layer

193a first dielectric layer

193b second dielectric layer

195. Top electrode layer

200. Mask pattern

270. Supporting structure

273. A first supporting layer

277. A second supporting layer

290. Capacitor structure

300. Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

R1 groove

Detailed Description

The following description sets forth the preferred embodiments of the present utility model and, together with the accompanying drawings, provides a further understanding of the utility model, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the utility model pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the utility model to accomplish other embodiments.

Referring to fig. 1 to 10, a schematic diagram of steps of a method for manufacturing a semiconductor device 300 according to an embodiment of the utility model is shown. First, as shown in fig. 1, a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., siC, siGe, etc.), or a silicon-on-insulator (SOI) substrate, is provided, at least one insulating region, such as a shallow trench isolation (shallow trench isolation, STI) 101, is formed in the substrate 100, and a plurality of Active Areas (AA) 103 are defined on the substrate 100, such that the shallow trench isolation 101 surrounds all of the active areas 103 from a top view (not shown). In one embodiment, the shallow trench isolation 101 is formed by, for example, etching a plurality of trenches (not shown) in the substrate 100, and then filling at least one insulating material (such as silicon oxide or silicon oxynitride) into the trenches to form the shallow trench isolation 101 with a surface level with the top surface of the substrate 100, but not limited thereto.

Next, a dielectric layer 110 is formed on the substrate 100, and the dielectric layer 110 preferably has a composite layer structure, for example, but not limited to, an oxide-nitride-oxide (ONO) structure including an oxide layer 111-a nitride layer 113-an oxide layer 115 sequentially stacked from bottom to top. Note that before forming the dielectric layer 110, a plurality of buried gates (not shown) are also formed in the substrate 100, such that the dielectric layer 110 covers the top surface of the buried gates. The buried gates extend in parallel to each other along a direction (e.g., x-direction, not shown) to serve as buried word lines (BWL, not shown) of the semiconductor device 300. On the other hand, a plurality of bit lines 120 and a plurality of plugs 130 are further formed over the substrate 100, wherein each bit line 120 extends parallel to each other in another direction (e.g., y-direction, not shown) perpendicular to the direction. Although the specific extending directions of the active region 103, the buried gate and the bit line 120 are not specifically shown in the drawings in this embodiment, it should be readily understood by those skilled in the art that the extending direction of the active region 103 is different from the extending direction of the word line and the bit line 120 when viewed from a top view (not shown), and the bit line 120 is perpendicular to the buried gate and simultaneously intersects the active region 103 and the buried gate.

In detail, each bit line 120 and the plug 130 are alternately arranged in a specific direction, and include, but not limited to, a semiconductor layer (e.g., including polysilicon) 121, a barrier layer 123 (e.g., including titanium and/or titanium nitride), a conductive layer 125 (e.g., including low-resistance metal such as tungsten, aluminum, or copper), and a cap layer 127 (e.g., including silicon oxide, silicon nitride, or silicon oxynitride). It should be noted that, in principle, all the bit lines 120 are formed on the dielectric layer 110 separately from each other and are staggered with the plurality of active regions 103, wherein the bit lines 120 falling on each active region 103 further extend into each active region 103 by Bit Line Contact (BLC) 120a correspondingly formed thereunder, as shown in fig. 1. That is, in the present embodiment, each bit line plug 120a is, for example, integrally formed with the semiconductor layer 121 of the bit line 120 and directly contacts the corresponding active region 103, but not limited thereto.

The plugs 130 are also formed on the substrate 100 separately from each other and directly contact the underlying substrate 100 (including the active region 103 and the shallow trench isolation 101), so that each plug 130 can serve as a storage node plug (storage node contact, SNC) of the semiconductor device 300 to receive or transmit a voltage signal from each memory cell. In one embodiment, the plugs 130 include low-resistance metal materials such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and the plugs 130 and the bit lines 120 are insulated from each other by spacer structures 140. In one embodiment, the spacer structure 140 may optionally have a single layer structure or a composite layer structure as shown in fig. 1, for example, but not limited to, a first spacer 141 (e.g., including silicon nitride), a second spacer 143 (e.g., including silicon oxide), and a third spacer 145 (e.g., including silicon nitride) sequentially stacked on the sidewalls of each bit line 120.

Referring to fig. 1 again, a dielectric layer 150 and a plurality of storage node pads (SN pads) 151 are further formed thereon, wherein the dielectric layer 150 integrally covers the plugs 130 and the bit lines 120, and each storage node pad 151 is formed in the dielectric layer 150 to be spaced apart from each other and has a top surface level with the top surface of the dielectric layer 150. Each storage node pad 151 contacts the underlying plug 130 and is electrically connected to each plug 130. In one embodiment, the storage node pads 151 also include low-resistance metal materials such as aluminum, titanium, copper, or tungsten, for example, which are different from the metal materials of the plugs 130, and the dielectric layer 150 includes dielectric materials such as silicon nitride, but is not limited thereto. In another embodiment, the storage node pads may alternatively be integrally formed with the plugs 130 and may comprise the same material.

As shown in fig. 2, an insulating layer 160 and a supporting layer structure 170 are sequentially formed on the dielectric layer 150, wherein the insulating layer 160 comprises an insulating material such as silicon oxide or silicon oxynitride, and the supporting layer structure 170 comprises at least one oxide layer and at least one nitride layer stacked alternately. In the present embodiment, the support layer structure 170 includes, but is not limited to, a first support material layer 171 (e.g., including silicon oxide), a second support material layer 173 (e.g., including silicon nitride or silicon carbonitride), a third support material layer 175 (e.g., including silicon oxide), a fourth support material layer 177 (e.g., including silicon nitride or silicon carbonitride), and a fifth support material layer 179 (e.g., including silicon oxide) stacked sequentially from bottom to top. Then, a plurality of openings 172 are formed in the support layer structure 170, and sequentially penetrate through the fifth support material layer 179, the fourth support material layer 177, the third support material layer 175, the second support material layer 173, the first support material layer 171 and the insulating layer 160, and align with each storage node pad 151 below, such that the top surface of each storage node pad 151 is exposed from each opening 172.

Preferably, the oxide layer (e.g., including the first support material layer 171 and the third support material layer 175) may have a relatively large thickness, for example, about 5 times to 10 times or more the thickness of the nitride layer (e.g., including the second support material layer 173 or the fourth support material layer 177), and the thickness of the nitride layer (e.g., the fourth support material layer 177) disposed away from the substrate 100 is preferably greater than the thickness of the nitride layer (e.g., the second support material layer 173) disposed adjacent to the substrate 100, as shown in fig. 2, but is not limited thereto. In the present embodiment, the thickness of the entire supporting layer structure 170 is about 1600 angstroms (angstrom) to about 2000 angstroms, but is not limited thereto. It should be understood by those skilled in the art that the specific number of stacked oxide layers (e.g., the first support material layer 171, or the third support material layer 175, or the fifth support material layer 179) and the nitride layers (e.g., the second support material layer 173, or the fourth support material layer 177) is not limited to the above number, but may be adjusted according to practical needs, such as 4 layers, 5 layers, or other numbers.

Next, as shown in fig. 3, a deposition process is performed to form a dielectric material layer 180 on the support layer structure 170. In detail, the dielectric material layer 180 is conformal and uniformly covers the top surface of the support layer structure 170, the surface of the opening 172 and the storage node pad 151, and includes, for example, a high-k dielectric material such as hafnium oxide (HfO) ₂ ) Hafnium silicate oxide (hafnium silicon oxide, hfSiO), hafnium silicate oxynitride (hafnium silicon oxynitride, hfSiON), aluminum oxide (Al) ₂ O ₃ ) Lanthanum oxide (LaO), lanthanum aluminate (lanthanum aluminum oxide, laAlO), tantalum oxide (Ta) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Yttrium oxide (Y) ₂ O ₃ ) Zirconium oxide, zrO ₂ ) Zirconium silicate oxide (zirconium silicon oxide, zrSiO) ₄ ) Hafnium zirconate (hafnium zirconium oxide, hfZrO), strontium bismuth tantalum oxide (strontium bismuth tantalate, srBi) ₂ Ta ₂ O ₉ SBT), lead zirconate titanate (Lead zirconate titanate, pbZrxTi _1-x O ₃ PZT) or barium strontium titanate (Barium Strontium Titanate, baxSr) _1-x TiO ₃ BST), etc., but not limited thereto.

As shown in fig. 4, an etching back process is performed on the dielectric material layer 180 to remove the dielectric material layer 180 covering the top surface of the support layer structure 170 and the storage node pads 151, forming a high-k dielectric layer 181 only on the sidewalls of the openings 172, exposing the top surface of the storage node pads 151. Then, an etching process, such as a dry etching process, is performed through the cover of the high-k dielectric layer 181, etching down a portion of the storage node pad 151 from the exposed top surface of the storage node pad 151, forming an opening 172a extending further into a portion of the storage node pad 151.

As shown in fig. 5, a deposition process is performed to form a bottom electrode layer 190 that fills each opening 172a and further overlies the top surface of the support layer structure 170. In one embodiment, the bottom electrode layer 190 includes a low-resistance metal material such as aluminum, titanium, copper or tungsten, preferably includes titanium, but is not limited thereto. Then, another etching back process is performed to remove the bottom electrode layer 190 covering the top surface of the support layer structure 170, thereby forming a plurality of columnar bottom electrodes 191 as shown in fig. 6. Thus, each of the column bottom electrodes 191 may have a vertically columnar structure that is bilaterally symmetrical. The bottom of the bottom electrode 191 is not level with the bottom surface of the high-k dielectric layer 181, but extends into part of the storage node pads 151 and directly contacts the storage node pads 151 to increase the contact area between the bottom electrode 191 and the storage node pads 151, and the top surface of the bottom electrode 191 is level with the top surface of the fifth supporting material layer 179 and the high-k dielectric layer 181.

Then, as shown in fig. 6 again. A plurality of mask patterns 200 are formed on the substrate 100 to cover a portion of the fifth support material layer 179 and a portion of the column-shaped bottom electrode 191. In detail, each mask pattern 200 covers the supporting layer structure 170 in such a way as to cover a portion of the top surfaces of two adjacent pillar-shaped bottom electrodes 191 and all the top surfaces of the fifth supporting material layer 179 therebetween, wherein about two-thirds to one-half of the top surfaces of two adjacent pillar-shaped bottom electrodes 191 are covered by the mask pattern 200 to expose at least about one-third to one-half of the top surfaces, but not limited thereto.

As shown in fig. 7, at least one etching process is performed through the mask pattern 200 to partially remove the support layer structure 170. In detail, in this embodiment, a first etching process, such as a dry etching process, is performed to remove a portion of the fifth support material layer 179 and the fourth support material layer 177 and the third support material layer 175 below the fifth support material layer 179 from the top surface of the fifth support material layer 179 not covered by the mask pattern 200, and then a second etching process, such as a wet etching process, is performed to remove the remaining portions of the fifth support material layer 179 and the third support material layer 175 laterally by introducing an etchant, such as tetramethylammonium hydroxide (tetramethylammonium hydroxide, TMAH). Thus, the fifth support material layer 179 and the third support material layer 175 of the support layer structure 170 can be completely removed.

In addition, it should be noted that, in the at least one etching process, the columnar bottom electrodes 191 not covered by the mask pattern 200 are further etched by adjusting the etching selection of the etching process, but the high-k dielectric layers 181 not covered by the mask pattern 200 are not etched, so that a groove R1 is etched on top of each columnar bottom electrode 191, which is sandwiched between the high-k dielectric layers 181 and each non-etched columnar bottom electrode 191. Wherein the lowest surface of each recess R1 is higher than the top surface of the fourth support material layer 177 and lower than the top surface of the high-k dielectric layer 181. In this embodiment, due to the aforementioned covering manner of the mask pattern 200, the recess R1 is formed only on the top of a single side of each pillar-shaped bottom electrode 191, so that the top of each pillar-shaped bottom electrode 191 presents a left-right asymmetric pattern, one side of each pillar-shaped bottom electrode having the recess does not contact the supporting structure, and two adjacent pillar-shaped bottom electrodes 191 can present mirror symmetry with each other, as shown in fig. 7, so as to facilitate enlarging the deposition space of the subsequently formed capacitor dielectric layer and top electrode layer.

As shown in fig. 8, a third etching process, such as a dry etching process, and a fourth etching process, such as an isotropic wet etching process, are sequentially performed through the mask pattern 200. The third etching process removes a portion of the second support material layer 173 and the first support material layer 171 downward from the top surface of the second support material layer 173 not covered by the mask pattern 200, and then, the etching agent such as tetramethyl ammonium hydroxide is introduced to laterally remove the remaining portion of the first support material layer 171 by using the fourth etching process.

It should be noted that, in the third etching process and the fourth etching process of the present embodiment, the etching selection of the foregoing etching process is preferably adjusted, but the top of each pillar-shaped bottom electrode 191 is not further etched, so that the lowest surface of each recess R1 is still located above the fourth supporting material layer 177 and below the top surface of the high-k dielectric layer 181, so as to avoid excessively large recess R1, but not limited thereto. In another embodiment, the same etching options as described above can also be optionally maintained, and the top of each pillar-shaped bottom electrode 191 is further etched by the third etching process and the fourth etching process, and the depth of the recess is amplified, so that the lowest surface of the recess is lowered to a position lower than the top surface of the fourth supporting material layer 177. In addition, since the high-k dielectric layer 181 covers the sidewalls of the columnar bottom electrode 191, the columnar bottom electrode 191 is further protected from the respective etching processes during the respective etching processes.

Then, as shown in fig. 9, the mask pattern 200 is completely removed, so that the remaining fourth supporting material layer 177 and the remaining second supporting material layer 173 respectively form a second supporting layer 277 and a first supporting layer 273 sequentially disposed from top to bottom, which are disposed on at least one sidewall of each pillar-shaped bottom electrode 191, to form the supporting structure 270 of the semiconductor device 300. Then, as further shown in fig. 9, at least one deposition process is performed on the support structure 270 to form a capacitor dielectric layer 193. In detail, the capacitor dielectric layer 193 includes a first dielectric layer 193a and a second dielectric layer 193b sequentially stacked, which are integrally covered on all exposed surfaces of the support structure 270, the pillar-shaped bottom electrode 191 and the high-k dielectric layer 181, wherein the first dielectric layer 193a further fills each recess R1. In this manner, the surfaces of the first support layer 273 and the second support layer 277 are covered with the high-permittivity dielectric layer 181 and the first dielectric layer 193a, respectively, and the first capacitor dielectric layer 193a covering the sidewalls of the columnar bottom electrode 191 directly contacts the high-permittivity dielectric layer 181.

In the present embodiment, the first dielectric layer 193a and the second dielectric layer 193b respectively include different dielectric materials with high dielectric coefficients, such as hafnium oxide, hafnium silicate oxynitride, aluminum oxide, lanthanum aluminate, tantalum oxide, titanium oxide, yttrium oxide, zirconium silicate oxide, hafnium zirconate, strontium bismuth tantalum oxide, lead zirconate titanate or barium strontium titanate, but not limited thereto. Preferably, the first dielectric layer 193a has a high dielectric coefficient dielectric material with good adhesion to a metal material, and the material selection of the first dielectric layer 193a and the second dielectric layer 193b is different from that of the high dielectric coefficient dielectric layer 181, but not limited thereto.

As shown in fig. 10, another deposition process is performed on the capacitor dielectric layer 193 to form a top electrode layer 195 filling the remaining space between the column-shaped bottom electrodes 191. Thus, the pillar-shaped bottom electrode 191, the capacitor dielectric layer 193, and the top electrode layer 195 may collectively form a capacitor structure 290. Wherein, part of the top electrode layer 195 may be further filled between the second supporting layer 277 and the first supporting layer 273, and at the same time, between the first supporting layer 273 and the insulating layer 160, so as to increase the contact area and increase the capacitance value. In one embodiment, the top electrode layer 195 includes a low resistance metal material such as aluminum, titanium, copper or tungsten, preferably, but not limited to, titanium.

Thus, the fabrication process of the capacitor structure 290 is completed. The capacitor structure 290 includes a plurality of capacitors extending vertically to serve as Storage Nodes (SN) of the semiconductor device 300, and the storage nodes can be electrically connected to transistor elements (not shown) of the semiconductor device 300 through the storage node pads 151 and the storage node plugs (i.e., plugs 130), so that the capacitor structure 290 and the storage node plugs disposed on the substrate 100 can have a good contact relationship. With this arrangement, the semiconductor device 300 of the present embodiment can form a dynamic random access memory (dynamic random access memory, DRAM) device, which is a minimum cell (memory cell) in a DRAM array formed by at least one of the transistor elements and at least one of the capacitors, for receiving voltage information from the bit line 120 and the buried word line.

According to the method of the present utility model, the high-k dielectric layer 181 and the pillar-shaped bottom electrode layer 191 are formed in the opening 172, the sidewall of the pillar-shaped bottom electrode layer 191 is protected from damage during the etching process by the high-k dielectric layer 181, and the adhesion between the pillar-shaped bottom electrode layer 191 and the subsequently formed capacitor dielectric layer 193 is improved, and in addition, the high-k dielectric material of the high-k dielectric layer 181 can further increase the capacitance. Moreover, the capacitor dielectric layer 193 is further filled into the recess R1 on top of the columnar bottom electrode layer 191, thereby further reducing the probability of the capacitor dielectric layer 193 peeling from the capacitor structure 290. Thus, in the manufacturing method of the present embodiment, the deposition process of the capacitor dielectric layer 193 and the top electrode layer 195 is performed more smoothly, so as to achieve the effect of simplifying the manufacturing process.

On the other hand, in the first etching process, the columnar bottom electrode layer 191 uncovered by the mask pattern 200 may also be selectively etched, so that the top portions of two adjacent columnar bottom electrodes 191 form opposite or opposite grooves R1. With this arrangement, the adjacent two columnar bottom electrodes 191 are mirror-symmetrical to each other, and the deposition space of the capacitor dielectric layer 193 to be formed later can be further enlarged. That is, the manufacturing method of the present embodiment enhances the adhesion between the pillar-shaped bottom electrode 191 and the capacitor dielectric layer 193 by the arrangement of the high-k dielectric layer 181 and the recess R1, and reduces the peeling probability of the capacitor dielectric layer 193 from the capacitor structure 290, so that the manufactured semiconductor device 300 has a more stable and reliable structure and achieves a relatively optimized device performance.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A semiconductor device characterized by comprising:

a substrate;

the capacitor structure is arranged on the substrate and comprises a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein a groove is formed in the top of each columnar bottom electrode, and the capacitor dielectric layer fills the groove; and

the support structure is arranged between the adjacent columnar bottom electrodes and comprises a first support layer and a second support layer which are sequentially arranged from bottom to top.

2. The semiconductor device of claim 1, wherein the capacitive dielectric layer comprises a first dielectric layer and a second dielectric layer stacked in sequence, wherein the first dielectric layer fills each of the recesses.

3. The semiconductor device of claim 2, wherein the first dielectric layer and the second dielectric layer are each different high permittivity dielectric materials.

4. The semiconductor device according to claim 2, further comprising:

and the high-dielectric-coefficient dielectric layers are arranged on two opposite side walls of each columnar bottom electrode, wherein a plurality of surfaces of the first supporting layer and the second supporting layer are respectively covered by the first dielectric layer and the high-dielectric-coefficient dielectric layers.

5. The semiconductor device according to claim 1, further comprising:

and a plurality of storage node pads disposed on the substrate and contacting each of the column-shaped bottom electrodes, respectively, wherein a portion of each of the column-shaped bottom electrodes extends into each of the storage node pads.

6. The semiconductor device of claim 1, wherein a lowermost surface of each of the grooves is higher than a top surface of the second support layer.

7. The semiconductor device according to claim 1, wherein a side of each of the columnar bottom electrodes having the recess does not contact the support structure.

8. The semiconductor device of claim 7, wherein adjacent two of said columnar bottom electrodes are mirror symmetric to each other.